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authorJosh Blum <josh@joshknows.com>2010-04-16 09:42:46 +0000
committerJosh Blum <josh@joshknows.com>2010-04-16 09:42:46 +0000
commit835cb56ef820a69e1e6e0ccde7c5a0e78ca5ad25 (patch)
tree4fe48bdaf92311deedfbe1a5e77dd209468a2d7d /fpga/usrp2/control_lib/setting_reg.v
parentf1838b9284a124fcfb5996eaf1647a69b4473278 (diff)
parent067491b58676cbdaa754334949a8ffc2daf32979 (diff)
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Merge branch 'master' of git@ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
Conflicts: .gitignore
Diffstat (limited to 'fpga/usrp2/control_lib/setting_reg.v')
-rw-r--r--fpga/usrp2/control_lib/setting_reg.v23
1 files changed, 23 insertions, 0 deletions
diff --git a/fpga/usrp2/control_lib/setting_reg.v b/fpga/usrp2/control_lib/setting_reg.v
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+
+
+module setting_reg
+ #(parameter my_addr = 0, parameter at_reset=32'd0)
+ (input clk, input rst, input strobe, input wire [7:0] addr,
+ input wire [31:0] in, output reg [31:0] out, output reg changed);
+
+ always @(posedge clk)
+ if(rst)
+ begin
+ out <= at_reset;
+ changed <= 1'b0;
+ end
+ else
+ if(strobe & (my_addr==addr))
+ begin
+ out <= in;
+ changed <= 1'b1;
+ end
+ else
+ changed <= 1'b0;
+
+endmodule // setting_reg