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authorJosh Blum <josh@joshknows.com>2010-04-16 09:42:46 +0000
committerJosh Blum <josh@joshknows.com>2010-04-16 09:42:46 +0000
commit835cb56ef820a69e1e6e0ccde7c5a0e78ca5ad25 (patch)
tree4fe48bdaf92311deedfbe1a5e77dd209468a2d7d /fpga/usrp2/control_lib/reset_sync.v
parentf1838b9284a124fcfb5996eaf1647a69b4473278 (diff)
parent067491b58676cbdaa754334949a8ffc2daf32979 (diff)
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Merge branch 'master' of git@ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
Conflicts: .gitignore
Diffstat (limited to 'fpga/usrp2/control_lib/reset_sync.v')
-rw-r--r--fpga/usrp2/control_lib/reset_sync.v16
1 files changed, 16 insertions, 0 deletions
diff --git a/fpga/usrp2/control_lib/reset_sync.v b/fpga/usrp2/control_lib/reset_sync.v
new file mode 100644
index 000000000..94d966840
--- /dev/null
+++ b/fpga/usrp2/control_lib/reset_sync.v
@@ -0,0 +1,16 @@
+
+
+module reset_sync
+ (input clk,
+ input reset_in,
+ output reg reset_out);
+
+ reg reset_int;
+
+ always @(posedge clk or posedge reset_in)
+ if(reset_in)
+ {reset_out,reset_int} <= 2'b11;
+ else
+ {reset_out,reset_int} <= {reset_int,1'b0};
+
+endmodule // reset_sync