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authorJosh Blum <josh@joshknows.com>2010-04-15 11:24:41 -0700
committerJosh Blum <josh@joshknows.com>2010-04-15 11:24:41 -0700
commit3a196c5d614fbec9b1010b3082245614ba5e0dc9 (patch)
tree784f075298f5d86c9e7429ce0ff977deaf4315c8 /fpga/usrp2/control_lib/gray_send.v
parentcbf7a0916f0455743d8446a8edc0f0775e3e63ed (diff)
parent05d77f772317de5d925301aa11bb9a880656dd05 (diff)
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Merge branch 'udp'
Diffstat (limited to 'fpga/usrp2/control_lib/gray_send.v')
-rw-r--r--fpga/usrp2/control_lib/gray_send.v29
1 files changed, 29 insertions, 0 deletions
diff --git a/fpga/usrp2/control_lib/gray_send.v b/fpga/usrp2/control_lib/gray_send.v
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index 000000000..7fc07d40c
--- /dev/null
+++ b/fpga/usrp2/control_lib/gray_send.v
@@ -0,0 +1,29 @@
+
+
+
+module gray_send
+ #(parameter WIDTH = 8)
+ (input clk_in, input [WIDTH-1:0] addr_in,
+ input clk_out, output reg [WIDTH-1:0] addr_out);
+
+ reg [WIDTH-1:0] gray_clkin, gray_clkout, gray_clkout_d1;
+ wire [WIDTH-1:0] gray, bin;
+
+ bin2gray #(.WIDTH(WIDTH)) b2g (.bin(addr_in), .gray(gray) );
+
+ always @(posedge clk_in)
+ gray_clkin <= gray;
+
+ always @(posedge clk_out)
+ gray_clkout <= gray_clkin;
+
+ always @(posedge clk_out)
+ gray_clkout_d1 <= gray_clkout;
+
+ gray2bin #(.WIDTH(WIDTH)) g2b (.gray(gray_clkout_d1), .bin(bin) );
+
+ // FIXME we may not need the next register, but it may help timing
+ always @(posedge clk_out)
+ addr_out <= bin;
+
+endmodule // gray_send