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| author | Josh Blum <josh@joshknows.com> | 2010-04-16 09:42:46 +0000 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-04-16 09:42:46 +0000 |
| commit | 835cb56ef820a69e1e6e0ccde7c5a0e78ca5ad25 (patch) | |
| tree | 4fe48bdaf92311deedfbe1a5e77dd209468a2d7d /fpga/usrp2/control_lib/cmdfile | |
| parent | f1838b9284a124fcfb5996eaf1647a69b4473278 (diff) | |
| parent | 067491b58676cbdaa754334949a8ffc2daf32979 (diff) | |
| download | uhd-835cb56ef820a69e1e6e0ccde7c5a0e78ca5ad25.tar.gz uhd-835cb56ef820a69e1e6e0ccde7c5a0e78ca5ad25.tar.bz2 uhd-835cb56ef820a69e1e6e0ccde7c5a0e78ca5ad25.zip | |
Merge branch 'master' of git@ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
Conflicts:
.gitignore
Diffstat (limited to 'fpga/usrp2/control_lib/cmdfile')
| -rw-r--r-- | fpga/usrp2/control_lib/cmdfile | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/fpga/usrp2/control_lib/cmdfile b/fpga/usrp2/control_lib/cmdfile new file mode 100644 index 000000000..cb3756cfc --- /dev/null +++ b/fpga/usrp2/control_lib/cmdfile @@ -0,0 +1,18 @@ +# My stuff +-y . +-y ../u2_basic +-y ../control_lib +-y ../sdr_lib + +# Models +-y ../models + +# Open Cores +-y ../opencores/spi/rtl/verilog ++incdir+../opencores/spi/rtl/verilog +-y ../opencores/wb_conbus/rtl/verilog ++incdir+../opencores/wb_conbus/rtl/verilog +-y ../opencores/i2c/rtl/verilog ++incdir+../opencores/i2c/rtl/verilog +-y ../opencores/aemb/rtl/verilog +-y ../opencores/simple_gpio/rtl |