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authorJosh Blum <josh@joshknows.com>2011-05-09 16:47:04 -0700
committerJosh Blum <josh@joshknows.com>2011-05-09 16:47:04 -0700
commit91e32eaea25b023ec33b0efc80a653dac5a676df (patch)
tree0b1841b9a95a8ff22e47ec48387decd4005ca8db /fpga/usrp2/control_lib/atr_controller.v
parent9daf1f0a7be5f6a2cc220e0c2f746e65dc649568 (diff)
parentd8aae182ffdafdd61bbd0100f845d7c93e6ec591 (diff)
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Merge branch 'next' into use_vita_length
Diffstat (limited to 'fpga/usrp2/control_lib/atr_controller.v')
-rw-r--r--fpga/usrp2/control_lib/atr_controller.v2
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp2/control_lib/atr_controller.v b/fpga/usrp2/control_lib/atr_controller.v
index fed2791f9..a161b5e00 100644
--- a/fpga/usrp2/control_lib/atr_controller.v
+++ b/fpga/usrp2/control_lib/atr_controller.v
@@ -7,7 +7,7 @@ module atr_controller
(input clk_i, input rst_i,
input [5:0] adr_i, input [3:0] sel_i, input [31:0] dat_i, output reg [31:0] dat_o,
input we_i, input stb_i, input cyc_i, output reg ack_o,
- input run_rx, input run_tx, input [31:0] master_time,
+ input run_rx, input run_tx,
output [31:0] ctrl_lines);
reg [3:0] state;