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| author | Josh Blum <josh@joshknows.com> | 2010-06-18 12:33:40 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-06-18 12:33:40 -0700 |
| commit | efbeb60d1dd7e870a48cf42df9a3650aefbf26cd (patch) | |
| tree | 12131942ff9f85f7776a864cb79120bab778d8f9 /fpga/usrp2/control_lib/Makefile.srcs | |
| parent | df80be9c61d95402976d3349acf62630044c1939 (diff) | |
| parent | edcc2df10ba59ed91ac9513c2dc1d36e155caaec (diff) | |
| download | uhd-efbeb60d1dd7e870a48cf42df9a3650aefbf26cd.tar.gz uhd-efbeb60d1dd7e870a48cf42df9a3650aefbf26cd.tar.bz2 uhd-efbeb60d1dd7e870a48cf42df9a3650aefbf26cd.zip | |
Merge branch 'uhd_fpga_merge' into pre_merge
Diffstat (limited to 'fpga/usrp2/control_lib/Makefile.srcs')
| -rw-r--r-- | fpga/usrp2/control_lib/Makefile.srcs | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/fpga/usrp2/control_lib/Makefile.srcs b/fpga/usrp2/control_lib/Makefile.srcs new file mode 100644 index 000000000..5e2a96a53 --- /dev/null +++ b/fpga/usrp2/control_lib/Makefile.srcs @@ -0,0 +1,44 @@ +# +# Copyright 2010 Ettus Research LLC +# + +################################################## +# Control Lib Sources +################################################## +CONTROL_LIB_SRCS = $(abspath $(addprefix $(BASE_DIR)/../control_lib/, \ +CRC16_D16.v \ +atr_controller.v \ +bin2gray.v \ +dcache.v \ +decoder_3_8.v \ +dpram32.v \ +gray2bin.v \ +gray_send.v \ +icache.v \ +mux4.v \ +mux8.v \ +nsgpio.v \ +ram_2port.v \ +ram_harv_cache.v \ +ram_loader.v \ +setting_reg.v \ +settings_bus.v \ +settings_bus_crossclock.v \ +srl.v \ +system_control.v \ +wb_1master.v \ +wb_readback_mux.v \ +simple_uart.v \ +simple_uart_tx.v \ +simple_uart_rx.v \ +oneshot_2clk.v \ +sd_spi.v \ +sd_spi_wb.v \ +wb_bridge_16_32.v \ +reset_sync.v \ +priority_enc.v \ +pic.v \ +longfifo.v \ +shortfifo.v \ +medfifo.v \ +)) |