Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>

7 files changed, 206 insertions, 0 deletions

diff --git a/fpga/usrp2/boot_cpld/.gitignore b/fpga/usrp2/boot_cpld/.gitignore
new file mode 100644
index 000000000..45cf9a86b
--- /dev/null
+++ b/fpga/usrp2/boot_cpld/.gitignore
@@ -0,0 +1,38 @@
+/*_xdb
+/*.restore
+/*.xrpt
+/*.zip
+/xst
+/_ngo
+/_xmsgs
+/*.log
+/*.stx
+/*.tspec
+/*.xml
+/*.gyd
+/*.ngr
+/*.tim
+/*.err
+/*.lso
+/*.bld
+/*.cmd_log
+/*.ise_ISE_Backup
+/*.ipf_ISE_Backup
+/*.mfd
+/*.vm6
+/*.syr
+/*.xst
+/*.csv
+/*.html
+/*.jed
+/*.pad
+/*.ng*
+/*.pnx
+/*.rpt
+/*.prj
+/*_html
+/*.cel
+/_pace.ucf
+/*.lock
+/*.tfi
+/templates
diff --git a/fpga/usrp2/boot_cpld/_impact.cmd b/fpga/usrp2/boot_cpld/_impact.cmd
new file mode 100755
index 000000000..a55b6b892
--- /dev/null
+++ b/fpga/usrp2/boot_cpld/_impact.cmd
@@ -0,0 +1,34 @@
+loadProjectFile -file "C:\cygwin\home\matt\usrp2\fpga\boot_cpld/boot_cpld.ipf"
+setMode -ss
+setMode -sm
+setMode -hw140
+setMode -spi
+setMode -acecf
+setMode -acempm
+setMode -pff
+setMode -bs
+setMode -bs
+setMode -bs
+setMode -bs
+setCable -port auto
+Identify 
+identifyMPM 
+assignFile -p 1 -file "C:/cygwin/home/matt/usrp2/fpga/boot_cpld/boot_cpld.jed"
+Program -p 1 -e -v -defaultVersion 0 
+Program -p 1 -e -v -defaultVersion 0 
+Program -p 1 -e -v -defaultVersion 0 
+Program -p 1 -e -v -defaultVersion 0 
+Program -p 1 -e -v -defaultVersion 0 
+Program -p 1 -e -v -defaultVersion 0 
+Identify 
+identifyMPM 
+Identify 
+identifyMPM 
+Identify 
+identifyMPM 
+Identify 
+identifyMPM 
+Identify 
+identifyMPM 
+setMode -bs
+deleteDevice -position 1
diff --git a/fpga/usrp2/boot_cpld/boot_cpld.ipf b/fpga/usrp2/boot_cpld/boot_cpld.ipf
new file mode 100755
index 000000000..8acb6821e
--- /dev/null
+++ b/fpga/usrp2/boot_cpld/boot_cpld.ipf
diff --git a/fpga/usrp2/boot_cpld/boot_cpld.ise b/fpga/usrp2/boot_cpld/boot_cpld.ise
new file mode 100755
index 000000000..7252d3768
--- /dev/null
+++ b/fpga/usrp2/boot_cpld/boot_cpld.ise
diff --git a/fpga/usrp2/boot_cpld/boot_cpld.lfp b/fpga/usrp2/boot_cpld/boot_cpld.lfp
new file mode 100755
index 000000000..e057c4977
--- /dev/null
+++ b/fpga/usrp2/boot_cpld/boot_cpld.lfp
@@ -0,0 +1,5 @@
+# begin LFP file C:\cygwin\home\matt\u2f\boot_cpld\boot_cpld.lfp
+designfile boot_cpld.v
+parttype xc9572xl-vq44-10
+bus_delimiter 0;
+set_busdelim_onsave 1;
diff --git a/fpga/usrp2/boot_cpld/boot_cpld.ucf b/fpga/usrp2/boot_cpld/boot_cpld.ucf
new file mode 100755
index 000000000..94b550459
--- /dev/null
+++ b/fpga/usrp2/boot_cpld/boot_cpld.ucf
@@ -0,0 +1,34 @@
+NET "CLK_25MHZ"  LOC = "P5"  ; 
+NET "CLK_25MHZ_EN"  LOC = "P6"  ; 
+NET "LED<0>"  LOC = "P12"  ; 
+NET "LED<1>"  LOC = "P8"  ; 
+NET "LED<2>"  LOC = "P7"  ; 
+NET "DEBUG<0>"  LOC = "P1"  ; 
+NET "DEBUG<1>"  LOC = "P2"  ; 
+NET "DEBUG<2>"  LOC = "P3"  ; 
+NET "DEBUG<3>"  LOC = "P29"  ; 
+NET "DEBUG<4>"  LOC = "P30"  ; 
+NET "DEBUG<5>"  LOC = "P31"  ; 
+NET "DEBUG<6>"  LOC = "P32"  ; 
+NET "DEBUG<7>"  LOC = "P33"  ; 
+NET "DEBUG<8>"  LOC = "P34"  ; 
+NET "POR"  LOC = "P42"  ; 
+NET "SD_nCS"  LOC = "P20"  ; 
+NET "SD_Din"  LOC = "P21"  ; 
+NET "SD_CLK"  LOC = "P22"  ; 
+NET "SD_Dout"  LOC = "P23"  ; 
+NET "SD_DAT1"  LOC = "P27"  ; 
+NET "SD_DAT2"  LOC = "P28"  ; 
+NET "SD_prot"  LOC = "P19"  ;
+NET "SD_det"  LOC = "P36"  ;
+NET "CFG_INIT_B"  LOC = "P38"  ; 
+NET "CFG_Din"  LOC = "P37"  ; 
+NET "CFG_CCLK"  LOC = "P41"  ; 
+NET "CFG_DONE"  LOC = "P40"  ; 
+NET "CFG_PROG_B"  LOC = "P39"  ; 
+NET "CPLD_CLK"  LOC = "P13"  ; 
+NET "START"  LOC = "P14"  ;
+NET "MODE"  LOC = "P18"  ;
+NET "DONE"  LOC = "P16"  ;
+NET "detached"  LOC = "P43"  ;
+NET "CPLD_misc"  LOC = "P44"  ;
diff --git a/fpga/usrp2/boot_cpld/boot_cpld.v b/fpga/usrp2/boot_cpld/boot_cpld.v
new file mode 100755
index 000000000..2ffc6daed
--- /dev/null
+++ b/fpga/usrp2/boot_cpld/boot_cpld.v
@@ -0,0 +1,95 @@
+`timescale 1ns / 1ps
+// ////////////////////////////////////////////////////////////////////////////////
+// Boot CPLD design, only for u2_rev2
+// ////////////////////////////////////////////////////////////////////////////////
+
+module boot_cpld
+  (input CLK_25MHZ,
+   output CLK_25MHZ_EN,
+   output [2:0] LED,
+   output [8:0] DEBUG,
+   input 	 POR,
+   
+   // To SD Card
+   output 	 SD_nCS,
+   output 	 SD_Din,
+   output 	 SD_CLK,
+   input 	 SD_Dout,
+   input 	 SD_DAT1,  // Unused
+   input 	 SD_DAT2,  // Unused
+   input         SD_prot,  // Write Protect
+   input         SD_det,   // Card Detect
+   
+   // To FPGA Config Interface
+   input 	 CFG_INIT_B,
+   output 	 CFG_Din,     // Also used in Data interface
+   output 	 CFG_CCLK,
+   input 	 CFG_DONE,
+   output 	 CFG_PROG_B,
+   
+   // To FPGA data interface
+   output 	 CPLD_CLK,
+   input 	 START,
+   input 	 MODE,
+   input 	 DONE,
+   output 	 detached,
+   input         CPLD_misc   // Unused for now
+   );
+   
+   assign 	 CLK_25MHZ_EN = 1'b1;
+   
+   assign 	 LED[0] = ~CFG_DONE;
+   assign 	 LED[1] = CFG_INIT_B;
+   assign 	 LED[2] = ~CFG_PROG_B;
+   			
+   wire 	 en_outs;
+   wire [3:0] 	 set_sel = 4'd0;
+   
+   assign 	 CPLD_CLK = CFG_CCLK;
+   assign 	 DEBUG[8:0] = { CLK_25MHZ, SD_nCS, SD_CLK, SD_Din, SD_Dout, 
+				START, MODE, DONE, CPLD_misc};
+
+   // Handle cutover to FPGA control of SD
+   wire 	 fpga_takeover = ~CPLD_misc;
+   wire 	 SD_CLK_int, SD_nCS_int, SD_Din_int, CFG_Din_int;
+
+   assign 	 SD_CLK = fpga_takeover ? START : SD_CLK_int;
+   assign 	 SD_nCS = fpga_takeover ? MODE : SD_nCS_int;
+   assign 	 SD_Din = fpga_takeover ? DONE : SD_Din_int;
+   assign 	 CFG_Din = fpga_takeover ? SD_Dout : CFG_Din_int;
+
+   spi_boot #(.width_set_sel_g(4),  // How many sets (16)
+	      .width_bit_cnt_g(6),  // Block length (12 is faster, 6 is minimum)
+	      .width_img_cnt_g(2),  // How many images per set
+	      .num_bits_per_img_g(20), // Image size, 20 = 1MB
+	      .sd_init_g(1),           // SD-specific initialization
+	      .mmc_compat_clk_div_g(0),// No MMC support
+	      .width_mmc_clk_div_g(0), // No MMC support
+	      .reset_level_g(0))       // Active low reset
+     
+     spi_boot(.clk_i(CLK_25MHZ), 
+	      .reset_i(POR),
+	      
+	      // To SD Card
+	      .spi_clk_o(SD_CLK_int), 
+	      .spi_cs_n_o(SD_nCS_int),
+	      .spi_data_in_i(SD_Dout), 
+	      .spi_data_out_o(SD_Din_int), 
+	      .spi_en_outs_o(en_outs), 
+	      
+	      // Data Port
+	      .start_i(START),
+	      .mode_i(MODE), // 0->conf mode, 1->data mode  
+	      .detached_o(detached), 
+	      .dat_done_i(DONE), 
+	      .set_sel_i(set_sel),
+	      
+	      // To FPGA
+	      .config_n_o(CFG_PROG_B), 
+	      .cfg_init_n_i(CFG_INIT_B), 
+	      .cfg_done_i(CFG_DONE), 
+	      .cfg_clk_o(CFG_CCLK), 
+	      .cfg_dat_o(CFG_Din_int)
+	      );
+   
+endmodule // boot_cpld