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author | Martin Braun <martin.braun@ettus.com> | 2021-12-08 15:00:57 +0100 |
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committer | Aaron Rossetto <aaron.rossetto@ni.com> | 2021-12-09 13:10:00 -0800 |
commit | ece958327caf4db4daee79ac2d3935bae3e1e87c (patch) | |
tree | b2b65752f154dcd1e36735fb619544cf136b511a /fpga/usrp1 | |
parent | f308a453c4e615143a467869accf550ab36493c7 (diff) | |
download | uhd-ece958327caf4db4daee79ac2d3935bae3e1e87c.tar.gz uhd-ece958327caf4db4daee79ac2d3935bae3e1e87c.tar.bz2 uhd-ece958327caf4db4daee79ac2d3935bae3e1e87c.zip |
tests: Add replay-back-edge test
This tests the following graph: DDC -> Replay -> DDC, where the initial
and final blocks are the same (i.e., a loop). This could be useful for
generating and capturing data with the same replay block while testing
a block.
Note that this test will fail if the edge consistency checks are buggy.
Diffstat (limited to 'fpga/usrp1')
0 files changed, 0 insertions, 0 deletions