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| author | Nick Foster <nick@ettus.com> | 2012-03-16 11:26:34 -0700 |
|---|---|---|
| committer | Nick Foster <nick@ettus.com> | 2012-03-16 11:27:39 -0700 |
| commit | 63991f7922a4e20888f001b802a8d8c88a8a16ee (patch) | |
| tree | 0026d0cb7a615a66c6dc90826d58015efe0a22ed /fpga/usrp1/toplevel | |
| parent | f91e247da23c09626cf215a7cede145b09376575 (diff) | |
| download | uhd-63991f7922a4e20888f001b802a8d8c88a8a16ee.tar.gz uhd-63991f7922a4e20888f001b802a8d8c88a8a16ee.tar.bz2 uhd-63991f7922a4e20888f001b802a8d8c88a8a16ee.zip | |
B100: enable_gpif(0) disables FIFO output clock on FX2. this prevents the "stuffing zeroes" problem and improves transport reliability.
Diffstat (limited to 'fpga/usrp1/toplevel')
0 files changed, 0 insertions, 0 deletions