moved usrp1 and usrp2 fpga dirs into fpga subdirectory

8 files changed, 1664 insertions, 0 deletions

diff --git a/fpga/usrp1/toplevel/usrp_multi/.gitignore b/fpga/usrp1/toplevel/usrp_multi/.gitignore
new file mode 100644
index 000000000..2cc25f0f2
--- /dev/null
+++ b/fpga/usrp1/toplevel/usrp_multi/.gitignore
@@ -0,0 +1,16 @@
+/*.qws
+/*.eqn
+/*.done
+/*.htm
+/*.rpt
+/*.ini
+/*.fsf
+/*.jam
+/*.jbc
+/*.pin
+/*.pof
+/*.sof
+/*.rbf
+/*.ttf
+/*.summary
+/db
diff --git a/fpga/usrp1/toplevel/usrp_multi/config.vh b/fpga/usrp1/toplevel/usrp_multi/config.vh
new file mode 100644
index 000000000..07011bd48
--- /dev/null
+++ b/fpga/usrp1/toplevel/usrp_multi/config.vh
@@ -0,0 +1,62 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2006,2007 Matt Ettus
+//  Copyright (C) 2006 Martin Dudok van Heel
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+// ====================================================================
+//            User control over what parts get included
+//
+//                  >>>> EDIT ONLY THIS SECTION <<<<
+//                  Uncomment only ONE configuration
+// ====================================================================
+
+// ====================================================================
+// FIXME drive configuration selection from the command line and/or gui
+// ====================================================================
+
+`define MULTI_ON		// enable multi usrp configuration
+
+// Uncomment this for 1 rx channel (w/ halfband) & 1 transmit channel
+//`include "../include/common_config_1rxhb_1tx.vh"
+
+// Uncomment this for multi with 2 rx channels (w/ halfband) & 2 transmit channels
+`include "../include/common_config_2rxhb_2tx.vh"
+
+// Uncomment this for multi with 4 rx channels (w/o halfband) & 0 transmit channels
+//`include "../include/common_config_4rx_0tx.vh"
+
+// Uncomment this for multi with 2 rx channels (w/ halfband) & 0 transmit channels
+//`include "../include/common_config_2rxhb_0tx.vh"
+
+// Uncomment this for multi with 2 rx channels (w/o halfband) & 0 transmit channels
+//`include "../include/common_config_2rx_0tx.vh"
+
+
+// Add other "known to fit" configurations here...
+
+// ====================================================================
+//  Now include the common footer
+// ====================================================================
+
+`ifdef MULTI_ON
+  `define COUNTER_32BIT_ON
+`endif
+
+`include "../include/common_config_bottom.vh"
diff --git a/fpga/usrp1/toplevel/usrp_multi/usrp_multi.csf b/fpga/usrp1/toplevel/usrp_multi/usrp_multi.csf
new file mode 100644
index 000000000..2f5df2bca
--- /dev/null
+++ b/fpga/usrp1/toplevel/usrp_multi/usrp_multi.csf
@@ -0,0 +1,444 @@
+COMPILER_SETTINGS
+{
+	IO_PLACEMENT_OPTIMIZATION = OFF;
+	ENABLE_DRC_SETTINGS = OFF;
+	PHYSICAL_SYNTHESIS_REGISTER_RETIMING = OFF;
+	PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION = OFF;
+	PHYSICAL_SYNTHESIS_COMBO_LOGIC = OFF;
+	DRC_FANOUT_EXCEEDING = 30;
+	DRC_REPORT_FANOUT_EXCEEDING = OFF;
+	DRC_TOP_FANOUT = 50;
+	DRC_REPORT_TOP_FANOUT = OFF;
+	RUN_DRC_DURING_COMPILATION = OFF;
+	ADV_NETLIST_OPT_RETIME_CORE_AND_IO = ON;
+	ADV_NETLIST_OPT_SYNTH_USE_FITTER_INFO = OFF;
+	ADV_NETLIST_OPT_SYNTH_GATE_RETIME = OFF;
+	ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP = OFF;
+	SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES = OFF;
+	MERGE_HEX_FILE = OFF;
+	TRUE_WYSIWYG_FLOW = OFF;
+	SEED = 1;
+	FINAL_PLACEMENT_OPTIMIZATION = AUTOMATICALLY;
+	FAMILY = Cyclone;
+	DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
+	DPRAM_32BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1";
+	DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1";
+	DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
+	DPRAM_32BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "LOWER TO 1ESB UPPER TO 1";
+	DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "MEGALAB COLUMN 1";
+	DPRAM_DUAL_PORT_MODE_INPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
+	DPRAM_32BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1";
+	DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1";
+	DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
+	DPRAM_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
+	DPRAM_WIDE_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3";
+	DPRAM_DEEP_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3";
+	DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB";
+	DPRAM_SINGLE_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB";
+	DPRAM_WIDE_MODE_OUTPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4ESB";
+	DPRAM_DEEP_MODE_OUTPUT_EPXA4_10 = "MEGALAB COLUMN 3";
+	DPRAM_DUAL_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
+	DPRAM_SINGLE_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
+	DPRAM_WIDE_MODE_INPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4";
+	DPRAM_DEEP_MODE_INPUT_EPXA4_10 = "MEGALAB COLUMN 3";
+	DPRAM_OTHER_SIGNALS_EPXA4_10 = "DEFAULT OTHER ROUTING OPTIONS";
+	DPRAM_OUTPUT_EPXA4_10 = "DEFAULT OUTPUT ROUTING OPTIONS";
+	DPRAM_INPUT_EPXA4_10 = "DEFAULT INPUT ROUTING OPTIONS";
+	STRIPE_TO_PLD_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2";
+	PLD_TO_STRIPE_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2";
+	PROCESSOR_DEBUG_EXTENSIONS_EPXA4_10 = "MEGALAB COLUMN 2";
+	STRIPE_TO_PLD_BRIDGE_EPXA4_10 = "MEGALAB COLUMN 1";
+	FAST_FIT_COMPILATION = OFF;
+	SIGNALPROBE_DURING_NORMAL_COMPILATION = OFF;
+	OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING = ON;
+	OPTIMIZE_TIMING = "NORMAL COMPILATION";
+	OPTIMIZE_HOLD_TIMING = OFF;
+	COMPILATION_LEVEL = FULL;
+	SAVE_DISK_SPACE = OFF;
+	SPEED_DISK_USAGE_TRADEOFF = NORMAL;
+	LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT = OFF;
+	SIGNALPROBE_ALLOW_OVERUSE = OFF;
+	FOCUS_ENTITY_NAME = |usrp_multi;
+	ROUTING_BACK_ANNOTATION_MODE = OFF;
+	INC_PLC_MODE = OFF;
+	FIT_ONLY_ONE_ATTEMPT = OFF;
+}
+DEFAULT_DEVICE_OPTIONS
+{
+	GENERATE_CONFIG_HEXOUT_FILE = OFF;
+	GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON;
+	GENERATE_CONFIG_JBC_FILE = OFF;
+	GENERATE_CONFIG_JAM_FILE = OFF;
+	GENERATE_CONFIG_ISC_FILE = OFF;
+	GENERATE_CONFIG_SVF_FILE = OFF;
+	GENERATE_JBC_FILE_COMPRESSED = ON;
+	GENERATE_JBC_FILE = OFF;
+	GENERATE_JAM_FILE = OFF;
+	GENERATE_ISC_FILE = OFF;
+	GENERATE_SVF_FILE = OFF;
+	RESERVE_PIN = "AS INPUT TRI-STATED";
+	RESERVE_ALL_UNUSED_PINS = "AS OUTPUT DRIVING GROUND";
+	HEXOUT_FILE_COUNT_DIRECTION = UP;
+	HEXOUT_FILE_START_ADDRESS = 0;
+	GENERATE_HEX_FILE = OFF;
+	GENERATE_RBF_FILE = OFF;
+	GENERATE_TTF_FILE = OFF;
+	RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+	RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED";
+	RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+	RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+	RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+	DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF;
+	AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON;
+	EPROM_USE_CHECKSUM_AS_USERCODE = OFF;
+	FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+	MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+	STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+	APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+	STRATIX_CONFIGURATION_DEVICE = AUTO;
+	CYCLONE_CONFIGURATION_DEVICE = AUTO;
+	FLEX10K_CONFIGURATION_DEVICE = AUTO;
+	FLEX6K_CONFIGURATION_DEVICE = AUTO;
+	MERCURY_CONFIGURATION_DEVICE = AUTO;
+	EXCALIBUR_CONFIGURATION_DEVICE = AUTO;
+	APEX20K_CONFIGURATION_DEVICE = AUTO;
+	USE_CONFIGURATION_DEVICE = ON;
+	ENABLE_INIT_DONE_OUTPUT = OFF;
+	FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
+	ENABLE_DEVICE_WIDE_OE = OFF;
+	ENABLE_DEVICE_WIDE_RESET = OFF;
+	RELEASE_CLEARS_BEFORE_TRI_STATES = OFF;
+	AUTO_RESTART_CONFIGURATION = OFF;
+	ENABLE_VREFB_PIN = OFF;
+	ENABLE_VREFA_PIN = OFF;
+	SECURITY_BIT = OFF;
+	USER_START_UP_CLOCK = OFF;
+	APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+	FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+	FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+	MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+	EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+	CYCLONE_CONFIGURATION_SCHEME = "ACTIVE SERIAL";
+	STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+	APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+	STRATIX_UPDATE_MODE = STANDARD;
+	USE_CHECKSUM_AS_USERCODE = OFF;
+	MAX7000_USE_CHECKSUM_AS_USERCODE = OFF;
+	MAX7000_JTAG_USER_CODE = FFFFFFFF;
+	FLEX10K_JTAG_USER_CODE = 7F;
+	MERCURY_JTAG_USER_CODE = FFFFFFFF;
+	APEX20K_JTAG_USER_CODE = FFFFFFFF;
+	STRATIX_JTAG_USER_CODE = FFFFFFFF;
+	MAX7000S_JTAG_USER_CODE = FFFF;
+	RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+	FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
+	FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF;
+	ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
+	MAX7000_ENABLE_JTAG_BST_SUPPORT = ON;
+	ENABLE_JTAG_BST_SUPPORT = OFF;
+	CONFIGURATION_CLOCK_DIVISOR = 1;
+	CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ";
+	CLOCK_SOURCE = INTERNAL;
+	COMPRESSION_MODE = OFF;
+	ON_CHIP_BITSTREAM_DECOMPRESSION = OFF;
+}
+AUTO_SLD_HUB_ENTITY
+{
+	AUTO_INSERT_SLD_HUB_ENTITY = ENABLE;
+	HUB_INSTANCE_NAME = SLD_HUB_INST;
+	HUB_ENTITY_NAME = SLD_HUB;
+}
+SIGNALTAP_LOGIC_ANALYZER_SETTINGS
+{
+	ENABLE_SIGNALTAP = Off;
+	AUTO_ENABLE_SMART_COMPILE = On;
+}
+CHIP(usrp_multi)
+{
+	DEVICE = EP1C12Q240C8;
+	DEVICE_FILTER_PACKAGE = "ANY QFP";
+	DEVICE_FILTER_PIN_COUNT = 240;
+	DEVICE_FILTER_SPEED_GRADE = ANY;
+	AUTO_RESTART_CONFIGURATION = OFF;
+	RELEASE_CLEARS_BEFORE_TRI_STATES = OFF;
+	USER_START_UP_CLOCK = OFF;
+	ENABLE_DEVICE_WIDE_RESET = OFF;
+	ENABLE_DEVICE_WIDE_OE = OFF;
+	ENABLE_INIT_DONE_OUTPUT = OFF;
+	FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
+	ENABLE_JTAG_BST_SUPPORT = OFF;
+	MAX7000_ENABLE_JTAG_BST_SUPPORT = ON;
+	APEX20K_JTAG_USER_CODE = FFFFFFFF;
+	MERCURY_JTAG_USER_CODE = FFFFFFFF;
+	FLEX10K_JTAG_USER_CODE = 7F;
+	MAX7000_JTAG_USER_CODE = FFFFFFFF;
+	MAX7000S_JTAG_USER_CODE = FFFF;
+	STRATIX_JTAG_USER_CODE = FFFFFFFF;
+	APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+	MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+	FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+	FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+	EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+	APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+	STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+	CYCLONE_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+	USE_CONFIGURATION_DEVICE = OFF;
+	APEX20K_CONFIGURATION_DEVICE = AUTO;
+	MERCURY_CONFIGURATION_DEVICE = AUTO;
+	FLEX6K_CONFIGURATION_DEVICE = AUTO;
+	FLEX10K_CONFIGURATION_DEVICE = AUTO;
+	EXCALIBUR_CONFIGURATION_DEVICE = AUTO;
+	STRATIX_CONFIGURATION_DEVICE = AUTO;
+	CYCLONE_CONFIGURATION_DEVICE = AUTO;
+	STRATIX_UPDATE_MODE = STANDARD;
+	APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+	MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+	FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+	STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+	AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON;
+	DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF;
+	COMPRESSION_MODE = OFF;
+	ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
+	FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF;
+	FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
+	EPROM_USE_CHECKSUM_AS_USERCODE = OFF;
+	USE_CHECKSUM_AS_USERCODE = OFF;
+	MAX7000_USE_CHECKSUM_AS_USERCODE = OFF;
+	GENERATE_TTF_FILE = OFF;
+	GENERATE_RBF_FILE = ON;
+	GENERATE_HEX_FILE = OFF;
+	SECURITY_BIT = OFF;
+	ENABLE_VREFA_PIN = OFF;
+	ENABLE_VREFB_PIN = OFF;
+	GENERATE_SVF_FILE = OFF;
+	GENERATE_ISC_FILE = OFF;
+	GENERATE_JAM_FILE = OFF;
+	GENERATE_JBC_FILE = OFF;
+	GENERATE_JBC_FILE_COMPRESSED = ON;
+	GENERATE_CONFIG_SVF_FILE = OFF;
+	GENERATE_CONFIG_ISC_FILE = OFF;
+	GENERATE_CONFIG_JAM_FILE = OFF;
+	GENERATE_CONFIG_JBC_FILE = OFF;
+	GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON;
+	GENERATE_CONFIG_HEXOUT_FILE = OFF;
+	ON_CHIP_BITSTREAM_DECOMPRESSION = OFF;
+	BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE = OFF;
+	HEXOUT_FILE_START_ADDRESS = 0;
+	HEXOUT_FILE_COUNT_DIRECTION = UP;
+	RESERVE_ALL_UNUSED_PINS = "AS INPUT TRI-STATED";
+	STRATIX_DEVICE_IO_STANDARD = LVTTL;
+	CLOCK_SOURCE = INTERNAL;
+	CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ";
+	CONFIGURATION_CLOCK_DIVISOR = 1;
+	RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+	RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+	RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+	RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED";
+	RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+	RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+	SCLK : LOCATION = Pin_101;
+	SDI : LOCATION = Pin_100;
+	SEN : LOCATION = Pin_98;
+	SLD : LOCATION = Pin_95;
+	adc1_data[0] : LOCATION = Pin_5;
+	adc1_data[10] : LOCATION = Pin_235;
+	adc1_data[11] : LOCATION = Pin_234;
+	adc1_data[1] : LOCATION = Pin_4;
+	adc1_data[2] : LOCATION = Pin_3;
+	adc1_data[3] : LOCATION = Pin_2;
+	adc1_data[4] : LOCATION = Pin_1;
+	adc1_data[4] : IO_STANDARD = LVTTL;
+	adc1_data[5] : LOCATION = Pin_240;
+	adc1_data[6] : LOCATION = Pin_239;
+	adc1_data[7] : LOCATION = Pin_238;
+	adc1_data[8] : LOCATION = Pin_237;
+	adc1_data[9] : LOCATION = Pin_236;
+	adc2_data[0] : LOCATION = Pin_20;
+	adc2_data[10] : LOCATION = Pin_8;
+	adc2_data[11] : LOCATION = Pin_7;
+	adc2_data[1] : LOCATION = Pin_19;
+	adc2_data[2] : LOCATION = Pin_18;
+	adc2_data[3] : LOCATION = Pin_17;
+	adc2_data[4] : LOCATION = Pin_16;
+	adc2_data[5] : LOCATION = Pin_15;
+	adc2_data[6] : LOCATION = Pin_14;
+	adc2_data[7] : LOCATION = Pin_13;
+	adc2_data[8] : LOCATION = Pin_12;
+	adc2_data[9] : LOCATION = Pin_11;
+	adc3_data[0] : LOCATION = Pin_200;
+	adc3_data[10] : LOCATION = Pin_184;
+	adc3_data[11] : LOCATION = Pin_183;
+	adc3_data[1] : LOCATION = Pin_197;
+	adc3_data[2] : LOCATION = Pin_196;
+	adc3_data[3] : LOCATION = Pin_195;
+	adc3_data[4] : LOCATION = Pin_194;
+	adc3_data[5] : LOCATION = Pin_193;
+	adc3_data[6] : LOCATION = Pin_188;
+	adc3_data[7] : LOCATION = Pin_187;
+	adc3_data[8] : LOCATION = Pin_186;
+	adc3_data[9] : LOCATION = Pin_185;
+	adc4_data[0] : LOCATION = Pin_222;
+	adc4_data[10] : LOCATION = Pin_203;
+	adc4_data[11] : LOCATION = Pin_202;
+	adc4_data[1] : LOCATION = Pin_219;
+	adc4_data[2] : LOCATION = Pin_217;
+	adc4_data[3] : LOCATION = Pin_216;
+	adc4_data[4] : LOCATION = Pin_215;
+	adc4_data[5] : LOCATION = Pin_214;
+	adc4_data[6] : LOCATION = Pin_213;
+	adc4_data[7] : LOCATION = Pin_208;
+	adc4_data[8] : LOCATION = Pin_207;
+	adc4_data[9] : LOCATION = Pin_206;
+	adc_oeb[0] : LOCATION = Pin_228;
+	adc_oeb[1] : LOCATION = Pin_21;
+	adc_oeb[2] : LOCATION = Pin_181;
+	adc_oeb[3] : LOCATION = Pin_218;
+	adc_otr[0] : LOCATION = Pin_233;
+	adc_otr[1] : LOCATION = Pin_6;
+	adc_otr[2] : LOCATION = Pin_182;
+	adc_otr[3] : LOCATION = Pin_201;
+	adclk0 : LOCATION = Pin_224;
+	adclk1 : LOCATION = Pin_226;
+	clk0 : LOCATION = Pin_28;
+	clk0 : RESERVE_PIN = "AS INPUT TRI-STATED";
+	clk0 : IO_STANDARD = LVTTL;
+	clk1 : LOCATION = Pin_29;
+	clk1 : RESERVE_PIN = "AS INPUT TRI-STATED";
+	clk1 : IO_STANDARD = LVTTL;
+	clk3 : LOCATION = Pin_152;
+	clk3 : RESERVE_PIN = "AS INPUT TRI-STATED";
+	clk3 : IO_STANDARD = LVTTL;
+	clk_120mhz : LOCATION = Pin_153;
+	clk_120mhz : IO_STANDARD = LVTTL;
+	clk_out : LOCATION = Pin_63;
+	clk_out : IO_STANDARD = LVTTL;
+	dac1_data[0] : LOCATION = Pin_165;
+	dac1_data[10] : LOCATION = Pin_177;
+	dac1_data[11] : LOCATION = Pin_178;
+	dac1_data[12] : LOCATION = Pin_179;
+	dac1_data[13] : LOCATION = Pin_180;
+	dac1_data[1] : LOCATION = Pin_166;
+	dac1_data[2] : LOCATION = Pin_167;
+	dac1_data[3] : LOCATION = Pin_168;
+	dac1_data[4] : LOCATION = Pin_169;
+	dac1_data[5] : LOCATION = Pin_170;
+	dac1_data[6] : LOCATION = Pin_173;
+	dac1_data[7] : LOCATION = Pin_174;
+	dac1_data[8] : LOCATION = Pin_175;
+	dac1_data[9] : LOCATION = Pin_176;
+	dac2_data[0] : LOCATION = Pin_159;
+	dac2_data[10] : LOCATION = Pin_163;
+	dac2_data[11] : LOCATION = Pin_139;
+	dac2_data[12] : LOCATION = Pin_164;
+	dac2_data[13] : LOCATION = Pin_138;
+	dac2_data[1] : LOCATION = Pin_158;
+	dac2_data[2] : LOCATION = Pin_160;
+	dac2_data[3] : LOCATION = Pin_156;
+	dac2_data[4] : LOCATION = Pin_161;
+	dac2_data[5] : LOCATION = Pin_144;
+	dac2_data[6] : LOCATION = Pin_162;
+	dac2_data[7] : LOCATION = Pin_141;
+	dac2_data[8] : LOCATION = Pin_143;
+	dac2_data[9] : LOCATION = Pin_140;
+	dac3_data[0] : LOCATION = Pin_122;
+	dac3_data[10] : LOCATION = Pin_134;
+	dac3_data[11] : LOCATION = Pin_135;
+	dac3_data[12] : LOCATION = Pin_136;
+	dac3_data[13] : LOCATION = Pin_137;
+	dac3_data[1] : LOCATION = Pin_123;
+	dac3_data[2] : LOCATION = Pin_124;
+	dac3_data[3] : LOCATION = Pin_125;
+	dac3_data[4] : LOCATION = Pin_126;
+	dac3_data[5] : LOCATION = Pin_127;
+	dac3_data[6] : LOCATION = Pin_128;
+	dac3_data[7] : LOCATION = Pin_131;
+	dac3_data[8] : LOCATION = Pin_132;
+	dac3_data[9] : LOCATION = Pin_133;
+	dac4_data[0] : LOCATION = Pin_104;
+	dac4_data[10] : LOCATION = Pin_118;
+	dac4_data[11] : LOCATION = Pin_119;
+	dac4_data[12] : LOCATION = Pin_120;
+	dac4_data[13] : LOCATION = Pin_121;
+	dac4_data[1] : LOCATION = Pin_105;
+	dac4_data[2] : LOCATION = Pin_106;
+	dac4_data[3] : LOCATION = Pin_107;
+	dac4_data[4] : LOCATION = Pin_108;
+	dac4_data[5] : LOCATION = Pin_113;
+	dac4_data[6] : LOCATION = Pin_114;
+	dac4_data[7] : LOCATION = Pin_115;
+	dac4_data[8] : LOCATION = Pin_116;
+	dac4_data[9] : LOCATION = Pin_117;
+	enable_rx : LOCATION = Pin_88;
+	enable_tx : LOCATION = Pin_93;
+	gndbus[0] : LOCATION = Pin_223;
+	gndbus[0] : RESERVE_PIN = "AS INPUT TRI-STATED";
+	gndbus[0] : IO_STANDARD = LVTTL;
+	gndbus[1] : LOCATION = Pin_225;
+	gndbus[1] : RESERVE_PIN = "AS INPUT TRI-STATED";
+	gndbus[1] : IO_STANDARD = LVTTL;
+	gndbus[2] : LOCATION = Pin_227;
+	gndbus[2] : RESERVE_PIN = "AS INPUT TRI-STATED";
+	gndbus[2] : IO_STANDARD = LVTTL;
+	gndbus[3] : LOCATION = Pin_62;
+	gndbus[3] : RESERVE_PIN = "AS INPUT TRI-STATED";
+	gndbus[3] : IO_STANDARD = LVTTL;
+	gndbus[4] : LOCATION = Pin_64;
+	gndbus[4] : RESERVE_PIN = "AS INPUT TRI-STATED";
+	gndbus[4] : IO_STANDARD = LVTTL;
+	misc_pins[0] : LOCATION = Pin_87;
+	misc_pins[0] : IO_STANDARD = LVTTL;
+	misc_pins[10] : LOCATION = Pin_76;
+	misc_pins[10] : IO_STANDARD = LVTTL;
+	misc_pins[11] : LOCATION = Pin_74;
+	misc_pins[11] : IO_STANDARD = LVTTL;
+	misc_pins[1] : LOCATION = Pin_86;
+	misc_pins[1] : IO_STANDARD = LVTTL;
+	misc_pins[2] : LOCATION = Pin_85;
+	misc_pins[2] : IO_STANDARD = LVTTL;
+	misc_pins[3] : LOCATION = Pin_84;
+	misc_pins[3] : IO_STANDARD = LVTTL;
+	misc_pins[4] : LOCATION = Pin_83;
+	misc_pins[4] : IO_STANDARD = LVTTL;
+	misc_pins[5] : LOCATION = Pin_82;
+	misc_pins[5] : IO_STANDARD = LVTTL;
+	misc_pins[6] : LOCATION = Pin_79;
+	misc_pins[6] : IO_STANDARD = LVTTL;
+	misc_pins[7] : LOCATION = Pin_78;
+	misc_pins[7] : IO_STANDARD = LVTTL;
+	misc_pins[8] : LOCATION = Pin_77;
+	misc_pins[8] : IO_STANDARD = LVTTL;
+	misc_pins[9] : LOCATION = Pin_75;
+	misc_pins[9] : IO_STANDARD = LVTTL;
+	reset : LOCATION = Pin_94;
+	usbclk : LOCATION = Pin_55;
+	usbctl[0] : LOCATION = Pin_56;
+	usbctl[1] : LOCATION = Pin_54;
+	usbctl[2] : LOCATION = Pin_53;
+	usbctl[3] : LOCATION = Pin_58;
+	usbctl[4] : LOCATION = Pin_57;
+	usbctl[5] : LOCATION = Pin_44;
+	usbdata[0] : LOCATION = Pin_73;
+	usbdata[10] : LOCATION = Pin_41;
+	usbdata[11] : LOCATION = Pin_39;
+	usbdata[12] : LOCATION = Pin_38;
+	usbdata[12] : IO_STANDARD = LVTTL;
+	usbdata[13] : LOCATION = Pin_37;
+	usbdata[14] : LOCATION = Pin_24;
+	usbdata[15] : LOCATION = Pin_23;
+	usbdata[1] : LOCATION = Pin_68;
+	usbdata[2] : LOCATION = Pin_67;
+	usbdata[3] : LOCATION = Pin_66;
+	usbdata[4] : LOCATION = Pin_65;
+	usbdata[5] : LOCATION = Pin_61;
+	usbdata[6] : LOCATION = Pin_60;
+	usbdata[7] : LOCATION = Pin_59;
+	usbdata[8] : LOCATION = Pin_43;
+	usbdata[9] : LOCATION = Pin_42;
+	usbrdy[0] : LOCATION = Pin_45;
+	usbrdy[1] : LOCATION = Pin_46;
+	usbrdy[2] : LOCATION = Pin_47;
+	usbrdy[3] : LOCATION = Pin_48;
+	usbrdy[4] : LOCATION = Pin_49;
+	usbrdy[5] : LOCATION = Pin_50;
+	clear_status : LOCATION = Pin_99;
+}
diff --git a/fpga/usrp1/toplevel/usrp_multi/usrp_multi.esf b/fpga/usrp1/toplevel/usrp_multi/usrp_multi.esf
new file mode 100644
index 000000000..df45f676b
--- /dev/null
+++ b/fpga/usrp1/toplevel/usrp_multi/usrp_multi.esf
@@ -0,0 +1,14 @@
+SIMULATOR_SETTINGS
+{
+	ESTIMATE_POWER_CONSUMPTION = OFF;
+	GLITCH_INTERVAL = 1NS;
+	GLITCH_DETECTION = OFF;
+	SIMULATION_COVERAGE = ON;
+	CHECK_OUTPUTS = OFF;
+	SETUP_HOLD_DETECTION = OFF;
+	POWER_ESTIMATION_START_TIME = "0 NS";
+	ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS = ON;
+	SIMULATION_MODE = TIMING;
+	START_TIME = 0NS;
+	USE_COMPILER_SETTINGS = usrp_multi;
+}
diff --git a/fpga/usrp1/toplevel/usrp_multi/usrp_multi.psf b/fpga/usrp1/toplevel/usrp_multi/usrp_multi.psf
new file mode 100644
index 000000000..68c2d12f9
--- /dev/null
+++ b/fpga/usrp1/toplevel/usrp_multi/usrp_multi.psf
@@ -0,0 +1,312 @@
+DEFAULT_DESIGN_ASSISTANT_SETTINGS
+{
+	HCPY_ALOAD_SIGNALS = OFF;
+	HCPY_VREF_PINS = OFF;
+	HCPY_CAT = OFF;
+	HCPY_ILLEGAL_HC_DEV_PKG = OFF;
+	ACLK_RULE_IMSZER_ADOMAIN = OFF;
+	ACLK_RULE_SZER_BTW_ACLK_DOMAIN = OFF;
+	ACLK_RULE_NO_SZER_ACLK_DOMAIN = OFF;
+	ACLK_CAT = OFF;
+	SIGNALRACE_RULE_ASYNCHPIN_SYNCH_CLKPIN = OFF;
+	SIGNALRACE_CAT = OFF;
+	NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED = OFF;
+	NONSYNCHSTRUCT_RULE_SRLATCH = OFF;
+	NONSYNCHSTRUCT_RULE_DLATCH = OFF;
+	NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR = OFF;
+	NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN = OFF;
+	NONSYNCHSTRUCT_RULE_RIPPLE_CLK = OFF;
+	NONSYNCHSTRUCT_RULE_DELAY_CHAIN = OFF;
+	NONSYNCHSTRUCT_RULE_REG_LOOP = OFF;
+	NONSYNCHSTRUCT_RULE_COMBLOOP = OFF;
+	NONSYNCHSTRUCT_CAT = OFF;
+	NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE = OFF;
+	TIMING_RULE_COIN_CLKEDGE = OFF;
+	TIMING_RULE_SHIFT_REG = OFF;
+	TIMING_RULE_HIGH_FANOUTS = OFF;
+	TIMING_CAT = OFF;
+	RESET_RULE_ALL = OFF;
+	RESET_RULE_IMSYNCH_ASYNCH_DOMAIN = OFF;
+	RESET_RULE_UNSYNCH_ASYNCH_DOMAIN = OFF;
+	RESET_RULE_REG_ASNYCH = OFF;
+	RESET_RULE_COMB_ASYNCH_RESET = OFF;
+	RESET_RULE_IMSYNCH_EXRESET = OFF;
+	RESET_RULE_UNSYNCH_EXRESET = OFF;
+	RESET_RULE_INPINS_RESETNET = OFF;
+	RESET_CAT = OFF;
+	CLK_RULE_ALL = OFF;
+	CLK_RULE_MIX_EDGES = OFF;
+	CLK_RULE_CLKNET_CLKSPINES = OFF;
+	CLK_RULE_INPINS_CLKNET = OFF;
+	CLK_RULE_GATING_SCHEME = OFF;
+	CLK_RULE_INV_CLOCK = OFF;
+	CLK_RULE_COMB_CLOCK = OFF;
+	CLK_CAT = OFF;
+	HCPY_EXCEED_USER_IO_USAGE = OFF;
+	HCPY_EXCEED_RAM_USAGE = OFF;
+	NONSYNCHSTRUCT_RULE_ASYN_RAM = OFF;
+	SIGNALRACE_RULE_TRISTATE = OFF;
+	ASSG_RULE_MISSING_TIMING = OFF;
+	ASSG_RULE_MISSING_FMAX = OFF;
+	ASSG_CAT = OFF;
+}
+SYNTHESIS_FITTING_SETTINGS
+{
+	AUTO_SHIFT_REGISTER_RECOGNITION = ON;
+	AUTO_DSP_RECOGNITION = ON;
+	AUTO_RAM_RECOGNITION = ON;
+	REMOVE_DUPLICATE_LOGIC = ON;
+	AUTO_TURBO_BIT = ON;
+	AUTO_MERGE_PLLS = ON;
+	AUTO_OPEN_DRAIN_PINS = ON;
+	AUTO_PARALLEL_EXPANDERS = ON;
+	AUTO_FAST_OUTPUT_ENABLE_REGISTERS = OFF;
+	AUTO_FAST_OUTPUT_REGISTERS = OFF;
+	AUTO_FAST_INPUT_REGISTERS = OFF;
+	AUTO_CASCADE_CHAINS = ON;
+	AUTO_CARRY_CHAINS = ON;
+	AUTO_DELAY_CHAINS = ON;
+	MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH = 4;
+	PARALLEL_EXPANDER_CHAIN_LENGTH = 16;
+	CASCADE_CHAIN_LENGTH = 2;
+	STRATIX_CARRY_CHAIN_LENGTH = 70;
+	MERCURY_CARRY_CHAIN_LENGTH = 48;
+	FLEX10K_CARRY_CHAIN_LENGTH = 32;
+	FLEX6K_CARRY_CHAIN_LENGTH = 32;
+	CARRY_CHAIN_LENGTH = 48;
+	CARRY_OUT_PINS_LCELL_INSERT = ON;
+	NORMAL_LCELL_INSERT = ON;
+	AUTO_LCELL_INSERTION = ON;
+	ALLOW_XOR_GATE_USAGE = ON;
+	AUTO_PACKED_REGISTERS_STRATIX = NORMAL;
+	AUTO_PACKED_REGISTERS = OFF;
+	AUTO_PACKED_REG_CYCLONE = NORMAL;
+	FLEX10K_OPTIMIZATION_TECHNIQUE = AREA;
+	FLEX6K_OPTIMIZATION_TECHNIQUE = AREA;
+	MERCURY_OPTIMIZATION_TECHNIQUE = AREA;
+	APEX20K_OPTIMIZATION_TECHNIQUE = SPEED;
+	MAX7000_OPTIMIZATION_TECHNIQUE = SPEED;
+	STRATIX_OPTIMIZATION_TECHNIQUE = SPEED;
+	CYCLONE_OPTIMIZATION_TECHNIQUE = AREA;
+	FLEX10K_TECHNOLOGY_MAPPER = LUT;
+	FLEX6K_TECHNOLOGY_MAPPER = LUT;
+	MERCURY_TECHNOLOGY_MAPPER = LUT;
+	APEX20K_TECHNOLOGY_MAPPER = LUT;
+	MAX7000_TECHNOLOGY_MAPPER = "PRODUCT TERM";
+	STRATIX_TECHNOLOGY_MAPPER = LUT;
+	AUTO_IMPLEMENT_IN_ROM = OFF;
+	AUTO_GLOBAL_MEMORY_CONTROLS = OFF;
+	AUTO_GLOBAL_REGISTER_CONTROLS = ON;
+	AUTO_GLOBAL_OE = ON;
+	AUTO_GLOBAL_CLOCK = ON;
+	USE_LPM_FOR_AHDL_OPERATORS = ON;
+	LIMIT_AHDL_INTEGERS_TO_32_BITS = OFF;
+	ENABLE_BUS_HOLD_CIRCUITRY = OFF;
+	WEAK_PULL_UP_RESISTOR = OFF;
+	TURBO_BIT = ON;
+	MAX7000_IGNORE_SOFT_BUFFERS = OFF;
+	IGNORE_SOFT_BUFFERS = ON;
+	MAX7000_IGNORE_LCELL_BUFFERS = AUTO;
+	IGNORE_LCELL_BUFFERS = OFF;
+	IGNORE_ROW_GLOBAL_BUFFERS = OFF;
+	IGNORE_GLOBAL_BUFFERS = OFF;
+	IGNORE_CASCADE_BUFFERS = OFF;
+	IGNORE_CARRY_BUFFERS = OFF;
+	REMOVE_DUPLICATE_REGISTERS = ON;
+	REMOVE_REDUNDANT_LOGIC_CELLS = OFF;
+	ALLOW_POWER_UP_DONT_CARE = ON;
+	PCI_IO = OFF;
+	NOT_GATE_PUSH_BACK = ON;
+	SLOW_SLEW_RATE = OFF;
+	DSP_BLOCK_BALANCING = AUTO;
+	STATE_MACHINE_PROCESSING = AUTO;
+}
+DEFAULT_HARDCOPY_SETTINGS
+{
+	HARDCOPY_EXTERNAL_CLOCK_JITTER = "0.0 NS";
+}
+DEFAULT_TIMING_REQUIREMENTS
+{
+	INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
+	RUN_ALL_TIMING_ANALYSES = ON;
+	IGNORE_CLOCK_SETTINGS = OFF;
+	DEFAULT_HOLD_MULTICYCLE = "SAME AS MULTICYCLE";
+	CUT_OFF_IO_PIN_FEEDBACK = ON;
+	CUT_OFF_CLEAR_AND_PRESET_PATHS = ON;
+	CUT_OFF_READ_DURING_WRITE_PATHS = ON;
+	CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS = ON;
+	DO_MIN_ANALYSIS = ON;
+	DO_MIN_TIMING = OFF;
+	NUMBER_OF_PATHS_TO_REPORT = 200;
+	NUMBER_OF_DESTINATION_TO_REPORT = 10;
+	NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT = 10;
+	MAX_SCC_SIZE = 50;
+}
+HDL_SETTINGS
+{
+	VERILOG_INPUT_VERSION = VERILOG_2001;
+	ENABLE_IP_DEBUG = OFF;
+	VHDL_INPUT_VERSION = VHDL93;
+	VHDL_SHOW_LMF_MAPPING_MESSAGES = OFF;
+}
+PROJECT_INFO(usrp_multi)
+{
+	ORIGINAL_QUARTUS_VERSION = 3.0;
+	PROJECT_CREATION_TIME_DATE = "00:14:04  JULY 13, 2003";
+	LAST_QUARTUS_VERSION = 3.0;
+	SHOW_REGISTRATION_MESSAGE = ON;
+	USER_LIBRARIES = "e:\usrp\fpga\megacells";
+}
+THIRD_PARTY_EDA_TOOLS(usrp_multi)
+{
+	EDA_DESIGN_ENTRY_SYNTHESIS_TOOL = "<NONE>";
+	EDA_SIMULATION_TOOL = "<NONE>";
+	EDA_TIMING_ANALYSIS_TOOL = "<NONE>";
+	EDA_BOARD_DESIGN_TOOL = "<NONE>";
+	EDA_FORMAL_VERIFICATION_TOOL = "<NONE>";
+	EDA_RESYNTHESIS_TOOL = "<NONE>";
+}
+EDA_TOOL_SETTINGS(eda_design_synthesis)
+{
+	EDA_INPUT_GND_NAME = GND;
+	EDA_INPUT_VCC_NAME = VCC;
+	EDA_SHOW_LMF_MAPPING_MESSAGES = OFF;
+	EDA_RUN_TOOL_AUTOMATICALLY = OFF;
+	EDA_INPUT_DATA_FORMAT = EDIF;
+	EDA_OUTPUT_DATA_FORMAT = NONE;
+	USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
+	RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
+	RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
+	RESYNTHESIS_RETIMING = FULL;
+}
+EDA_TOOL_SETTINGS(eda_simulation)
+{
+	EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
+	EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
+	EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
+	EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
+	EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
+	EDA_FLATTEN_BUSES = OFF;
+	EDA_MAP_ILLEGAL_CHARACTERS = OFF;
+	EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
+	EDA_RUN_TOOL_AUTOMATICALLY = OFF;
+	EDA_OUTPUT_DATA_FORMAT = NONE;
+	USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
+	RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
+	RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
+	RESYNTHESIS_RETIMING = FULL;
+}
+EDA_TOOL_SETTINGS(eda_timing_analysis)
+{
+	EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
+	EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
+	EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
+	EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
+	EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
+	EDA_FLATTEN_BUSES = OFF;
+	EDA_MAP_ILLEGAL_CHARACTERS = OFF;
+	EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
+	EDA_RUN_TOOL_AUTOMATICALLY = OFF;
+	EDA_OUTPUT_DATA_FORMAT = NONE;
+	EDA_LAUNCH_CMD_LINE_TOOL = OFF;
+	USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
+	RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
+	RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
+	RESYNTHESIS_RETIMING = FULL;
+}
+EDA_TOOL_SETTINGS(eda_board_design)
+{
+	EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
+	EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
+	EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
+	EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
+	EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
+	EDA_FLATTEN_BUSES = OFF;
+	EDA_MAP_ILLEGAL_CHARACTERS = OFF;
+	EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
+	EDA_RUN_TOOL_AUTOMATICALLY = OFF;
+	EDA_OUTPUT_DATA_FORMAT = NONE;
+	USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
+	RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
+	RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
+	RESYNTHESIS_RETIMING = FULL;
+}
+EDA_TOOL_SETTINGS(eda_formal_verification)
+{
+	EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
+	EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
+	EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
+	EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
+	EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
+	EDA_FLATTEN_BUSES = OFF;
+	EDA_MAP_ILLEGAL_CHARACTERS = OFF;
+	EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
+	EDA_RUN_TOOL_AUTOMATICALLY = OFF;
+	EDA_OUTPUT_DATA_FORMAT = NONE;
+	USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
+	RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
+	RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
+	RESYNTHESIS_RETIMING = FULL;
+}
+EDA_TOOL_SETTINGS(eda_palace)
+{
+	EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
+	EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
+	EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
+	EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
+	EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
+	EDA_FLATTEN_BUSES = OFF;
+	EDA_MAP_ILLEGAL_CHARACTERS = OFF;
+	EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
+	EDA_RUN_TOOL_AUTOMATICALLY = OFF;
+	EDA_OUTPUT_DATA_FORMAT = NONE;
+	RESYNTHESIS_RETIMING = FULL;
+	RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
+	RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
+	USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
+}
+CLOCK(clk_120mhz)
+{
+	FMAX_REQUIREMENT = "120.0 MHz";
+	INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
+	DUTY_CYCLE = 50;
+	DIVIDE_BASE_CLOCK_PERIOD_BY = 1;
+	MULTIPLY_BASE_CLOCK_PERIOD_BY = 1;
+	INVERT_BASE_CLOCK = OFF;
+}
+CLOCK(usbclk)
+{
+	FMAX_REQUIREMENT = "48.0 MHz";
+	INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
+	DUTY_CYCLE = 50;
+	DIVIDE_BASE_CLOCK_PERIOD_BY = 1;
+	MULTIPLY_BASE_CLOCK_PERIOD_BY = 1;
+	INVERT_BASE_CLOCK = OFF;
+}
+CLOCK(SCLK)
+{
+	FMAX_REQUIREMENT = "1.0 MHz";
+	INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
+	DUTY_CYCLE = 50;
+	DIVIDE_BASE_CLOCK_PERIOD_BY = 1;
+	MULTIPLY_BASE_CLOCK_PERIOD_BY = 1;
+	INVERT_BASE_CLOCK = OFF;
+}
+CLOCK(adclk0)
+{
+	FMAX_REQUIREMENT = "60.0 MHz";
+	INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
+	DUTY_CYCLE = 50;
+	DIVIDE_BASE_CLOCK_PERIOD_BY = 1;
+	MULTIPLY_BASE_CLOCK_PERIOD_BY = 1;
+	INVERT_BASE_CLOCK = OFF;
+}
+CLOCK(adclk1)
+{
+	FMAX_REQUIREMENT = "60.0 MHz";
+	INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
+	DUTY_CYCLE = 50;
+	DIVIDE_BASE_CLOCK_PERIOD_BY = 1;
+	MULTIPLY_BASE_CLOCK_PERIOD_BY = 1;
+	INVERT_BASE_CLOCK = OFF;
+}
diff --git a/fpga/usrp1/toplevel/usrp_multi/usrp_multi.qpf b/fpga/usrp1/toplevel/usrp_multi/usrp_multi.qpf
new file mode 100644
index 000000000..1524de1bb
--- /dev/null
+++ b/fpga/usrp1/toplevel/usrp_multi/usrp_multi.qpf
@@ -0,0 +1,29 @@
+# Copyright (C) 1991-2004 Altera Corporation
+# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+# support information,  device programming or simulation file,  and any other
+# associated  documentation or information  provided by  Altera  or a partner
+# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+# other  use  of such  megafunction  design,  netlist,  support  information,
+# device programming or simulation file,  or any other  related documentation
+# or information  is prohibited  for  any  other purpose,  including, but not
+# limited to  modification,  reverse engineering,  de-compiling, or use  with
+# any other  silicon devices,  unless such use is  explicitly  licensed under
+# a separate agreement with  Altera  or a megafunction partner.  Title to the
+# intellectual property,  including patents,  copyrights,  trademarks,  trade
+# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+# support  information,  device programming or simulation file,  or any other
+# related documentation or information provided by  Altera  or a megafunction
+# partner, remains with Altera, the megafunction partner, or their respective
+# licensors. No other licenses, including any licenses needed under any third
+# party's intellectual property, are provided herein.
+
+
+
+QUARTUS_VERSION = "4.0"
+DATE = "17:10:11  December 20, 2004"
+
+
+# Active Revisions
+
+PROJECT_REVISION = "usrp_multi"
diff --git a/fpga/usrp1/toplevel/usrp_multi/usrp_multi.qsf b/fpga/usrp1/toplevel/usrp_multi/usrp_multi.qsf
new file mode 100644
index 000000000..9f0efbd83
--- /dev/null
+++ b/fpga/usrp1/toplevel/usrp_multi/usrp_multi.qsf
@@ -0,0 +1,408 @@
+# Copyright (C) 1991-2005 Altera Corporation

+# Your use of Altera Corporation's design tools, logic functions 

+# and other software and tools, and its AMPP partner logic       

+# functions, and any output files any of the foregoing           

+# (including device programming or simulation files), and any    

+# associated documentation or information are expressly subject  

+# to the terms and conditions of the Altera Program License      

+# Subscription Agreement, Altera MegaCore Function License       

+# Agreement, or other applicable license agreement, including,   

+# without limitation, that your use is for the sole purpose of   

+# programming logic devices manufactured by Altera and sold by   

+# Altera or its authorized distributors.  Please refer to the    

+# applicable agreement for further details.

+

+

+# The default values for assignments are stored in the file

+#		usrp_multi_assignment_defaults.qdf

+# If this file doesn't exist, and for assignments not listed, see file

+#		assignment_defaults.qdf

+

+# Altera recommends that you do not modify this file. This

+# file is updated automatically by the Quartus II software

+# and any changes you make may be lost or overwritten.

+

+

+# Project-Wide Assignments

+# ========================

+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0

+set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04  JULY 13, 2003"

+set_global_assignment -name LAST_QUARTUS_VERSION 6.1

+

+# Pin & Location Assignments

+# ==========================

+set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED"

+set_location_assignment PIN_29 -to SCLK

+set_location_assignment PIN_117 -to SDI

+set_location_assignment PIN_28 -to usbclk

+set_location_assignment PIN_107 -to usbctl[0]

+set_location_assignment PIN_106 -to usbctl[1]

+set_location_assignment PIN_105 -to usbctl[2]

+set_location_assignment PIN_100 -to usbdata[0]

+set_location_assignment PIN_84 -to usbdata[10]

+set_location_assignment PIN_83 -to usbdata[11]

+set_location_assignment PIN_82 -to usbdata[12]

+set_location_assignment PIN_79 -to usbdata[13]

+set_location_assignment PIN_78 -to usbdata[14]

+set_location_assignment PIN_77 -to usbdata[15]

+set_location_assignment PIN_99 -to usbdata[1]

+set_location_assignment PIN_98 -to usbdata[2]

+set_location_assignment PIN_95 -to usbdata[3]

+set_location_assignment PIN_94 -to usbdata[4]

+set_location_assignment PIN_93 -to usbdata[5]

+set_location_assignment PIN_88 -to usbdata[6]

+set_location_assignment PIN_87 -to usbdata[7]

+set_location_assignment PIN_86 -to usbdata[8]

+set_location_assignment PIN_85 -to usbdata[9]

+set_location_assignment PIN_104 -to usbrdy[0]

+set_location_assignment PIN_101 -to usbrdy[1]

+set_location_assignment PIN_76 -to FX2_1

+set_location_assignment PIN_75 -to FX2_2

+set_location_assignment PIN_74 -to FX2_3

+set_location_assignment PIN_116 -to io_rx_a[0]

+set_location_assignment PIN_115 -to io_rx_a[1]

+set_location_assignment PIN_114 -to io_rx_a[2]

+set_location_assignment PIN_113 -to io_rx_a[3]

+set_location_assignment PIN_108 -to io_rx_a[4]

+set_location_assignment PIN_195 -to io_rx_a[5]

+set_location_assignment PIN_196 -to io_rx_a[6]

+set_location_assignment PIN_197 -to io_rx_a[7]

+set_location_assignment PIN_200 -to io_rx_a[8]

+set_location_assignment PIN_201 -to io_rx_a[9]

+set_location_assignment PIN_202 -to io_rx_a[10]

+set_location_assignment PIN_203 -to io_rx_a[11]

+set_location_assignment PIN_206 -to io_rx_a[12]

+set_location_assignment PIN_207 -to io_rx_a[13]

+set_location_assignment PIN_208 -to io_rx_a[14]

+set_location_assignment PIN_214 -to io_rx_b[0]

+set_location_assignment PIN_215 -to io_rx_b[1]

+set_location_assignment PIN_216 -to io_rx_b[2]

+set_location_assignment PIN_217 -to io_rx_b[3]

+set_location_assignment PIN_218 -to io_rx_b[4]

+set_location_assignment PIN_219 -to io_rx_b[5]

+set_location_assignment PIN_222 -to io_rx_b[6]

+set_location_assignment PIN_223 -to io_rx_b[7]

+set_location_assignment PIN_224 -to io_rx_b[8]

+set_location_assignment PIN_225 -to io_rx_b[9]

+set_location_assignment PIN_226 -to io_rx_b[10]

+set_location_assignment PIN_227 -to io_rx_b[11]

+set_location_assignment PIN_228 -to io_rx_b[12]

+set_location_assignment PIN_233 -to io_rx_b[13]

+set_location_assignment PIN_234 -to io_rx_b[14]

+set_location_assignment PIN_175 -to io_tx_a[0]

+set_location_assignment PIN_176 -to io_tx_a[1]

+set_location_assignment PIN_177 -to io_tx_a[2]

+set_location_assignment PIN_178 -to io_tx_a[3]

+set_location_assignment PIN_179 -to io_tx_a[4]

+set_location_assignment PIN_180 -to io_tx_a[5]

+set_location_assignment PIN_181 -to io_tx_a[6]

+set_location_assignment PIN_182 -to io_tx_a[7]

+set_location_assignment PIN_183 -to io_tx_a[8]

+set_location_assignment PIN_184 -to io_tx_a[9]

+set_location_assignment PIN_185 -to io_tx_a[10]

+set_location_assignment PIN_186 -to io_tx_a[11]

+set_location_assignment PIN_187 -to io_tx_a[12]

+set_location_assignment PIN_188 -to io_tx_a[13]

+set_location_assignment PIN_193 -to io_tx_a[14]

+set_location_assignment PIN_73 -to io_tx_b[0]

+set_location_assignment PIN_68 -to io_tx_b[1]

+set_location_assignment PIN_67 -to io_tx_b[2]

+set_location_assignment PIN_66 -to io_tx_b[3]

+set_location_assignment PIN_65 -to io_tx_b[4]

+set_location_assignment PIN_64 -to io_tx_b[5]

+set_location_assignment PIN_63 -to io_tx_b[6]

+set_location_assignment PIN_62 -to io_tx_b[7]

+set_location_assignment PIN_61 -to io_tx_b[8]

+set_location_assignment PIN_60 -to io_tx_b[9]

+set_location_assignment PIN_59 -to io_tx_b[10]

+set_location_assignment PIN_58 -to io_tx_b[11]

+set_location_assignment PIN_57 -to io_tx_b[12]

+set_location_assignment PIN_56 -to io_tx_b[13]

+set_location_assignment PIN_55 -to io_tx_b[14]

+set_location_assignment PIN_152 -to master_clk

+set_location_assignment PIN_144 -to rx_a_a[0]

+set_location_assignment PIN_143 -to rx_a_a[1]

+set_location_assignment PIN_141 -to rx_a_a[2]

+set_location_assignment PIN_140 -to rx_a_a[3]

+set_location_assignment PIN_139 -to rx_a_a[4]

+set_location_assignment PIN_138 -to rx_a_a[5]

+set_location_assignment PIN_137 -to rx_a_a[6]

+set_location_assignment PIN_136 -to rx_a_a[7]

+set_location_assignment PIN_135 -to rx_a_a[8]

+set_location_assignment PIN_134 -to rx_a_a[9]

+set_location_assignment PIN_133 -to rx_a_a[10]

+set_location_assignment PIN_132 -to rx_a_a[11]

+set_location_assignment PIN_23 -to rx_a_b[0]

+set_location_assignment PIN_21 -to rx_a_b[1]

+set_location_assignment PIN_20 -to rx_a_b[2]

+set_location_assignment PIN_19 -to rx_a_b[3]

+set_location_assignment PIN_18 -to rx_a_b[4]

+set_location_assignment PIN_17 -to rx_a_b[5]

+set_location_assignment PIN_16 -to rx_a_b[6]

+set_location_assignment PIN_15 -to rx_a_b[7]

+set_location_assignment PIN_14 -to rx_a_b[8]

+set_location_assignment PIN_13 -to rx_a_b[9]

+set_location_assignment PIN_12 -to rx_a_b[10]

+set_location_assignment PIN_11 -to rx_a_b[11]

+set_location_assignment PIN_131 -to rx_b_a[0]

+set_location_assignment PIN_128 -to rx_b_a[1]

+set_location_assignment PIN_127 -to rx_b_a[2]

+set_location_assignment PIN_126 -to rx_b_a[3]

+set_location_assignment PIN_125 -to rx_b_a[4]

+set_location_assignment PIN_124 -to rx_b_a[5]

+set_location_assignment PIN_123 -to rx_b_a[6]

+set_location_assignment PIN_122 -to rx_b_a[7]

+set_location_assignment PIN_121 -to rx_b_a[8]

+set_location_assignment PIN_120 -to rx_b_a[9]

+set_location_assignment PIN_119 -to rx_b_a[10]

+set_location_assignment PIN_118 -to rx_b_a[11]

+set_location_assignment PIN_8 -to rx_b_b[0]

+set_location_assignment PIN_7 -to rx_b_b[1]

+set_location_assignment PIN_6 -to rx_b_b[2]

+set_location_assignment PIN_5 -to rx_b_b[3]

+set_location_assignment PIN_4 -to rx_b_b[4]

+set_location_assignment PIN_3 -to rx_b_b[5]

+set_location_assignment PIN_2 -to rx_b_b[6]

+set_location_assignment PIN_240 -to rx_b_b[7]

+set_location_assignment PIN_239 -to rx_b_b[8]

+set_location_assignment PIN_238 -to rx_b_b[9]

+set_location_assignment PIN_237 -to rx_b_b[10]

+set_location_assignment PIN_236 -to rx_b_b[11]

+set_location_assignment PIN_156 -to SDO

+set_location_assignment PIN_153 -to SEN_FPGA

+set_location_assignment PIN_159 -to tx_a[0]

+set_location_assignment PIN_160 -to tx_a[1]

+set_location_assignment PIN_161 -to tx_a[2]

+set_location_assignment PIN_162 -to tx_a[3]

+set_location_assignment PIN_163 -to tx_a[4]

+set_location_assignment PIN_164 -to tx_a[5]

+set_location_assignment PIN_165 -to tx_a[6]

+set_location_assignment PIN_166 -to tx_a[7]

+set_location_assignment PIN_167 -to tx_a[8]

+set_location_assignment PIN_168 -to tx_a[9]

+set_location_assignment PIN_169 -to tx_a[10]

+set_location_assignment PIN_170 -to tx_a[11]

+set_location_assignment PIN_173 -to tx_a[12]

+set_location_assignment PIN_174 -to tx_a[13]

+set_location_assignment PIN_38 -to tx_b[0]

+set_location_assignment PIN_39 -to tx_b[1]

+set_location_assignment PIN_41 -to tx_b[2]

+set_location_assignment PIN_42 -to tx_b[3]

+set_location_assignment PIN_43 -to tx_b[4]

+set_location_assignment PIN_44 -to tx_b[5]

+set_location_assignment PIN_45 -to tx_b[6]

+set_location_assignment PIN_46 -to tx_b[7]

+set_location_assignment PIN_47 -to tx_b[8]

+set_location_assignment PIN_48 -to tx_b[9]

+set_location_assignment PIN_49 -to tx_b[10]

+set_location_assignment PIN_50 -to tx_b[11]

+set_location_assignment PIN_53 -to tx_b[12]

+set_location_assignment PIN_54 -to tx_b[13]

+set_location_assignment PIN_158 -to TXSYNC_A

+set_location_assignment PIN_37 -to TXSYNC_B

+set_location_assignment PIN_235 -to io_rx_b[15]

+set_location_assignment PIN_24 -to io_tx_b[15]

+set_location_assignment PIN_213 -to io_rx_a[15]

+set_location_assignment PIN_194 -to io_tx_a[15]

+set_location_assignment PIN_1 -to MYSTERY_SIGNAL

+

+# Timing Assignments

+# ==================

+set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF

+

+# Analysis & Synthesis Assignments

+# ================================

+set_global_assignment -name SAVE_DISK_SPACE OFF

+set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"

+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240

+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"

+set_global_assignment -name FAMILY Cyclone

+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE BALANCED

+set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED

+set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED

+set_global_assignment -name TOP_LEVEL_ENTITY usrp_multi

+set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF

+set_global_assignment -name USER_LIBRARIES "H:\\usrp-for2.7\\fpga\\megacells"

+set_global_assignment -name AUTO_ENABLE_SMART_COMPILE ON

+

+# Fitter Assignments

+# ==================

+set_global_assignment -name DEVICE EP1C12Q240C8

+set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL"

+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"

+set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF

+set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION"

+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF

+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF

+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF

+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION OFF

+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL

+set_global_assignment -name INC_PLC_MODE OFF

+set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF

+set_instance_assignment -name IO_STANDARD LVTTL -to usbdata[12]

+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL

+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1

+

+# Timing Analysis Assignments

+# ===========================

+set_global_assignment -name MAX_SCC_SIZE 50

+

+# EDA Netlist Writer Assignments

+# ==============================

+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"

+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<NONE>"

+set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<NONE>"

+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<NONE>"

+set_global_assignment -name EDA_RESYNTHESIS_TOOL "<NONE>"

+

+# Assembler Assignments

+# =====================

+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF

+set_global_assignment -name GENERATE_RBF_FILE ON

+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"

+set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF

+

+# Simulator Assignments

+# =====================

+set_global_assignment -name START_TIME "0 ns"

+set_global_assignment -name GLITCH_INTERVAL "1 ns"

+

+# Design Assistant Assignments

+# ============================

+set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF

+set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF

+set_global_assignment -name ASSG_CAT OFF

+set_global_assignment -name ASSG_RULE_MISSING_FMAX OFF

+set_global_assignment -name ASSG_RULE_MISSING_TIMING OFF

+set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM OFF

+set_global_assignment -name CLK_CAT OFF

+set_global_assignment -name CLK_RULE_COMB_CLOCK OFF

+set_global_assignment -name CLK_RULE_INV_CLOCK OFF

+set_global_assignment -name CLK_RULE_GATING_SCHEME OFF

+set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF

+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF

+set_global_assignment -name CLK_RULE_MIX_EDGES OFF

+set_global_assignment -name RESET_CAT OFF

+set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF

+set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF

+set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF

+set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF

+set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF

+set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF

+set_global_assignment -name TIMING_CAT OFF

+set_global_assignment -name TIMING_RULE_SHIFT_REG OFF

+set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF

+set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE OFF

+set_global_assignment -name NONSYNCHSTRUCT_CAT OFF

+set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF

+set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF

+set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF

+set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF

+set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF

+set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF

+set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF

+set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF

+set_global_assignment -name SIGNALRACE_CAT OFF

+set_global_assignment -name ACLK_CAT OFF

+set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF

+set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF

+set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF

+set_global_assignment -name HCPY_CAT OFF

+set_global_assignment -name HCPY_VREF_PINS OFF

+

+# SignalTap II Assignments

+# ========================

+set_global_assignment -name HUB_ENTITY_NAME SLD_HUB

+set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST

+set_global_assignment -name ENABLE_SIGNALTAP OFF

+

+# LogicLock Region Assignments

+# ============================

+set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF

+

+# -----------------

+# start CLOCK(SCLK)

+

+	# Timing Assignments

+	# ==================

+set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK

+set_global_assignment -name FMAX_REQUIREMENT "1 MHz" -section_id SCLK

+set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id SCLK

+

+# end CLOCK(SCLK)

+# ---------------

+

+# -----------------------

+# start CLOCK(master_clk)

+

+	# Timing Assignments

+	# ==================

+set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk

+set_global_assignment -name FMAX_REQUIREMENT "64 MHz" -section_id master_clk

+set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id master_clk

+

+# end CLOCK(master_clk)

+# ---------------------

+

+# -------------------

+# start CLOCK(usbclk)

+

+	# Timing Assignments

+	# ==================

+set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk

+set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id usbclk

+set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id usbclk

+

+# end CLOCK(usbclk)

+# -----------------

+

+# ----------------------

+# start ENTITY(usrp_multi)

+

+	# Timing Assignments

+	# ==================

+set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK

+set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk

+set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk

+

+# end ENTITY(usrp_multi)

+# --------------------

+

+

+set_global_assignment -name VERILOG_FILE ../../sdr_lib/rssi.v

+set_global_assignment -name VERILOG_FILE ../../sdr_lib/setting_reg_masked.v

+set_global_assignment -name VERILOG_FILE ../../sdr_lib/master_control_multi.v

+set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v

+set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k.v

+set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/acc.v

+set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mult.v

+set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/ram16_2sum.v

+set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_rom.v

+set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/halfband_decim.v

+set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mac.v

+set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_ram.v

+set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_chain.v

+set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_dcoffset.v

+set_global_assignment -name VERILOG_FILE ../../sdr_lib/adc_interface.v

+set_global_assignment -name VERILOG_FILE ../../sdr_lib/io_pins.v

+set_global_assignment -name VERILOG_FILE ../../sdr_lib/setting_reg.v

+set_global_assignment -name VERILOG_FILE ../../sdr_lib/bidir_reg.v

+set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_int_shifter.v

+set_global_assignment -name VERILOG_FILE ../../megacells/clk_doubler.v

+set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_chain.v

+set_global_assignment -name VERILOG_FILE ../../sdr_lib/gen_sync.v

+set_global_assignment -name VERILOG_FILE ../../sdr_lib/master_control.v

+set_global_assignment -name VERILOG_FILE ../../megacells/fifo_2k.v

+set_global_assignment -name VERILOG_FILE ../../megacells/bustri.v

+set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_buffer.v

+set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_buffer.v

+set_global_assignment -name VERILOG_FILE ../../sdr_lib/phase_acc.v

+set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_interp.v

+set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_decim.v

+set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic_stage.v

+set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic.v

+set_global_assignment -name VERILOG_FILE usrp_multi.v

+set_global_assignment -name VERILOG_FILE ../../sdr_lib/clk_divider.v

+set_global_assignment -name VERILOG_FILE ../../sdr_lib/serial_io.v

+set_global_assignment -name VERILOG_FILE ../../sdr_lib/strobe_gen.v

+set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v
\ No newline at end of file
diff --git a/fpga/usrp1/toplevel/usrp_multi/usrp_multi.v b/fpga/usrp1/toplevel/usrp_multi/usrp_multi.v
new file mode 100644
index 000000000..ce484fc1c
--- /dev/null
+++ b/fpga/usrp1/toplevel/usrp_multi/usrp_multi.v
@@ -0,0 +1,379 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003,2004,2005,2006 Matt Ettus
+//  Copyright (C) 2006 Martin Dudok van Heel
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+// Top level module for a full setup with DUCs and DDCs
+
+// Define DEBUG_OWNS_IO_PINS if we're using the daughterboard i/o pins
+// for debugging info.  NB, This can kill the m'board and/or d'board if you
+// have anything except basic d'boards installed.
+
+// Uncomment the following to include optional circuitry
+
+`include "config.vh"
+`include "../../../firmware/include/fpga_regs_common.v"
+`include "../../../firmware/include/fpga_regs_standard.v"
+
+module usrp_multi
+(output MYSTERY_SIGNAL,
+ input master_clk,
+ input SCLK,
+ input SDI,
+ inout SDO,
+ input SEN_FPGA,
+
+ input FX2_1,
+ output FX2_2,
+ output FX2_3,
+ 
+ input wire [11:0] rx_a_a,
+ input wire [11:0] rx_b_a,
+ input wire [11:0] rx_a_b,
+ input wire [11:0] rx_b_b,
+
+ output wire [13:0] tx_a,
+ output wire [13:0] tx_b,
+
+ output wire TXSYNC_A,
+ output wire TXSYNC_B,
+ 
+  // USB interface
+ input usbclk,
+ input wire [2:0] usbctl,
+ output wire [1:0] usbrdy,
+ inout [15:0] usbdata,  // NB Careful, inout
+
+ // These are the general purpose i/o's that go to the daughterboard slots
+ inout wire [15:0] io_tx_a,
+ inout wire [15:0] io_tx_b,
+ inout wire [15:0] io_rx_a,
+ inout wire [15:0] io_rx_b
+ );	
+   wire [15:0] debugdata,debugctrl;
+   assign MYSTERY_SIGNAL = 1'b0;
+   
+   wire clk64,clk128;
+   
+   wire WR = usbctl[0];
+   wire RD = usbctl[1];
+   wire OE = usbctl[2];
+
+   wire have_space, have_pkt_rdy;
+   assign usbrdy[0] = have_space;
+   assign usbrdy[1] = have_pkt_rdy;
+
+   wire   tx_underrun, rx_overrun;    
+   wire   clear_status = FX2_1;
+   assign FX2_2 = rx_overrun;
+   assign FX2_3 = tx_underrun;
+      
+   wire [15:0] usbdata_out;
+   
+   wire [3:0]  dac0mux,dac1mux,dac2mux,dac3mux;
+   
+   wire        tx_realsignals;
+   wire [3:0]  rx_numchan;
+   wire [2:0]  tx_numchan;
+   
+   wire [7:0]  interp_rate, decim_rate;
+   wire [15:0] tx_debugbus, rx_debugbus;
+   
+   wire        enable_tx, enable_rx;
+   wire        reset_data;
+`ifdef MULTI_ON
+   wire        sync_rx;
+   assign reset_data = sync_rx;
+`else
+   assign reset_data = 1'b0;
+`endif //  `ifdef MULTI_ON
+
+   wire        tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset;
+   wire [7:0]  settings;
+   
+   // Tri-state bus macro
+   bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) );
+
+   assign      clk64 = master_clk;
+
+   wire [15:0] ch0tx,ch1tx,ch2tx,ch3tx; //,ch4tx,ch5tx,ch6tx,ch7tx;
+   wire [15:0] ch0rx,ch1rx,ch2rx,ch3rx,ch4rx,ch5rx,ch6rx,ch7rx;
+   
+   // TX
+   wire [15:0] i_out_0,i_out_1,q_out_0,q_out_1;
+   wire [15:0] bb_tx_i0,bb_tx_q0,bb_tx_i1,bb_tx_q1;  // bb_tx_i2,bb_tx_q2,bb_tx_i3,bb_tx_q3;
+   
+   wire        strobe_interp, tx_sample_strobe;
+   wire        tx_empty;
+   
+   wire        serial_strobe;
+   wire [6:0]  serial_addr;
+   wire [31:0] serial_data;
+
+   reg [15:0] debug_counter;
+`ifdef COUNTER_32BIT_ON
+   reg [31:0] sample_counter_32bit;
+`endif //  `ifdef COUNTER_32BIT_ON
+   reg [15:0] loopback_i_0,loopback_q_0;
+   
+   ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+   // Transmit Side
+`ifdef TX_ON
+   assign     bb_tx_i0 = ch0tx;
+   assign      bb_tx_q0 = ch1tx;
+   assign      bb_tx_i1 = ch2tx;
+   assign      bb_tx_q1 = ch3tx;
+   
+   tx_buffer tx_buffer
+     ( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset),
+       .usbdata(usbdata),.WR(WR),.have_space(have_space),.tx_underrun(tx_underrun),
+       .channels({tx_numchan,1'b0}),
+       .tx_i_0(ch0tx),.tx_q_0(ch1tx),
+       .tx_i_1(ch2tx),.tx_q_1(ch3tx),
+       .tx_i_2(),.tx_q_2(),
+       .tx_i_3(),.tx_q_3(),
+       .txclk(clk64),.txstrobe(strobe_interp),
+       .clear_status(clear_status),
+       .tx_empty(tx_empty),
+       .debugbus(tx_debugbus) );
+
+   tx_chain tx_chain_0
+     ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
+       .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe),
+       .interpolator_strobe(strobe_interp),.freq(),
+       .i_in(bb_tx_i0),.q_in(bb_tx_q0),.i_out(i_out_0),.q_out(q_out_0) );
+
+   tx_chain tx_chain_1
+     ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
+       .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe),
+       .interpolator_strobe(strobe_interp),.freq(),
+       .i_in(bb_tx_i1),.q_in(bb_tx_q1),.i_out(i_out_1),.q_out(q_out_1) );
+
+   setting_reg #(`FR_TX_MUX) 
+     sr_txmux(.clock(clk64),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
+	      .out({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan}));
+   
+   wire [15:0] tx_a_a = dac0mux[3] ? (dac0mux[1] ? (dac0mux[0] ? q_out_1 : i_out_1) : (dac0mux[0] ? q_out_0 : i_out_0)) : 16'b0;
+   wire [15:0] tx_b_a = dac1mux[3] ? (dac1mux[1] ? (dac1mux[0] ? q_out_1 : i_out_1) : (dac1mux[0] ? q_out_0 : i_out_0)) : 16'b0;
+   wire [15:0] tx_a_b = dac2mux[3] ? (dac2mux[1] ? (dac2mux[0] ? q_out_1 : i_out_1) : (dac2mux[0] ? q_out_0 : i_out_0)) : 16'b0;
+   wire [15:0] tx_b_b = dac3mux[3] ? (dac3mux[1] ? (dac3mux[0] ? q_out_1 : i_out_1) : (dac3mux[0] ? q_out_0 : i_out_0)) : 16'b0;
+
+   wire txsync = tx_sample_strobe;
+   assign TXSYNC_A = txsync;
+   assign TXSYNC_B = txsync;
+
+   assign tx_a = txsync ? tx_b_a[15:2] : tx_a_a[15:2];
+   assign tx_b = txsync ? tx_b_b[15:2] : tx_a_b[15:2];
+`endif //  `ifdef TX_ON
+   
+   /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+   // Receive Side
+`ifdef RX_ON
+   wire        rx_sample_strobe,strobe_decim,hb_strobe;
+   wire [15:0] bb_rx_i0,bb_rx_q0,bb_rx_i1,bb_rx_q1,
+	       bb_rx_i2,bb_rx_q2,bb_rx_i3,bb_rx_q3;
+
+   wire loopback = settings[0];
+   wire counter = settings[1];
+`ifdef COUNTER_32BIT_ON
+   wire counter_32bit = settings[2];
+
+   always @(posedge clk64)
+     if(rx_dsp_reset)
+       sample_counter_32bit <= #1 32'd0;
+     else if(~enable_rx | reset_data)
+       sample_counter_32bit <=#1 32'd0;
+     else if(hb_strobe)
+       sample_counter_32bit <=#1 sample_counter_32bit + 32'd1;
+`endif //  `ifdef COUNTER_32BIT_ON
+
+   always @(posedge clk64)
+     if(rx_dsp_reset)
+       debug_counter <= #1 16'd0;
+     else if(~enable_rx)
+       debug_counter <= #1 16'd0;
+     else if(hb_strobe)
+       debug_counter <=#1 debug_counter + 16'd2;
+   
+   always @(posedge clk64)
+     if(strobe_interp)
+       begin
+	  loopback_i_0 <= #1 ch0tx;
+	  loopback_q_0 <= #1 ch1tx;
+       end
+   
+`ifdef COUNTER_32BIT_ON
+   assign ch0rx = counter_32bit?sample_counter_32bit[31:16]:counter ? debug_counter : loopback ? loopback_i_0 : bb_rx_i0;
+   assign ch1rx = counter_32bit?sample_counter_32bit[15:0]:counter ? debug_counter + 16'd1 : loopback ? loopback_q_0 : bb_rx_q0;
+   assign ch2rx = bb_rx_i1;
+   assign ch3rx = bb_rx_q1;
+   assign ch4rx = counter_32bit?bb_rx_i0:bb_rx_i2;
+   assign ch5rx = counter_32bit?bb_rx_q0:bb_rx_q2;// If using counter replicate channels here to be able to get rx_i0 when using counter
+                           //This means if you use 4 channels that channel 3 will be replaced by channel 0
+                           // and channel 0 will output the 32 bit counter.
+   assign ch6rx = bb_rx_i3;
+   assign ch7rx = bb_rx_q3;
+`else
+   assign ch0rx = counter ? debug_counter : loopback ? loopback_i_0 : bb_rx_i0;
+   assign ch1rx = counter ? debug_counter + 16'd1 : loopback ? loopback_q_0 : bb_rx_q0;
+   assign ch2rx = bb_rx_i1;
+   assign ch3rx = bb_rx_q1;
+   assign ch4rx = bb_rx_i2;
+   assign ch5rx = bb_rx_q2;
+   assign ch6rx = bb_rx_i3;
+   assign ch7rx = bb_rx_q3;
+`endif //  `ifdef COUNTER_32BIT_ON
+
+
+   wire [15:0] ddc0_in_i,ddc0_in_q,ddc1_in_i,ddc1_in_q,ddc2_in_i,ddc2_in_q,ddc3_in_i,ddc3_in_q;
+   adc_interface adc_interface(.clock(clk64),.reset(rx_dsp_reset),.enable(1'b1),
+			       .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+			       .rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(rx_a_b),.rx_b_b(rx_b_b),
+			       .ddc0_in_i(ddc0_in_i),.ddc0_in_q(ddc0_in_q),
+			       .ddc1_in_i(ddc1_in_i),.ddc1_in_q(ddc1_in_q),
+			       .ddc2_in_i(ddc2_in_i),.ddc2_in_q(ddc2_in_q),
+			       .ddc3_in_i(ddc3_in_i),.ddc3_in_q(ddc3_in_q),.rx_numchan(rx_numchan) );
+   
+   rx_buffer rx_buffer
+     ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset | reset_data),
+       .reset_regs(rx_dsp_reset),
+       .usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun),
+       .channels(rx_numchan),
+       .ch_0(ch0rx),.ch_1(ch1rx),
+       .ch_2(ch2rx),.ch_3(ch3rx),
+       .ch_4(ch4rx),.ch_5(ch5rx),
+       .ch_6(ch6rx),.ch_7(ch7rx),
+       .rxclk(clk64),.rxstrobe(hb_strobe),
+       .clear_status(clear_status),
+       .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+       .debugbus(rx_debugbus) );
+   
+ `ifdef RX_EN_0
+   rx_chain #(`FR_RX_FREQ_0,`FR_RX_PHASE_0) rx_chain_0
+     ( .clock(clk64),.reset(reset_data),.enable(enable_rx),
+       .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(hb_strobe),
+       .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+       .i_in(ddc0_in_i),.q_in(ddc0_in_q),.i_out(bb_rx_i0),.q_out(bb_rx_q0),.debugdata(debugdata),.debugctrl(debugctrl));
+ `else
+   assign      bb_rx_i0=16'd0;
+   assign      bb_rx_q0=16'd0;
+ `endif
+   
+ `ifdef RX_EN_1
+   rx_chain #(`FR_RX_FREQ_1,`FR_RX_PHASE_1) rx_chain_1
+     ( .clock(clk64),.reset(reset_data),.enable(enable_rx),
+       .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
+       .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+       .i_in(ddc1_in_i),.q_in(ddc1_in_q),.i_out(bb_rx_i1),.q_out(bb_rx_q1));
+ `else
+   assign      bb_rx_i1=16'd0;
+   assign      bb_rx_q1=16'd0;
+ `endif
+   
+ `ifdef RX_EN_2
+   rx_chain #(`FR_RX_FREQ_2,`FR_RX_PHASE_2) rx_chain_2
+     ( .clock(clk64),.reset(reset_data),.enable(enable_rx),
+       .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
+       .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+       .i_in(ddc2_in_i),.q_in(ddc2_in_q),.i_out(bb_rx_i2),.q_out(bb_rx_q2));
+ `else
+   assign      bb_rx_i2=16'd0;
+   assign      bb_rx_q2=16'd0;
+ `endif
+
+ `ifdef RX_EN_3
+   rx_chain #(`FR_RX_FREQ_3,`FR_RX_PHASE_3) rx_chain_3
+     ( .clock(clk64),.reset(reset_data),.enable(enable_rx),
+       .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
+       .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+       .i_in(ddc3_in_i),.q_in(ddc3_in_q),.i_out(bb_rx_i3),.q_out(bb_rx_q3));
+   assign      bb_rx_i3=16'd0;
+   assign      bb_rx_q3=16'd0;
+ `endif
+
+`endif //  `ifdef RX_ON
+   
+   ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+   // Control Functions
+
+   wire [31:0] capabilities;
+   assign      capabilities[7] =   `TX_CAP_HB;
+   assign      capabilities[6:4] = `TX_CAP_NCHAN;
+   assign      capabilities[3] =   `RX_CAP_HB;
+   assign      capabilities[2:0] = `RX_CAP_NCHAN;
+
+
+   serial_io serial_io
+     ( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI),
+       .enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO),
+       .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+       .readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_b,io_tx_b}),.readback_2(capabilities),.readback_3(32'hf0f0931a) );
+
+   wire [15:0] reg_0,reg_1,reg_2,reg_3;
+
+`ifdef MULTI_ON
+
+   master_control_multi master_control
+     ( .master_clk(clk64),.usbclk(usbclk),
+       .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+       .rx_slave_sync(io_rx_a[`bitnoFR_RX_SYNC_INPUT_IOPIN]),
+       .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset),
+       .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset),
+       .enable_tx(enable_tx),.enable_rx(enable_rx),
+       .sync_rx(sync_rx),
+       .interp_rate(interp_rate),.decim_rate(decim_rate),
+       .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp),
+       .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim),
+       .tx_empty(tx_empty),
+       //.debug_0(rx_a_a),.debug_1(ddc0_in_i),
+       .debug_0(rx_debugbus),.debug_1(ddc0_in_i),
+       .debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,tx_underrun,rx_overrun,decim_rate}),
+       .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) );
+
+`else //`ifdef MULTI_ON
+
+   master_control master_control
+     ( .master_clk(clk64),.usbclk(usbclk),
+       .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+       .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset),
+       .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset),
+       .enable_tx(enable_tx),.enable_rx(enable_rx),
+       .interp_rate(interp_rate),.decim_rate(decim_rate),
+       .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp),
+       .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim),
+       .tx_empty(tx_empty),
+       //.debug_0(rx_a_a),.debug_1(ddc0_in_i),
+       .debug_0(rx_debugbus),.debug_1(ddc0_in_i),
+       .debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,tx_underrun,rx_overrun,decim_rate}),
+       .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) );
+
+`endif //`ifdef MULTI_ON   
+
+   io_pins io_pins
+     (.io_0(io_tx_a),.io_1(io_rx_a),.io_2(io_tx_b),.io_3(io_rx_b),
+      .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3),
+      .clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset),
+      .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
+   
+   ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+   // Misc Settings
+   setting_reg #(`FR_MODE) sr_misc(.clock(clk64),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(settings));
+
+endmodule // usrp_multi