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author | Josh Blum <josh@joshknows.com> | 2010-04-15 11:24:41 -0700 |
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committer | Josh Blum <josh@joshknows.com> | 2010-04-15 11:24:41 -0700 |
commit | 3a196c5d614fbec9b1010b3082245614ba5e0dc9 (patch) | |
tree | 784f075298f5d86c9e7429ce0ff977deaf4315c8 /fpga/usrp1/sdr_lib/ram64.v | |
parent | cbf7a0916f0455743d8446a8edc0f0775e3e63ed (diff) | |
parent | 05d77f772317de5d925301aa11bb9a880656dd05 (diff) | |
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Merge branch 'udp'
Diffstat (limited to 'fpga/usrp1/sdr_lib/ram64.v')
-rw-r--r-- | fpga/usrp1/sdr_lib/ram64.v | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/fpga/usrp1/sdr_lib/ram64.v b/fpga/usrp1/sdr_lib/ram64.v new file mode 100644 index 000000000..084545808 --- /dev/null +++ b/fpga/usrp1/sdr_lib/ram64.v @@ -0,0 +1,16 @@ + + +module ram64 (input clock, input write, + input [5:0] wr_addr, input [15:0] wr_data, + input [5:0] rd_addr, output reg [15:0] rd_data); + + reg [15:0] ram_array [0:63]; + + always @(posedge clock) + rd_data <= #1 ram_array[rd_addr]; + + always @(posedge clock) + if(write) + ram_array[wr_addr] <= #1 wr_data; + +endmodule // ram64 |