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authorJosh Blum <josh@joshknows.com>2010-04-16 09:42:46 +0000
committerJosh Blum <josh@joshknows.com>2010-04-16 09:42:46 +0000
commit835cb56ef820a69e1e6e0ccde7c5a0e78ca5ad25 (patch)
tree4fe48bdaf92311deedfbe1a5e77dd209468a2d7d /fpga/usrp1/sdr_lib/ram32.v
parentf1838b9284a124fcfb5996eaf1647a69b4473278 (diff)
parent067491b58676cbdaa754334949a8ffc2daf32979 (diff)
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Merge branch 'master' of git@ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
Conflicts: .gitignore
Diffstat (limited to 'fpga/usrp1/sdr_lib/ram32.v')
-rw-r--r--fpga/usrp1/sdr_lib/ram32.v17
1 files changed, 17 insertions, 0 deletions
diff --git a/fpga/usrp1/sdr_lib/ram32.v b/fpga/usrp1/sdr_lib/ram32.v
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+++ b/fpga/usrp1/sdr_lib/ram32.v
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+
+
+module ram32 (input clock, input write,
+ input [4:0] wr_addr, input [15:0] wr_data,
+ input [4:0] rd_addr, output reg [15:0] rd_data);
+
+ reg [15:0] ram_array [0:31];
+
+ always @(posedge clock)
+ rd_data <= #1 ram_array[rd_addr];
+
+ always @(posedge clock)
+ if(write)
+ ram_array[wr_addr] <= #1 wr_data;
+
+endmodule // ram32
+