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authorJosh Blum <josh@joshknows.com>2010-04-16 09:42:46 +0000
committerJosh Blum <josh@joshknows.com>2010-04-16 09:42:46 +0000
commit835cb56ef820a69e1e6e0ccde7c5a0e78ca5ad25 (patch)
tree4fe48bdaf92311deedfbe1a5e77dd209468a2d7d /fpga/usrp1/models/fifo_2k.v
parentf1838b9284a124fcfb5996eaf1647a69b4473278 (diff)
parent067491b58676cbdaa754334949a8ffc2daf32979 (diff)
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Merge branch 'master' of git@ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
Conflicts: .gitignore
Diffstat (limited to 'fpga/usrp1/models/fifo_2k.v')
-rw-r--r--fpga/usrp1/models/fifo_2k.v24
1 files changed, 24 insertions, 0 deletions
diff --git a/fpga/usrp1/models/fifo_2k.v b/fpga/usrp1/models/fifo_2k.v
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+
+
+module fifo_2k
+ ( input [15:0] data,
+ input wrreq,
+ input rdreq,
+ input rdclk,
+ input wrclk,
+ input aclr,
+ output [15:0] q,
+ output rdfull,
+ output rdempty,
+ output [10:0] rdusedw,
+ output wrfull,
+ output wrempty,
+ output [10:0] wrusedw
+ );
+
+fifo #(.width(16),.depth(2048),.addr_bits(11)) fifo_2k
+ ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
+ rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
+
+endmodule // fifo_1k
+