Removed copy of FPGA source files.

61 files changed, 0 insertions, 12489 deletions

diff --git a/fpga/usrp1/megacells/.gitignore b/fpga/usrp1/megacells/.gitignore
deleted file mode 100644
index c2de89b27..000000000
--- a/fpga/usrp1/megacells/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-/db
diff --git a/fpga/usrp1/megacells/accum32.bsf b/fpga/usrp1/megacells/accum32.bsf
deleted file mode 100755
index 494a8200f..000000000
--- a/fpga/usrp1/megacells/accum32.bsf
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 1991-2003 Altera Corporation
-Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-support information,  device programming or simulation file,  and any other
-associated  documentation or information  provided by  Altera  or a partner
-under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-other  use  of such  megafunction  design,  netlist,  support  information,
-device programming or simulation file,  or any other  related documentation
-or information  is prohibited  for  any  other purpose,  including, but not
-limited to  modification,  reverse engineering,  de-compiling, or use  with
-any other  silicon devices,  unless such use is  explicitly  licensed under
-a separate agreement with  Altera  or a megafunction partner.  Title to the
-intellectual property,  including patents,  copyrights,  trademarks,  trade
-secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-support  information,  device programming or simulation file,  or any other
-related documentation or information provided by  Altera  or a megafunction
-partner, remains with Altera, the megafunction partner, or their respective
-licensors. No other licenses, including any licenses needed under any third
-party's intellectual property, are provided herein.
-*/
-(header "symbol" (version "1.1"))
-(symbol
-	(rect 0 0 240 120)
-	(text "accum32" (rect 87 2 166 21)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 101 31 116)(font "Arial" ))
-	(port
-		(pt 0 40)
-		(input)
-		(text "data[31..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "data[31..0]" (rect 20 24 82 40)(font "Arial" (font_size 8)))
-		(line (pt 0 40)(pt 16 40)(line_width 3))
-	)
-	(port
-		(pt 0 56)
-		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 20 40 51 56)(font "Arial" (font_size 8)))
-		(line (pt 0 56)(pt 16 56)(line_width 1))
-	)
-	(port
-		(pt 0 72)
-		(input)
-		(text "clken" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clken" (rect 20 56 51 72)(font "Arial" (font_size 8)))
-		(line (pt 0 72)(pt 16 72)(line_width 1))
-	)
-	(port
-		(pt 0 96)
-		(input)
-		(text "aclr" (rect 0 0 24 16)(font "Arial" (font_size 8)))
-		(text "aclr" (rect 20 80 41 96)(font "Arial" (font_size 8)))
-		(line (pt 0 96)(pt 16 96)(line_width 1))
-	)
-	(port
-		(pt 240 56)
-		(output)
-		(text "result[31..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "result[31..0]" (rect 152 40 221 56)(font "Arial" (font_size 8)))
-		(line (pt 240 56)(pt 224 56)(line_width 3))
-	)
-	(drawing
-		(text "acc" (rect 102 48 123 64)(font "Arial" (font_size 8)))
-		(text "SIGNED" (rect 177 18 214 32)(font "Arial" ))
-		(line (pt 16 16)(pt 224 16)(line_width 1))
-		(line (pt 16 16)(pt 16 104)(line_width 1))
-		(line (pt 16 104)(pt 224 104)(line_width 1))
-		(line (pt 224 16)(pt 224 104)(line_width 1))
-		(line (pt 88 24)(pt 136 48)(line_width 1))
-		(line (pt 136 64)(pt 136 48)(line_width 1))
-		(line (pt 88 88)(pt 136 64)(line_width 1))
-		(line (pt 88 24)(pt 88 88)(line_width 1))
-		(line (pt 16 40)(pt 88 40)(line_width 1))
-		(line (pt 16 56)(pt 88 56)(line_width 1))
-		(line (pt 136 56)(pt 224 56)(line_width 1))
-		(line (pt 16 72)(pt 88 72)(line_width 1))
-		(line (pt 16 72)(pt 88 72)(line_width 1))
-		(line (pt 16 96)(pt 104 96)(line_width 1))
-		(line (pt 104 96)(pt 104 80)(line_width 1))
-	)
-)
diff --git a/fpga/usrp1/megacells/accum32.cmp b/fpga/usrp1/megacells/accum32.cmp
deleted file mode 100755
index 55b5fdc22..000000000
--- a/fpga/usrp1/megacells/accum32.cmp
+++ /dev/null
@@ -1,31 +0,0 @@
---Copyright (C) 1991-2003 Altera Corporation
---Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
---support information,  device programming or simulation file,  and any other
---associated  documentation or information  provided by  Altera  or a partner
---under  Altera's   Megafunction   Partnership   Program  may  be  used  only
---to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
---other  use  of such  megafunction  design,  netlist,  support  information,
---device programming or simulation file,  or any other  related documentation
---or information  is prohibited  for  any  other purpose,  including, but not
---limited to  modification,  reverse engineering,  de-compiling, or use  with
---any other  silicon devices,  unless such use is  explicitly  licensed under
---a separate agreement with  Altera  or a megafunction partner.  Title to the
---intellectual property,  including patents,  copyrights,  trademarks,  trade
---secrets,  or maskworks,  embodied in any such megafunction design, netlist,
---support  information,  device programming or simulation file,  or any other
---related documentation or information provided by  Altera  or a megafunction
---partner, remains with Altera, the megafunction partner, or their respective
---licensors. No other licenses, including any licenses needed under any third
---party's intellectual property, are provided herein.
-
-
-component accum32
-	PORT
-	(
-		data		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-		clock		: IN STD_LOGIC  := '0';
-		clken		: IN STD_LOGIC  := '1';
-		aclr		: IN STD_LOGIC  := '0';
-		result		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
-	);
-end component;
diff --git a/fpga/usrp1/megacells/accum32.inc b/fpga/usrp1/megacells/accum32.inc
deleted file mode 100755
index 6c6690025..000000000
--- a/fpga/usrp1/megacells/accum32.inc
+++ /dev/null
@@ -1,32 +0,0 @@
---Copyright (C) 1991-2003 Altera Corporation
---Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
---support information,  device programming or simulation file,  and any other
---associated  documentation or information  provided by  Altera  or a partner
---under  Altera's   Megafunction   Partnership   Program  may  be  used  only
---to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
---other  use  of such  megafunction  design,  netlist,  support  information,
---device programming or simulation file,  or any other  related documentation
---or information  is prohibited  for  any  other purpose,  including, but not
---limited to  modification,  reverse engineering,  de-compiling, or use  with
---any other  silicon devices,  unless such use is  explicitly  licensed under
---a separate agreement with  Altera  or a megafunction partner.  Title to the
---intellectual property,  including patents,  copyrights,  trademarks,  trade
---secrets,  or maskworks,  embodied in any such megafunction design, netlist,
---support  information,  device programming or simulation file,  or any other
---related documentation or information provided by  Altera  or a megafunction
---partner, remains with Altera, the megafunction partner, or their respective
---licensors. No other licenses, including any licenses needed under any third
---party's intellectual property, are provided herein.
-
-
-FUNCTION accum32 
-(
-	data[31..0],
-	clock,
-	clken,
-	aclr
-)
-
-RETURNS (
-	result[31..0]
-);
diff --git a/fpga/usrp1/megacells/accum32.v b/fpga/usrp1/megacells/accum32.v
deleted file mode 100755
index ce50cbbf1..000000000
--- a/fpga/usrp1/megacells/accum32.v
+++ /dev/null
@@ -1,765 +0,0 @@
-// megafunction wizard: %ALTACCUMULATE%CBX%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: altaccumulate 
-
-// ============================================================
-// File Name: accum32.v
-// Megafunction Name(s):
-// 			altaccumulate
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-// ************************************************************
-
-
-//Copyright (C) 1991-2003 Altera Corporation
-//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-//support information,  device programming or simulation file,  and any other
-//associated  documentation or information  provided by  Altera  or a partner
-//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-//other  use  of such  megafunction  design,  netlist,  support  information,
-//device programming or simulation file,  or any other  related documentation
-//or information  is prohibited  for  any  other purpose,  including, but not
-//limited to  modification,  reverse engineering,  de-compiling, or use  with
-//any other  silicon devices,  unless such use is  explicitly  licensed under
-//a separate agreement with  Altera  or a megafunction partner.  Title to the
-//intellectual property,  including patents,  copyrights,  trademarks,  trade
-//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-//support  information,  device programming or simulation file,  or any other
-//related documentation or information provided by  Altera  or a megafunction
-//partner, remains with Altera, the megafunction partner, or their respective
-//licensors. No other licenses, including any licenses needed under any third
-//party's intellectual property, are provided herein.
-
-
-//altaccumulate DEVICE_FAMILY=Cyclone LPM_REPRESENTATION=SIGNED WIDTH_IN=32 WIDTH_OUT=32 aclr clken clock data result
-//VERSION_BEGIN 3.0 cbx_altaccumulate 2003:04:08:16:04:48:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ  VERSION_END
-
-//synthesis_resources = lut 32 
-module  accum32_accum_nta
-	( 
-	aclr,
-	clken,
-	clock,
-	data,
-	result) /* synthesis synthesis_clearbox=1 */;
-	input   aclr;
-	input   clken;
-	input   clock;
-	input   [31:0]  data;
-	output   [31:0]  result;
-
-	wire  [0:0]   wire_acc_cella_0cout;
-	wire  [0:0]   wire_acc_cella_1cout;
-	wire  [0:0]   wire_acc_cella_2cout;
-	wire  [0:0]   wire_acc_cella_3cout;
-	wire  [0:0]   wire_acc_cella_4cout;
-	wire  [0:0]   wire_acc_cella_5cout;
-	wire  [0:0]   wire_acc_cella_6cout;
-	wire  [0:0]   wire_acc_cella_7cout;
-	wire  [0:0]   wire_acc_cella_8cout;
-	wire  [0:0]   wire_acc_cella_9cout;
-	wire  [0:0]   wire_acc_cella_10cout;
-	wire  [0:0]   wire_acc_cella_11cout;
-	wire  [0:0]   wire_acc_cella_12cout;
-	wire  [0:0]   wire_acc_cella_13cout;
-	wire  [0:0]   wire_acc_cella_14cout;
-	wire  [0:0]   wire_acc_cella_15cout;
-	wire  [0:0]   wire_acc_cella_16cout;
-	wire  [0:0]   wire_acc_cella_17cout;
-	wire  [0:0]   wire_acc_cella_18cout;
-	wire  [0:0]   wire_acc_cella_19cout;
-	wire  [0:0]   wire_acc_cella_20cout;
-	wire  [0:0]   wire_acc_cella_21cout;
-	wire  [0:0]   wire_acc_cella_22cout;
-	wire  [0:0]   wire_acc_cella_23cout;
-	wire  [0:0]   wire_acc_cella_24cout;
-	wire  [0:0]   wire_acc_cella_25cout;
-	wire  [0:0]   wire_acc_cella_26cout;
-	wire  [0:0]   wire_acc_cella_27cout;
-	wire  [0:0]   wire_acc_cella_28cout;
-	wire  [0:0]   wire_acc_cella_29cout;
-	wire  [0:0]   wire_acc_cella_30cout;
-	wire  [31:0]   wire_acc_cella_dataa;
-	wire  [31:0]   wire_acc_cella_datab;
-	wire  [31:0]   wire_acc_cella_datac;
-	wire  [31:0]   wire_acc_cella_regout;
-	wire sload;
-
-	stratix_lcell   acc_cella_0
-	( 
-	.aclr(aclr),
-	.cin(1'b0),
-	.clk(clock),
-	.cout(wire_acc_cella_0cout[0:0]),
-	.dataa(wire_acc_cella_dataa[0:0]),
-	.datab(wire_acc_cella_datab[0:0]),
-	.datac(wire_acc_cella_datac[0:0]),
-	.ena(clken),
-	.regout(wire_acc_cella_regout[0:0]),
-	.sload(sload));
-	defparam
-		acc_cella_0.cin_used = "true",
-		acc_cella_0.lut_mask = "96e8",
-		acc_cella_0.operation_mode = "arithmetic",
-		acc_cella_0.sum_lutc_input = "cin",
-		acc_cella_0.synch_mode = "on",
-		acc_cella_0.lpm_type = "stratix_lcell";
-	stratix_lcell   acc_cella_1
-	( 
-	.aclr(aclr),
-	.cin(wire_acc_cella_0cout[0:0]),
-	.clk(clock),
-	.cout(wire_acc_cella_1cout[0:0]),
-	.dataa(wire_acc_cella_dataa[1:1]),
-	.datab(wire_acc_cella_datab[1:1]),
-	.datac(wire_acc_cella_datac[1:1]),
-	.ena(clken),
-	.regout(wire_acc_cella_regout[1:1]),
-	.sload(sload));
-	defparam
-		acc_cella_1.cin_used = "true",
-		acc_cella_1.lut_mask = "96e8",
-		acc_cella_1.operation_mode = "arithmetic",
-		acc_cella_1.sum_lutc_input = "cin",
-		acc_cella_1.synch_mode = "on",
-		acc_cella_1.lpm_type = "stratix_lcell";
-	stratix_lcell   acc_cella_2
-	( 
-	.aclr(aclr),
-	.cin(wire_acc_cella_1cout[0:0]),
-	.clk(clock),
-	.cout(wire_acc_cella_2cout[0:0]),
-	.dataa(wire_acc_cella_dataa[2:2]),
-	.datab(wire_acc_cella_datab[2:2]),
-	.datac(wire_acc_cella_datac[2:2]),
-	.ena(clken),
-	.regout(wire_acc_cella_regout[2:2]),
-	.sload(sload));
-	defparam
-		acc_cella_2.cin_used = "true",
-		acc_cella_2.lut_mask = "96e8",
-		acc_cella_2.operation_mode = "arithmetic",
-		acc_cella_2.sum_lutc_input = "cin",
-		acc_cella_2.synch_mode = "on",
-		acc_cella_2.lpm_type = "stratix_lcell";
-	stratix_lcell   acc_cella_3
-	( 
-	.aclr(aclr),
-	.cin(wire_acc_cella_2cout[0:0]),
-	.clk(clock),
-	.cout(wire_acc_cella_3cout[0:0]),
-	.dataa(wire_acc_cella_dataa[3:3]),
-	.datab(wire_acc_cella_datab[3:3]),
-	.datac(wire_acc_cella_datac[3:3]),
-	.ena(clken),
-	.regout(wire_acc_cella_regout[3:3]),
-	.sload(sload));
-	defparam
-		acc_cella_3.cin_used = "true",
-		acc_cella_3.lut_mask = "96e8",
-		acc_cella_3.operation_mode = "arithmetic",
-		acc_cella_3.sum_lutc_input = "cin",
-		acc_cella_3.synch_mode = "on",
-		acc_cella_3.lpm_type = "stratix_lcell";
-	stratix_lcell   acc_cella_4
-	( 
-	.aclr(aclr),
-	.cin(wire_acc_cella_3cout[0:0]),
-	.clk(clock),
-	.cout(wire_acc_cella_4cout[0:0]),
-	.dataa(wire_acc_cella_dataa[4:4]),
-	.datab(wire_acc_cella_datab[4:4]),
-	.datac(wire_acc_cella_datac[4:4]),
-	.ena(clken),
-	.regout(wire_acc_cella_regout[4:4]),
-	.sload(sload));
-	defparam
-		acc_cella_4.cin_used = "true",
-		acc_cella_4.lut_mask = "96e8",
-		acc_cella_4.operation_mode = "arithmetic",
-		acc_cella_4.sum_lutc_input = "cin",
-		acc_cella_4.synch_mode = "on",
-		acc_cella_4.lpm_type = "stratix_lcell";
-	stratix_lcell   acc_cella_5
-	( 
-	.aclr(aclr),
-	.cin(wire_acc_cella_4cout[0:0]),
-	.clk(clock),
-	.cout(wire_acc_cella_5cout[0:0]),
-	.dataa(wire_acc_cella_dataa[5:5]),
-	.datab(wire_acc_cella_datab[5:5]),
-	.datac(wire_acc_cella_datac[5:5]),
-	.ena(clken),
-	.regout(wire_acc_cella_regout[5:5]),
-	.sload(sload));
-	defparam
-		acc_cella_5.cin_used = "true",
-		acc_cella_5.lut_mask = "96e8",
-		acc_cella_5.operation_mode = "arithmetic",
-		acc_cella_5.sum_lutc_input = "cin",
-		acc_cella_5.synch_mode = "on",
-		acc_cella_5.lpm_type = "stratix_lcell";
-	stratix_lcell   acc_cella_6
-	( 
-	.aclr(aclr),
-	.cin(wire_acc_cella_5cout[0:0]),
-	.clk(clock),
-	.cout(wire_acc_cella_6cout[0:0]),
-	.dataa(wire_acc_cella_dataa[6:6]),
-	.datab(wire_acc_cella_datab[6:6]),
-	.datac(wire_acc_cella_datac[6:6]),
-	.ena(clken),
-	.regout(wire_acc_cella_regout[6:6]),
-	.sload(sload));
-	defparam
-		acc_cella_6.cin_used = "true",
-		acc_cella_6.lut_mask = "96e8",
-		acc_cella_6.operation_mode = "arithmetic",
-		acc_cella_6.sum_lutc_input = "cin",
-		acc_cella_6.synch_mode = "on",
-		acc_cella_6.lpm_type = "stratix_lcell";
-	stratix_lcell   acc_cella_7
-	( 
-	.aclr(aclr),
-	.cin(wire_acc_cella_6cout[0:0]),
-	.clk(clock),
-	.cout(wire_acc_cella_7cout[0:0]),
-	.dataa(wire_acc_cella_dataa[7:7]),
-	.datab(wire_acc_cella_datab[7:7]),
-	.datac(wire_acc_cella_datac[7:7]),
-	.ena(clken),
-	.regout(wire_acc_cella_regout[7:7]),
-	.sload(sload));
-	defparam
-		acc_cella_7.cin_used = "true",
-		acc_cella_7.lut_mask = "96e8",
-		acc_cella_7.operation_mode = "arithmetic",
-		acc_cella_7.sum_lutc_input = "cin",
-		acc_cella_7.synch_mode = "on",
-		acc_cella_7.lpm_type = "stratix_lcell";
-	stratix_lcell   acc_cella_8
-	( 
-	.aclr(aclr),
-	.cin(wire_acc_cella_7cout[0:0]),
-	.clk(clock),
-	.cout(wire_acc_cella_8cout[0:0]),
-	.dataa(wire_acc_cella_dataa[8:8]),
-	.datab(wire_acc_cella_datab[8:8]),
-	.datac(wire_acc_cella_datac[8:8]),
-	.ena(clken),
-	.regout(wire_acc_cella_regout[8:8]),
-	.sload(sload));
-	defparam
-		acc_cella_8.cin_used = "true",
-		acc_cella_8.lut_mask = "96e8",
-		acc_cella_8.operation_mode = "arithmetic",
-		acc_cella_8.sum_lutc_input = "cin",
-		acc_cella_8.synch_mode = "on",
-		acc_cella_8.lpm_type = "stratix_lcell";
-	stratix_lcell   acc_cella_9
-	( 
-	.aclr(aclr),
-	.cin(wire_acc_cella_8cout[0:0]),
-	.clk(clock),
-	.cout(wire_acc_cella_9cout[0:0]),
-	.dataa(wire_acc_cella_dataa[9:9]),
-	.datab(wire_acc_cella_datab[9:9]),
-	.datac(wire_acc_cella_datac[9:9]),
-	.ena(clken),
-	.regout(wire_acc_cella_regout[9:9]),
-	.sload(sload));
-	defparam
-		acc_cella_9.cin_used = "true",
-		acc_cella_9.lut_mask = "96e8",
-		acc_cella_9.operation_mode = "arithmetic",
-		acc_cella_9.sum_lutc_input = "cin",
-		acc_cella_9.synch_mode = "on",
-		acc_cella_9.lpm_type = "stratix_lcell";
-	stratix_lcell   acc_cella_10
-	( 
-	.aclr(aclr),
-	.cin(wire_acc_cella_9cout[0:0]),
-	.clk(clock),
-	.cout(wire_acc_cella_10cout[0:0]),
-	.dataa(wire_acc_cella_dataa[10:10]),
-	.datab(wire_acc_cella_datab[10:10]),
-	.datac(wire_acc_cella_datac[10:10]),
-	.ena(clken),
-	.regout(wire_acc_cella_regout[10:10]),
-	.sload(sload));
-	defparam
-		acc_cella_10.cin_used = "true",
-		acc_cella_10.lut_mask = "96e8",
-		acc_cella_10.operation_mode = "arithmetic",
-		acc_cella_10.sum_lutc_input = "cin",
-		acc_cella_10.synch_mode = "on",
-		acc_cella_10.lpm_type = "stratix_lcell";
-	stratix_lcell   acc_cella_11
-	( 
-	.aclr(aclr),
-	.cin(wire_acc_cella_10cout[0:0]),
-	.clk(clock),
-	.cout(wire_acc_cella_11cout[0:0]),
-	.dataa(wire_acc_cella_dataa[11:11]),
-	.datab(wire_acc_cella_datab[11:11]),
-	.datac(wire_acc_cella_datac[11:11]),
-	.ena(clken),
-	.regout(wire_acc_cella_regout[11:11]),
-	.sload(sload));
-	defparam
-		acc_cella_11.cin_used = "true",
-		acc_cella_11.lut_mask = "96e8",
-		acc_cella_11.operation_mode = "arithmetic",
-		acc_cella_11.sum_lutc_input = "cin",
-		acc_cella_11.synch_mode = "on",
-		acc_cella_11.lpm_type = "stratix_lcell";
-	stratix_lcell   acc_cella_12
-	( 
-	.aclr(aclr),
-	.cin(wire_acc_cella_11cout[0:0]),
-	.clk(clock),
-	.cout(wire_acc_cella_12cout[0:0]),
-	.dataa(wire_acc_cella_dataa[12:12]),
-	.datab(wire_acc_cella_datab[12:12]),
-	.datac(wire_acc_cella_datac[12:12]),
-	.ena(clken),
-	.regout(wire_acc_cella_regout[12:12]),
-	.sload(sload));
-	defparam
-		acc_cella_12.cin_used = "true",
-		acc_cella_12.lut_mask = "96e8",
-		acc_cella_12.operation_mode = "arithmetic",
-		acc_cella_12.sum_lutc_input = "cin",
-		acc_cella_12.synch_mode = "on",
-		acc_cella_12.lpm_type = "stratix_lcell";
-	stratix_lcell   acc_cella_13
-	( 
-	.aclr(aclr),
-	.cin(wire_acc_cella_12cout[0:0]),
-	.clk(clock),
-	.cout(wire_acc_cella_13cout[0:0]),
-	.dataa(wire_acc_cella_dataa[13:13]),
-	.datab(wire_acc_cella_datab[13:13]),
-	.datac(wire_acc_cella_datac[13:13]),
-	.ena(clken),
-	.regout(wire_acc_cella_regout[13:13]),
-	.sload(sload));
-	defparam
-		acc_cella_13.cin_used = "true",
-		acc_cella_13.lut_mask = "96e8",
-		acc_cella_13.operation_mode = "arithmetic",
-		acc_cella_13.sum_lutc_input = "cin",
-		acc_cella_13.synch_mode = "on",
-		acc_cella_13.lpm_type = "stratix_lcell";
-	stratix_lcell   acc_cella_14
-	( 
-	.aclr(aclr),
-	.cin(wire_acc_cella_13cout[0:0]),
-	.clk(clock),
-	.cout(wire_acc_cella_14cout[0:0]),
-	.dataa(wire_acc_cella_dataa[14:14]),
-	.datab(wire_acc_cella_datab[14:14]),
-	.datac(wire_acc_cella_datac[14:14]),
-	.ena(clken),
-	.regout(wire_acc_cella_regout[14:14]),
-	.sload(sload));
-	defparam
-		acc_cella_14.cin_used = "true",
-		acc_cella_14.lut_mask = "96e8",
-		acc_cella_14.operation_mode = "arithmetic",
-		acc_cella_14.sum_lutc_input = "cin",
-		acc_cella_14.synch_mode = "on",
-		acc_cella_14.lpm_type = "stratix_lcell";
-	stratix_lcell   acc_cella_15
-	( 
-	.aclr(aclr),
-	.cin(wire_acc_cella_14cout[0:0]),
-	.clk(clock),
-	.cout(wire_acc_cella_15cout[0:0]),
-	.dataa(wire_acc_cella_dataa[15:15]),
-	.datab(wire_acc_cella_datab[15:15]),
-	.datac(wire_acc_cella_datac[15:15]),
-	.ena(clken),
-	.regout(wire_acc_cella_regout[15:15]),
-	.sload(sload));
-	defparam
-		acc_cella_15.cin_used = "true",
-		acc_cella_15.lut_mask = "96e8",
-		acc_cella_15.operation_mode = "arithmetic",
-		acc_cella_15.sum_lutc_input = "cin",
-		acc_cella_15.synch_mode = "on",
-		acc_cella_15.lpm_type = "stratix_lcell";
-	stratix_lcell   acc_cella_16
-	( 
-	.aclr(aclr),
-	.cin(wire_acc_cella_15cout[0:0]),
-	.clk(clock),
-	.cout(wire_acc_cella_16cout[0:0]),
-	.dataa(wire_acc_cella_dataa[16:16]),
-	.datab(wire_acc_cella_datab[16:16]),
-	.datac(wire_acc_cella_datac[16:16]),
-	.ena(clken),
-	.regout(wire_acc_cella_regout[16:16]),
-	.sload(sload));
-	defparam
-		acc_cella_16.cin_used = "true",
-		acc_cella_16.lut_mask = "96e8",
-		acc_cella_16.operation_mode = "arithmetic",
-		acc_cella_16.sum_lutc_input = "cin",
-		acc_cella_16.synch_mode = "on",
-		acc_cella_16.lpm_type = "stratix_lcell";
-	stratix_lcell   acc_cella_17
-	( 
-	.aclr(aclr),
-	.cin(wire_acc_cella_16cout[0:0]),
-	.clk(clock),
-	.cout(wire_acc_cella_17cout[0:0]),
-	.dataa(wire_acc_cella_dataa[17:17]),
-	.datab(wire_acc_cella_datab[17:17]),
-	.datac(wire_acc_cella_datac[17:17]),
-	.ena(clken),
-	.regout(wire_acc_cella_regout[17:17]),
-	.sload(sload));
-	defparam
-		acc_cella_17.cin_used = "true",
-		acc_cella_17.lut_mask = "96e8",
-		acc_cella_17.operation_mode = "arithmetic",
-		acc_cella_17.sum_lutc_input = "cin",
-		acc_cella_17.synch_mode = "on",
-		acc_cella_17.lpm_type = "stratix_lcell";
-	stratix_lcell   acc_cella_18
-	( 
-	.aclr(aclr),
-	.cin(wire_acc_cella_17cout[0:0]),
-	.clk(clock),
-	.cout(wire_acc_cella_18cout[0:0]),
-	.dataa(wire_acc_cella_dataa[18:18]),
-	.datab(wire_acc_cella_datab[18:18]),
-	.datac(wire_acc_cella_datac[18:18]),
-	.ena(clken),
-	.regout(wire_acc_cella_regout[18:18]),
-	.sload(sload));
-	defparam
-		acc_cella_18.cin_used = "true",
-		acc_cella_18.lut_mask = "96e8",
-		acc_cella_18.operation_mode = "arithmetic",
-		acc_cella_18.sum_lutc_input = "cin",
-		acc_cella_18.synch_mode = "on",
-		acc_cella_18.lpm_type = "stratix_lcell";
-	stratix_lcell   acc_cella_19
-	( 
-	.aclr(aclr),
-	.cin(wire_acc_cella_18cout[0:0]),
-	.clk(clock),
-	.cout(wire_acc_cella_19cout[0:0]),
-	.dataa(wire_acc_cella_dataa[19:19]),
-	.datab(wire_acc_cella_datab[19:19]),
-	.datac(wire_acc_cella_datac[19:19]),
-	.ena(clken),
-	.regout(wire_acc_cella_regout[19:19]),
-	.sload(sload));
-	defparam
-		acc_cella_19.cin_used = "true",
-		acc_cella_19.lut_mask = "96e8",
-		acc_cella_19.operation_mode = "arithmetic",
-		acc_cella_19.sum_lutc_input = "cin",
-		acc_cella_19.synch_mode = "on",
-		acc_cella_19.lpm_type = "stratix_lcell";
-	stratix_lcell   acc_cella_20
-	( 
-	.aclr(aclr),
-	.cin(wire_acc_cella_19cout[0:0]),
-	.clk(clock),
-	.cout(wire_acc_cella_20cout[0:0]),
-	.dataa(wire_acc_cella_dataa[20:20]),
-	.datab(wire_acc_cella_datab[20:20]),
-	.datac(wire_acc_cella_datac[20:20]),
-	.ena(clken),
-	.regout(wire_acc_cella_regout[20:20]),
-	.sload(sload));
-	defparam
-		acc_cella_20.cin_used = "true",
-		acc_cella_20.lut_mask = "96e8",
-		acc_cella_20.operation_mode = "arithmetic",
-		acc_cella_20.sum_lutc_input = "cin",
-		acc_cella_20.synch_mode = "on",
-		acc_cella_20.lpm_type = "stratix_lcell";
-	stratix_lcell   acc_cella_21
-	( 
-	.aclr(aclr),
-	.cin(wire_acc_cella_20cout[0:0]),
-	.clk(clock),
-	.cout(wire_acc_cella_21cout[0:0]),
-	.dataa(wire_acc_cella_dataa[21:21]),
-	.datab(wire_acc_cella_datab[21:21]),
-	.datac(wire_acc_cella_datac[21:21]),
-	.ena(clken),
-	.regout(wire_acc_cella_regout[21:21]),
-	.sload(sload));
-	defparam
-		acc_cella_21.cin_used = "true",
-		acc_cella_21.lut_mask = "96e8",
-		acc_cella_21.operation_mode = "arithmetic",
-		acc_cella_21.sum_lutc_input = "cin",
-		acc_cella_21.synch_mode = "on",
-		acc_cella_21.lpm_type = "stratix_lcell";
-	stratix_lcell   acc_cella_22
-	( 
-	.aclr(aclr),
-	.cin(wire_acc_cella_21cout[0:0]),
-	.clk(clock),
-	.cout(wire_acc_cella_22cout[0:0]),
-	.dataa(wire_acc_cella_dataa[22:22]),
-	.datab(wire_acc_cella_datab[22:22]),
-	.datac(wire_acc_cella_datac[22:22]),
-	.ena(clken),
-	.regout(wire_acc_cella_regout[22:22]),
-	.sload(sload));
-	defparam
-		acc_cella_22.cin_used = "true",
-		acc_cella_22.lut_mask = "96e8",
-		acc_cella_22.operation_mode = "arithmetic",
-		acc_cella_22.sum_lutc_input = "cin",
-		acc_cella_22.synch_mode = "on",
-		acc_cella_22.lpm_type = "stratix_lcell";
-	stratix_lcell   acc_cella_23
-	( 
-	.aclr(aclr),
-	.cin(wire_acc_cella_22cout[0:0]),
-	.clk(clock),
-	.cout(wire_acc_cella_23cout[0:0]),
-	.dataa(wire_acc_cella_dataa[23:23]),
-	.datab(wire_acc_cella_datab[23:23]),
-	.datac(wire_acc_cella_datac[23:23]),
-	.ena(clken),
-	.regout(wire_acc_cella_regout[23:23]),
-	.sload(sload));
-	defparam
-		acc_cella_23.cin_used = "true",
-		acc_cella_23.lut_mask = "96e8",
-		acc_cella_23.operation_mode = "arithmetic",
-		acc_cella_23.sum_lutc_input = "cin",
-		acc_cella_23.synch_mode = "on",
-		acc_cella_23.lpm_type = "stratix_lcell";
-	stratix_lcell   acc_cella_24
-	( 
-	.aclr(aclr),
-	.cin(wire_acc_cella_23cout[0:0]),
-	.clk(clock),
-	.cout(wire_acc_cella_24cout[0:0]),
-	.dataa(wire_acc_cella_dataa[24:24]),
-	.datab(wire_acc_cella_datab[24:24]),
-	.datac(wire_acc_cella_datac[24:24]),
-	.ena(clken),
-	.regout(wire_acc_cella_regout[24:24]),
-	.sload(sload));
-	defparam
-		acc_cella_24.cin_used = "true",
-		acc_cella_24.lut_mask = "96e8",
-		acc_cella_24.operation_mode = "arithmetic",
-		acc_cella_24.sum_lutc_input = "cin",
-		acc_cella_24.synch_mode = "on",
-		acc_cella_24.lpm_type = "stratix_lcell";
-	stratix_lcell   acc_cella_25
-	( 
-	.aclr(aclr),
-	.cin(wire_acc_cella_24cout[0:0]),
-	.clk(clock),
-	.cout(wire_acc_cella_25cout[0:0]),
-	.dataa(wire_acc_cella_dataa[25:25]),
-	.datab(wire_acc_cella_datab[25:25]),
-	.datac(wire_acc_cella_datac[25:25]),
-	.ena(clken),
-	.regout(wire_acc_cella_regout[25:25]),
-	.sload(sload));
-	defparam
-		acc_cella_25.cin_used = "true",
-		acc_cella_25.lut_mask = "96e8",
-		acc_cella_25.operation_mode = "arithmetic",
-		acc_cella_25.sum_lutc_input = "cin",
-		acc_cella_25.synch_mode = "on",
-		acc_cella_25.lpm_type = "stratix_lcell";
-	stratix_lcell   acc_cella_26
-	( 
-	.aclr(aclr),
-	.cin(wire_acc_cella_25cout[0:0]),
-	.clk(clock),
-	.cout(wire_acc_cella_26cout[0:0]),
-	.dataa(wire_acc_cella_dataa[26:26]),
-	.datab(wire_acc_cella_datab[26:26]),
-	.datac(wire_acc_cella_datac[26:26]),
-	.ena(clken),
-	.regout(wire_acc_cella_regout[26:26]),
-	.sload(sload));
-	defparam
-		acc_cella_26.cin_used = "true",
-		acc_cella_26.lut_mask = "96e8",
-		acc_cella_26.operation_mode = "arithmetic",
-		acc_cella_26.sum_lutc_input = "cin",
-		acc_cella_26.synch_mode = "on",
-		acc_cella_26.lpm_type = "stratix_lcell";
-	stratix_lcell   acc_cella_27
-	( 
-	.aclr(aclr),
-	.cin(wire_acc_cella_26cout[0:0]),
-	.clk(clock),
-	.cout(wire_acc_cella_27cout[0:0]),
-	.dataa(wire_acc_cella_dataa[27:27]),
-	.datab(wire_acc_cella_datab[27:27]),
-	.datac(wire_acc_cella_datac[27:27]),
-	.ena(clken),
-	.regout(wire_acc_cella_regout[27:27]),
-	.sload(sload));
-	defparam
-		acc_cella_27.cin_used = "true",
-		acc_cella_27.lut_mask = "96e8",
-		acc_cella_27.operation_mode = "arithmetic",
-		acc_cella_27.sum_lutc_input = "cin",
-		acc_cella_27.synch_mode = "on",
-		acc_cella_27.lpm_type = "stratix_lcell";
-	stratix_lcell   acc_cella_28
-	( 
-	.aclr(aclr),
-	.cin(wire_acc_cella_27cout[0:0]),
-	.clk(clock),
-	.cout(wire_acc_cella_28cout[0:0]),
-	.dataa(wire_acc_cella_dataa[28:28]),
-	.datab(wire_acc_cella_datab[28:28]),
-	.datac(wire_acc_cella_datac[28:28]),
-	.ena(clken),
-	.regout(wire_acc_cella_regout[28:28]),
-	.sload(sload));
-	defparam
-		acc_cella_28.cin_used = "true",
-		acc_cella_28.lut_mask = "96e8",
-		acc_cella_28.operation_mode = "arithmetic",
-		acc_cella_28.sum_lutc_input = "cin",
-		acc_cella_28.synch_mode = "on",
-		acc_cella_28.lpm_type = "stratix_lcell";
-	stratix_lcell   acc_cella_29
-	( 
-	.aclr(aclr),
-	.cin(wire_acc_cella_28cout[0:0]),
-	.clk(clock),
-	.cout(wire_acc_cella_29cout[0:0]),
-	.dataa(wire_acc_cella_dataa[29:29]),
-	.datab(wire_acc_cella_datab[29:29]),
-	.datac(wire_acc_cella_datac[29:29]),
-	.ena(clken),
-	.regout(wire_acc_cella_regout[29:29]),
-	.sload(sload));
-	defparam
-		acc_cella_29.cin_used = "true",
-		acc_cella_29.lut_mask = "96e8",
-		acc_cella_29.operation_mode = "arithmetic",
-		acc_cella_29.sum_lutc_input = "cin",
-		acc_cella_29.synch_mode = "on",
-		acc_cella_29.lpm_type = "stratix_lcell";
-	stratix_lcell   acc_cella_30
-	( 
-	.aclr(aclr),
-	.cin(wire_acc_cella_29cout[0:0]),
-	.clk(clock),
-	.cout(wire_acc_cella_30cout[0:0]),
-	.dataa(wire_acc_cella_dataa[30:30]),
-	.datab(wire_acc_cella_datab[30:30]),
-	.datac(wire_acc_cella_datac[30:30]),
-	.ena(clken),
-	.regout(wire_acc_cella_regout[30:30]),
-	.sload(sload));
-	defparam
-		acc_cella_30.cin_used = "true",
-		acc_cella_30.lut_mask = "96e8",
-		acc_cella_30.operation_mode = "arithmetic",
-		acc_cella_30.sum_lutc_input = "cin",
-		acc_cella_30.synch_mode = "on",
-		acc_cella_30.lpm_type = "stratix_lcell";
-	stratix_lcell   acc_cella_31
-	( 
-	.aclr(aclr),
-	.cin(wire_acc_cella_30cout[0:0]),
-	.clk(clock),
-	.dataa(wire_acc_cella_dataa[31:31]),
-	.datab(wire_acc_cella_datab[31:31]),
-	.datac(wire_acc_cella_datac[31:31]),
-	.ena(clken),
-	.regout(wire_acc_cella_regout[31:31]),
-	.sload(sload));
-	defparam
-		acc_cella_31.cin_used = "true",
-		acc_cella_31.lut_mask = "9696",
-		acc_cella_31.operation_mode = "normal",
-		acc_cella_31.sum_lutc_input = "cin",
-		acc_cella_31.synch_mode = "on",
-		acc_cella_31.lpm_type = "stratix_lcell";
-	assign
-		wire_acc_cella_dataa = data,
-		wire_acc_cella_datab = wire_acc_cella_regout,
-		wire_acc_cella_datac = data;
-	assign
-		result = wire_acc_cella_regout,
-		sload = 1'b0;
-endmodule //accum32_accum_nta
-//VALID FILE
-
-
-module accum32 (
-	data,
-	clock,
-	clken,
-	aclr,
-	result)/* synthesis synthesis_clearbox = 1 */;
-
-	input	[31:0]  data;
-	input	  clock;
-	input	  clken;
-	input	  aclr;
-	output	[31:0]  result;
-
-	wire [31:0] sub_wire0;
-	wire [31:0] result = sub_wire0[31:0];
-
-	accum32_accum_nta	accum32_accum_nta_component (
-				.clken (clken),
-				.aclr (aclr),
-				.clock (clock),
-				.data (data),
-				.result (sub_wire0));
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: WIDTH_IN NUMERIC "32"
-// Retrieval info: PRIVATE: WIDTH_OUT NUMERIC "32"
-// Retrieval info: PRIVATE: LPM_REPRESENTATION NUMERIC "0"
-// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-// Retrieval info: PRIVATE: ADD_SUB NUMERIC "0"
-// Retrieval info: PRIVATE: CIN NUMERIC "0"
-// Retrieval info: PRIVATE: CLKEN NUMERIC "1"
-// Retrieval info: PRIVATE: ACLR NUMERIC "1"
-// Retrieval info: PRIVATE: COUT NUMERIC "0"
-// Retrieval info: PRIVATE: OVERFLOW NUMERIC "0"
-// Retrieval info: PRIVATE: LATENCY NUMERIC "0"
-// Retrieval info: PRIVATE: EXTRA_LATENCY NUMERIC "0"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: CONSTANT: WIDTH_IN NUMERIC "32"
-// Retrieval info: CONSTANT: WIDTH_OUT NUMERIC "32"
-// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "altaccumulate"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
-// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
-// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT GND clock
-// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
-// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
-// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
-// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
-// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
-// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
diff --git a/fpga/usrp1/megacells/accum32_bb.v b/fpga/usrp1/megacells/accum32_bb.v
deleted file mode 100755
index 142bde88c..000000000
--- a/fpga/usrp1/megacells/accum32_bb.v
+++ /dev/null
@@ -1,35 +0,0 @@
-//Copyright (C) 1991-2003 Altera Corporation
-//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-//support information,  device programming or simulation file,  and any other
-//associated  documentation or information  provided by  Altera  or a partner
-//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-//other  use  of such  megafunction  design,  netlist,  support  information,
-//device programming or simulation file,  or any other  related documentation
-//or information  is prohibited  for  any  other purpose,  including, but not
-//limited to  modification,  reverse engineering,  de-compiling, or use  with
-//any other  silicon devices,  unless such use is  explicitly  licensed under
-//a separate agreement with  Altera  or a megafunction partner.  Title to the
-//intellectual property,  including patents,  copyrights,  trademarks,  trade
-//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-//support  information,  device programming or simulation file,  or any other
-//related documentation or information provided by  Altera  or a megafunction
-//partner, remains with Altera, the megafunction partner, or their respective
-//licensors. No other licenses, including any licenses needed under any third
-//party's intellectual property, are provided herein.
-
-module accum32 (
-	data,
-	clock,
-	clken,
-	aclr,
-	result)/* synthesis synthesis_clearbox = 1 */;
-
-	input	[31:0]  data;
-	input	  clock;
-	input	  clken;
-	input	  aclr;
-	output	[31:0]  result;
-
-endmodule
-
diff --git a/fpga/usrp1/megacells/accum32_inst.v b/fpga/usrp1/megacells/accum32_inst.v
deleted file mode 100755
index c354accae..000000000
--- a/fpga/usrp1/megacells/accum32_inst.v
+++ /dev/null
@@ -1,7 +0,0 @@
-accum32	accum32_inst (
-	.data ( data_sig ),
-	.clock ( clock_sig ),
-	.clken ( clken_sig ),
-	.aclr ( aclr_sig ),
-	.result ( result_sig )
-	);
diff --git a/fpga/usrp1/megacells/add32.bsf b/fpga/usrp1/megacells/add32.bsf
deleted file mode 100755
index b2da9fc2a..000000000
--- a/fpga/usrp1/megacells/add32.bsf
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 1991-2003 Altera Corporation
-Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-support information,  device programming or simulation file,  and any other
-associated  documentation or information  provided by  Altera  or a partner
-under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-other  use  of such  megafunction  design,  netlist,  support  information,
-device programming or simulation file,  or any other  related documentation
-or information  is prohibited  for  any  other purpose,  including, but not
-limited to  modification,  reverse engineering,  de-compiling, or use  with
-any other  silicon devices,  unless such use is  explicitly  licensed under
-a separate agreement with  Altera  or a megafunction partner.  Title to the
-intellectual property,  including patents,  copyrights,  trademarks,  trade
-secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-support  information,  device programming or simulation file,  or any other
-related documentation or information provided by  Altera  or a megafunction
-partner, remains with Altera, the megafunction partner, or their respective
-licensors. No other licenses, including any licenses needed under any third
-party's intellectual property, are provided herein.
-*/
-(header "symbol" (version "1.1"))
-(symbol
-	(rect 0 0 160 96)
-	(text "add32" (rect 58 2 111 21)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 77 31 92)(font "Arial" ))
-	(port
-		(pt 0 40)
-		(input)
-		(text "dataa[7..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "dataa[7..0]" (rect 4 24 66 40)(font "Arial" (font_size 8)))
-		(line (pt 0 40)(pt 64 40)(line_width 3))
-	)
-	(port
-		(pt 0 72)
-		(input)
-		(text "datab[7..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "datab[7..0]" (rect 4 56 66 72)(font "Arial" (font_size 8)))
-		(line (pt 0 72)(pt 64 72)(line_width 3))
-	)
-	(port
-		(pt 160 56)
-		(output)
-		(text "result[7..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "result[7..0]" (rect 95 40 157 56)(font "Arial" (font_size 8)))
-		(line (pt 160 56)(pt 96 56)(line_width 3))
-	)
-	(drawing
-		(text "A" (rect 66 32 75 48)(font "Arial" (font_size 8)))
-		(text "B" (rect 66 64 75 80)(font "Arial" (font_size 8)))
-		(text "A+B" (rect 68 48 94 64)(font "Arial" (font_size 8)))
-		(line (pt 64 32)(pt 96 40)(line_width 1))
-		(line (pt 96 40)(pt 96 72)(line_width 1))
-		(line (pt 96 72)(pt 64 80)(line_width 1))
-		(line (pt 64 80)(pt 64 32)(line_width 1))
-	)
-)
diff --git a/fpga/usrp1/megacells/add32.cmp b/fpga/usrp1/megacells/add32.cmp
deleted file mode 100755
index 3b120176d..000000000
--- a/fpga/usrp1/megacells/add32.cmp
+++ /dev/null
@@ -1,29 +0,0 @@
---Copyright (C) 1991-2003 Altera Corporation
---Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
---support information,  device programming or simulation file,  and any other
---associated  documentation or information  provided by  Altera  or a partner
---under  Altera's   Megafunction   Partnership   Program  may  be  used  only
---to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
---other  use  of such  megafunction  design,  netlist,  support  information,
---device programming or simulation file,  or any other  related documentation
---or information  is prohibited  for  any  other purpose,  including, but not
---limited to  modification,  reverse engineering,  de-compiling, or use  with
---any other  silicon devices,  unless such use is  explicitly  licensed under
---a separate agreement with  Altera  or a megafunction partner.  Title to the
---intellectual property,  including patents,  copyrights,  trademarks,  trade
---secrets,  or maskworks,  embodied in any such megafunction design, netlist,
---support  information,  device programming or simulation file,  or any other
---related documentation or information provided by  Altera  or a megafunction
---partner, remains with Altera, the megafunction partner, or their respective
---licensors. No other licenses, including any licenses needed under any third
---party's intellectual property, are provided herein.
-
-
-component add32
-	PORT
-	(
-		dataa		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-		datab		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-		result		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
-	);
-end component;
diff --git a/fpga/usrp1/megacells/add32.inc b/fpga/usrp1/megacells/add32.inc
deleted file mode 100755
index 675525713..000000000
--- a/fpga/usrp1/megacells/add32.inc
+++ /dev/null
@@ -1,30 +0,0 @@
---Copyright (C) 1991-2003 Altera Corporation
---Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
---support information,  device programming or simulation file,  and any other
---associated  documentation or information  provided by  Altera  or a partner
---under  Altera's   Megafunction   Partnership   Program  may  be  used  only
---to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
---other  use  of such  megafunction  design,  netlist,  support  information,
---device programming or simulation file,  or any other  related documentation
---or information  is prohibited  for  any  other purpose,  including, but not
---limited to  modification,  reverse engineering,  de-compiling, or use  with
---any other  silicon devices,  unless such use is  explicitly  licensed under
---a separate agreement with  Altera  or a megafunction partner.  Title to the
---intellectual property,  including patents,  copyrights,  trademarks,  trade
---secrets,  or maskworks,  embodied in any such megafunction design, netlist,
---support  information,  device programming or simulation file,  or any other
---related documentation or information provided by  Altera  or a megafunction
---partner, remains with Altera, the megafunction partner, or their respective
---licensors. No other licenses, including any licenses needed under any third
---party's intellectual property, are provided herein.
-
-
-FUNCTION add32 
-(
-	dataa[7..0],
-	datab[7..0]
-)
-
-RETURNS (
-	result[7..0]
-);
diff --git a/fpga/usrp1/megacells/add32.v b/fpga/usrp1/megacells/add32.v
deleted file mode 100755
index d8090617a..000000000
--- a/fpga/usrp1/megacells/add32.v
+++ /dev/null
@@ -1,221 +0,0 @@
-// megafunction wizard: %LPM_ADD_SUB%CBX%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: lpm_add_sub 
-
-// ============================================================
-// File Name: add32.v
-// Megafunction Name(s):
-// 			lpm_add_sub
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-// ************************************************************
-
-
-//Copyright (C) 1991-2003 Altera Corporation
-//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-//support information,  device programming or simulation file,  and any other
-//associated  documentation or information  provided by  Altera  or a partner
-//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-//other  use  of such  megafunction  design,  netlist,  support  information,
-//device programming or simulation file,  or any other  related documentation
-//or information  is prohibited  for  any  other purpose,  including, but not
-//limited to  modification,  reverse engineering,  de-compiling, or use  with
-//any other  silicon devices,  unless such use is  explicitly  licensed under
-//a separate agreement with  Altera  or a megafunction partner.  Title to the
-//intellectual property,  including patents,  copyrights,  trademarks,  trade
-//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-//support  information,  device programming or simulation file,  or any other
-//related documentation or information provided by  Altera  or a megafunction
-//partner, remains with Altera, the megafunction partner, or their respective
-//licensors. No other licenses, including any licenses needed under any third
-//party's intellectual property, are provided herein.
-
-
-//lpm_add_sub DEVICE_FAMILY=Cyclone LPM_DIRECTION=ADD LPM_WIDTH=8 dataa datab result
-//VERSION_BEGIN 3.0 cbx_lpm_add_sub 2003:04:10:18:28:42:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ  VERSION_END
-
-//synthesis_resources = lut 8 
-module  add32_add_sub_nq7
-	( 
-	dataa,
-	datab,
-	result) /* synthesis synthesis_clearbox=1 */;
-	input   [7:0]  dataa;
-	input   [7:0]  datab;
-	output   [7:0]  result;
-
-	wire  [7:0]   wire_add_sub_cella_combout;
-	wire  [0:0]   wire_add_sub_cella_0cout;
-	wire  [0:0]   wire_add_sub_cella_1cout;
-	wire  [0:0]   wire_add_sub_cella_2cout;
-	wire  [0:0]   wire_add_sub_cella_3cout;
-	wire  [0:0]   wire_add_sub_cella_4cout;
-	wire  [0:0]   wire_add_sub_cella_5cout;
-	wire  [0:0]   wire_add_sub_cella_6cout;
-	wire  [7:0]   wire_add_sub_cella_dataa;
-	wire  [7:0]   wire_add_sub_cella_datab;
-
-	stratix_lcell   add_sub_cella_0
-	( 
-	.cin(1'b0),
-	.combout(wire_add_sub_cella_combout[0:0]),
-	.cout(wire_add_sub_cella_0cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[0:0]),
-	.datab(wire_add_sub_cella_datab[0:0]));
-	defparam
-		add_sub_cella_0.cin_used = "true",
-		add_sub_cella_0.lut_mask = "96e8",
-		add_sub_cella_0.operation_mode = "arithmetic",
-		add_sub_cella_0.sum_lutc_input = "cin",
-		add_sub_cella_0.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_1
-	( 
-	.cin(wire_add_sub_cella_0cout[0:0]),
-	.combout(wire_add_sub_cella_combout[1:1]),
-	.cout(wire_add_sub_cella_1cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[1:1]),
-	.datab(wire_add_sub_cella_datab[1:1]));
-	defparam
-		add_sub_cella_1.cin_used = "true",
-		add_sub_cella_1.lut_mask = "96e8",
-		add_sub_cella_1.operation_mode = "arithmetic",
-		add_sub_cella_1.sum_lutc_input = "cin",
-		add_sub_cella_1.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_2
-	( 
-	.cin(wire_add_sub_cella_1cout[0:0]),
-	.combout(wire_add_sub_cella_combout[2:2]),
-	.cout(wire_add_sub_cella_2cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[2:2]),
-	.datab(wire_add_sub_cella_datab[2:2]));
-	defparam
-		add_sub_cella_2.cin_used = "true",
-		add_sub_cella_2.lut_mask = "96e8",
-		add_sub_cella_2.operation_mode = "arithmetic",
-		add_sub_cella_2.sum_lutc_input = "cin",
-		add_sub_cella_2.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_3
-	( 
-	.cin(wire_add_sub_cella_2cout[0:0]),
-	.combout(wire_add_sub_cella_combout[3:3]),
-	.cout(wire_add_sub_cella_3cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[3:3]),
-	.datab(wire_add_sub_cella_datab[3:3]));
-	defparam
-		add_sub_cella_3.cin_used = "true",
-		add_sub_cella_3.lut_mask = "96e8",
-		add_sub_cella_3.operation_mode = "arithmetic",
-		add_sub_cella_3.sum_lutc_input = "cin",
-		add_sub_cella_3.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_4
-	( 
-	.cin(wire_add_sub_cella_3cout[0:0]),
-	.combout(wire_add_sub_cella_combout[4:4]),
-	.cout(wire_add_sub_cella_4cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[4:4]),
-	.datab(wire_add_sub_cella_datab[4:4]));
-	defparam
-		add_sub_cella_4.cin_used = "true",
-		add_sub_cella_4.lut_mask = "96e8",
-		add_sub_cella_4.operation_mode = "arithmetic",
-		add_sub_cella_4.sum_lutc_input = "cin",
-		add_sub_cella_4.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_5
-	( 
-	.cin(wire_add_sub_cella_4cout[0:0]),
-	.combout(wire_add_sub_cella_combout[5:5]),
-	.cout(wire_add_sub_cella_5cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[5:5]),
-	.datab(wire_add_sub_cella_datab[5:5]));
-	defparam
-		add_sub_cella_5.cin_used = "true",
-		add_sub_cella_5.lut_mask = "96e8",
-		add_sub_cella_5.operation_mode = "arithmetic",
-		add_sub_cella_5.sum_lutc_input = "cin",
-		add_sub_cella_5.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_6
-	( 
-	.cin(wire_add_sub_cella_5cout[0:0]),
-	.combout(wire_add_sub_cella_combout[6:6]),
-	.cout(wire_add_sub_cella_6cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[6:6]),
-	.datab(wire_add_sub_cella_datab[6:6]));
-	defparam
-		add_sub_cella_6.cin_used = "true",
-		add_sub_cella_6.lut_mask = "96e8",
-		add_sub_cella_6.operation_mode = "arithmetic",
-		add_sub_cella_6.sum_lutc_input = "cin",
-		add_sub_cella_6.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_7
-	( 
-	.cin(wire_add_sub_cella_6cout[0:0]),
-	.combout(wire_add_sub_cella_combout[7:7]),
-	.dataa(wire_add_sub_cella_dataa[7:7]),
-	.datab(wire_add_sub_cella_datab[7:7]));
-	defparam
-		add_sub_cella_7.cin_used = "true",
-		add_sub_cella_7.lut_mask = "9696",
-		add_sub_cella_7.operation_mode = "normal",
-		add_sub_cella_7.sum_lutc_input = "cin",
-		add_sub_cella_7.lpm_type = "stratix_lcell";
-	assign
-		wire_add_sub_cella_dataa = dataa,
-		wire_add_sub_cella_datab = datab;
-	assign
-		result = wire_add_sub_cella_combout;
-endmodule //add32_add_sub_nq7
-//VALID FILE
-
-
-module add32 (
-	dataa,
-	datab,
-	result)/* synthesis synthesis_clearbox = 1 */;
-
-	input	[7:0]  dataa;
-	input	[7:0]  datab;
-	output	[7:0]  result;
-
-	wire [7:0] sub_wire0;
-	wire [7:0] result = sub_wire0[7:0];
-
-	add32_add_sub_nq7	add32_add_sub_nq7_component (
-				.dataa (dataa),
-				.datab (datab),
-				.result (sub_wire0));
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: nBit NUMERIC "8"
-// Retrieval info: PRIVATE: Function NUMERIC "0"
-// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
-// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
-// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
-// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
-// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
-// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-// Retrieval info: PRIVATE: Overflow NUMERIC "0"
-// Retrieval info: PRIVATE: Latency NUMERIC "0"
-// Retrieval info: PRIVATE: aclr NUMERIC "0"
-// Retrieval info: PRIVATE: clken NUMERIC "0"
-// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-// Retrieval info: CONSTANT: LPM_DIRECTION STRING "ADD"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
-// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL result[7..0]
-// Retrieval info: USED_PORT: dataa 0 0 8 0 INPUT NODEFVAL dataa[7..0]
-// Retrieval info: USED_PORT: datab 0 0 8 0 INPUT NODEFVAL datab[7..0]
-// Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
-// Retrieval info: CONNECT: @dataa 0 0 8 0 dataa 0 0 8 0
-// Retrieval info: CONNECT: @datab 0 0 8 0 datab 0 0 8 0
-// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
diff --git a/fpga/usrp1/megacells/add32_bb.v b/fpga/usrp1/megacells/add32_bb.v
deleted file mode 100755
index 8d1588cc6..000000000
--- a/fpga/usrp1/megacells/add32_bb.v
+++ /dev/null
@@ -1,31 +0,0 @@
-//Copyright (C) 1991-2003 Altera Corporation
-//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-//support information,  device programming or simulation file,  and any other
-//associated  documentation or information  provided by  Altera  or a partner
-//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-//other  use  of such  megafunction  design,  netlist,  support  information,
-//device programming or simulation file,  or any other  related documentation
-//or information  is prohibited  for  any  other purpose,  including, but not
-//limited to  modification,  reverse engineering,  de-compiling, or use  with
-//any other  silicon devices,  unless such use is  explicitly  licensed under
-//a separate agreement with  Altera  or a megafunction partner.  Title to the
-//intellectual property,  including patents,  copyrights,  trademarks,  trade
-//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-//support  information,  device programming or simulation file,  or any other
-//related documentation or information provided by  Altera  or a megafunction
-//partner, remains with Altera, the megafunction partner, or their respective
-//licensors. No other licenses, including any licenses needed under any third
-//party's intellectual property, are provided herein.
-
-module add32 (
-	dataa,
-	datab,
-	result)/* synthesis synthesis_clearbox = 1 */;
-
-	input	[7:0]  dataa;
-	input	[7:0]  datab;
-	output	[7:0]  result;
-
-endmodule
-
diff --git a/fpga/usrp1/megacells/add32_inst.v b/fpga/usrp1/megacells/add32_inst.v
deleted file mode 100755
index bc7e6d441..000000000
--- a/fpga/usrp1/megacells/add32_inst.v
+++ /dev/null
@@ -1,5 +0,0 @@
-add32	add32_inst (
-	.dataa ( dataa_sig ),
-	.datab ( datab_sig ),
-	.result ( result_sig )
-	);
diff --git a/fpga/usrp1/megacells/addsub16.bsf b/fpga/usrp1/megacells/addsub16.bsf
deleted file mode 100755
index 9ed6b72ae..000000000
--- a/fpga/usrp1/megacells/addsub16.bsf
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 1991-2003 Altera Corporation
-Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-support information,  device programming or simulation file,  and any other
-associated  documentation or information  provided by  Altera  or a partner
-under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-other  use  of such  megafunction  design,  netlist,  support  information,
-device programming or simulation file,  or any other  related documentation
-or information  is prohibited  for  any  other purpose,  including, but not
-limited to  modification,  reverse engineering,  de-compiling, or use  with
-any other  silicon devices,  unless such use is  explicitly  licensed under
-a separate agreement with  Altera  or a megafunction partner.  Title to the
-intellectual property,  including patents,  copyrights,  trademarks,  trade
-secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-support  information,  device programming or simulation file,  or any other
-related documentation or information provided by  Altera  or a megafunction
-partner, remains with Altera, the megafunction partner, or their respective
-licensors. No other licenses, including any licenses needed under any third
-party's intellectual property, are provided herein.
-*/
-(header "symbol" (version "1.1"))
-(symbol
-	(rect 0 0 160 144)
-	(text "addsub16" (rect 45 2 128 21)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 125 31 140)(font "Arial" ))
-	(port
-		(pt 0 56)
-		(input)
-		(text "dataa[15..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "dataa[15..0]" (rect 4 40 73 56)(font "Arial" (font_size 8)))
-		(line (pt 0 56)(pt 64 56)(line_width 3))
-	)
-	(port
-		(pt 0 88)
-		(input)
-		(text "datab[15..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "datab[15..0]" (rect 4 72 73 88)(font "Arial" (font_size 8)))
-		(line (pt 0 88)(pt 64 88)(line_width 3))
-	)
-	(port
-		(pt 0 72)
-		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 4 56 35 72)(font "Arial" (font_size 8)))
-		(line (pt 0 72)(pt 64 72)(line_width 1))
-	)
-	(port
-		(pt 0 32)
-		(input)
-		(text "add_sub" (rect 0 0 57 16)(font "Arial" (font_size 8)))
-		(text "add_sub" (rect 4 16 53 32)(font "Arial" (font_size 8)))
-		(line (pt 0 32)(pt 80 32)(line_width 1))
-	)
-	(port
-		(pt 0 112)
-		(input)
-		(text "clken" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clken" (rect 4 96 35 112)(font "Arial" (font_size 8)))
-		(line (pt 0 112)(pt 74 112)(line_width 1))
-	)
-	(port
-		(pt 0 128)
-		(input)
-		(text "aclr" (rect 0 0 24 16)(font "Arial" (font_size 8)))
-		(text "aclr" (rect 4 112 25 128)(font "Arial" (font_size 8)))
-		(line (pt 0 128)(pt 85 128)(line_width 1))
-	)
-	(port
-		(pt 160 72)
-		(output)
-		(text "result[15..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "result[15..0]" (rect 88 56 157 72)(font "Arial" (font_size 8)))
-		(line (pt 160 72)(pt 96 72)(line_width 3))
-	)
-	(drawing
-		(text "A" (rect 66 48 75 64)(font "Arial" (font_size 8)))
-		(text "B" (rect 66 80 75 96)(font "Arial" (font_size 8)))
-		(text "A+B/A-B" (rect 82 37 134 53)(font "Arial" (font_size 8)))
-		(line (pt 64 48)(pt 96 56)(line_width 1))
-		(line (pt 96 56)(pt 96 88)(line_width 1))
-		(line (pt 96 88)(pt 64 96)(line_width 1))
-		(line (pt 64 96)(pt 64 48)(line_width 1))
-		(line (pt 80 32)(pt 80 52)(line_width 1))
-		(line (pt 106 40)(pt 125 40)(line_width 1))
-		(line (pt 74 112)(pt 74 93)(line_width 1))
-		(line (pt 85 128)(pt 85 90)(line_width 1))
-		(line (pt 64 66)(pt 70 72)(line_width 1))
-		(line (pt 70 72)(pt 64 78)(line_width 1))
-	)
-)
diff --git a/fpga/usrp1/megacells/addsub16.cmp b/fpga/usrp1/megacells/addsub16.cmp
deleted file mode 100755
index e32e01b31..000000000
--- a/fpga/usrp1/megacells/addsub16.cmp
+++ /dev/null
@@ -1,33 +0,0 @@
---Copyright (C) 1991-2003 Altera Corporation
---Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
---support information,  device programming or simulation file,  and any other
---associated  documentation or information  provided by  Altera  or a partner
---under  Altera's   Megafunction   Partnership   Program  may  be  used  only
---to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
---other  use  of such  megafunction  design,  netlist,  support  information,
---device programming or simulation file,  or any other  related documentation
---or information  is prohibited  for  any  other purpose,  including, but not
---limited to  modification,  reverse engineering,  de-compiling, or use  with
---any other  silicon devices,  unless such use is  explicitly  licensed under
---a separate agreement with  Altera  or a megafunction partner.  Title to the
---intellectual property,  including patents,  copyrights,  trademarks,  trade
---secrets,  or maskworks,  embodied in any such megafunction design, netlist,
---support  information,  device programming or simulation file,  or any other
---related documentation or information provided by  Altera  or a megafunction
---partner, remains with Altera, the megafunction partner, or their respective
---licensors. No other licenses, including any licenses needed under any third
---party's intellectual property, are provided herein.
-
-
-component addsub16
-	PORT
-	(
-		add_sub		: IN STD_LOGIC ;
-		dataa		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-		datab		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-		clock		: IN STD_LOGIC ;
-		aclr		: IN STD_LOGIC ;
-		clken		: IN STD_LOGIC ;
-		result		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
-	);
-end component;
diff --git a/fpga/usrp1/megacells/addsub16.inc b/fpga/usrp1/megacells/addsub16.inc
deleted file mode 100755
index 846f301d2..000000000
--- a/fpga/usrp1/megacells/addsub16.inc
+++ /dev/null
@@ -1,34 +0,0 @@
---Copyright (C) 1991-2003 Altera Corporation
---Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
---support information,  device programming or simulation file,  and any other
---associated  documentation or information  provided by  Altera  or a partner
---under  Altera's   Megafunction   Partnership   Program  may  be  used  only
---to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
---other  use  of such  megafunction  design,  netlist,  support  information,
---device programming or simulation file,  or any other  related documentation
---or information  is prohibited  for  any  other purpose,  including, but not
---limited to  modification,  reverse engineering,  de-compiling, or use  with
---any other  silicon devices,  unless such use is  explicitly  licensed under
---a separate agreement with  Altera  or a megafunction partner.  Title to the
---intellectual property,  including patents,  copyrights,  trademarks,  trade
---secrets,  or maskworks,  embodied in any such megafunction design, netlist,
---support  information,  device programming or simulation file,  or any other
---related documentation or information provided by  Altera  or a megafunction
---partner, remains with Altera, the megafunction partner, or their respective
---licensors. No other licenses, including any licenses needed under any third
---party's intellectual property, are provided herein.
-
-
-FUNCTION addsub16 
-(
-	add_sub,
-	dataa[15..0],
-	datab[15..0],
-	clock,
-	aclr,
-	clken
-)
-
-RETURNS (
-	result[15..0]
-);
diff --git a/fpga/usrp1/megacells/addsub16.v b/fpga/usrp1/megacells/addsub16.v
deleted file mode 100755
index 431af3e43..000000000
--- a/fpga/usrp1/megacells/addsub16.v
+++ /dev/null
@@ -1,438 +0,0 @@
-// megafunction wizard: %LPM_ADD_SUB%CBX%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: lpm_add_sub 
-
-// ============================================================
-// File Name: addsub16.v
-// Megafunction Name(s):
-// 			lpm_add_sub
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-// ************************************************************
-
-
-//Copyright (C) 1991-2003 Altera Corporation
-//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-//support information,  device programming or simulation file,  and any other
-//associated  documentation or information  provided by  Altera  or a partner
-//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-//other  use  of such  megafunction  design,  netlist,  support  information,
-//device programming or simulation file,  or any other  related documentation
-//or information  is prohibited  for  any  other purpose,  including, but not
-//limited to  modification,  reverse engineering,  de-compiling, or use  with
-//any other  silicon devices,  unless such use is  explicitly  licensed under
-//a separate agreement with  Altera  or a megafunction partner.  Title to the
-//intellectual property,  including patents,  copyrights,  trademarks,  trade
-//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-//support  information,  device programming or simulation file,  or any other
-//related documentation or information provided by  Altera  or a megafunction
-//partner, remains with Altera, the megafunction partner, or their respective
-//licensors. No other licenses, including any licenses needed under any third
-//party's intellectual property, are provided herein.
-
-
-//lpm_add_sub DEVICE_FAMILY=Cyclone LPM_PIPELINE=1 LPM_WIDTH=16 aclr add_sub clken clock dataa datab result
-//VERSION_BEGIN 3.0 cbx_lpm_add_sub 2003:04:10:18:28:42:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ  VERSION_END
-
-//synthesis_resources = lut 17 
-module  addsub16_add_sub_gp9
-	( 
-	aclr,
-	add_sub,
-	clken,
-	clock,
-	dataa,
-	datab,
-	result) /* synthesis synthesis_clearbox=1 */;
-	input   aclr;
-	input   add_sub;
-	input   clken;
-	input   clock;
-	input   [15:0]  dataa;
-	input   [15:0]  datab;
-	output   [15:0]  result;
-
-	wire  [0:0]   wire_add_sub_cella_0cout;
-	wire  [0:0]   wire_add_sub_cella_1cout;
-	wire  [0:0]   wire_add_sub_cella_2cout;
-	wire  [0:0]   wire_add_sub_cella_3cout;
-	wire  [0:0]   wire_add_sub_cella_4cout;
-	wire  [0:0]   wire_add_sub_cella_5cout;
-	wire  [0:0]   wire_add_sub_cella_6cout;
-	wire  [0:0]   wire_add_sub_cella_7cout;
-	wire  [0:0]   wire_add_sub_cella_8cout;
-	wire  [0:0]   wire_add_sub_cella_9cout;
-	wire  [0:0]   wire_add_sub_cella_10cout;
-	wire  [0:0]   wire_add_sub_cella_11cout;
-	wire  [0:0]   wire_add_sub_cella_12cout;
-	wire  [0:0]   wire_add_sub_cella_13cout;
-	wire  [0:0]   wire_add_sub_cella_14cout;
-	wire  [15:0]   wire_add_sub_cella_dataa;
-	wire  [15:0]   wire_add_sub_cella_datab;
-	wire  [15:0]   wire_add_sub_cella_regout;
-	wire  wire_strx_lcell1_cout;
-
-	stratix_lcell   add_sub_cella_0
-	( 
-	.aclr(aclr),
-	.cin(wire_strx_lcell1_cout),
-	.clk(clock),
-	.cout(wire_add_sub_cella_0cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[0:0]),
-	.datab(wire_add_sub_cella_datab[0:0]),
-	.ena(clken),
-	.inverta((~ add_sub)),
-	.regout(wire_add_sub_cella_regout[0:0]));
-	defparam
-		add_sub_cella_0.cin_used = "true",
-		add_sub_cella_0.lut_mask = "96e8",
-		add_sub_cella_0.operation_mode = "arithmetic",
-		add_sub_cella_0.sum_lutc_input = "cin",
-		add_sub_cella_0.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_1
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_0cout[0:0]),
-	.clk(clock),
-	.cout(wire_add_sub_cella_1cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[1:1]),
-	.datab(wire_add_sub_cella_datab[1:1]),
-	.ena(clken),
-	.inverta((~ add_sub)),
-	.regout(wire_add_sub_cella_regout[1:1]));
-	defparam
-		add_sub_cella_1.cin_used = "true",
-		add_sub_cella_1.lut_mask = "96e8",
-		add_sub_cella_1.operation_mode = "arithmetic",
-		add_sub_cella_1.sum_lutc_input = "cin",
-		add_sub_cella_1.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_2
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_1cout[0:0]),
-	.clk(clock),
-	.cout(wire_add_sub_cella_2cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[2:2]),
-	.datab(wire_add_sub_cella_datab[2:2]),
-	.ena(clken),
-	.inverta((~ add_sub)),
-	.regout(wire_add_sub_cella_regout[2:2]));
-	defparam
-		add_sub_cella_2.cin_used = "true",
-		add_sub_cella_2.lut_mask = "96e8",
-		add_sub_cella_2.operation_mode = "arithmetic",
-		add_sub_cella_2.sum_lutc_input = "cin",
-		add_sub_cella_2.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_3
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_2cout[0:0]),
-	.clk(clock),
-	.cout(wire_add_sub_cella_3cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[3:3]),
-	.datab(wire_add_sub_cella_datab[3:3]),
-	.ena(clken),
-	.inverta((~ add_sub)),
-	.regout(wire_add_sub_cella_regout[3:3]));
-	defparam
-		add_sub_cella_3.cin_used = "true",
-		add_sub_cella_3.lut_mask = "96e8",
-		add_sub_cella_3.operation_mode = "arithmetic",
-		add_sub_cella_3.sum_lutc_input = "cin",
-		add_sub_cella_3.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_4
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_3cout[0:0]),
-	.clk(clock),
-	.cout(wire_add_sub_cella_4cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[4:4]),
-	.datab(wire_add_sub_cella_datab[4:4]),
-	.ena(clken),
-	.inverta((~ add_sub)),
-	.regout(wire_add_sub_cella_regout[4:4]));
-	defparam
-		add_sub_cella_4.cin_used = "true",
-		add_sub_cella_4.lut_mask = "96e8",
-		add_sub_cella_4.operation_mode = "arithmetic",
-		add_sub_cella_4.sum_lutc_input = "cin",
-		add_sub_cella_4.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_5
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_4cout[0:0]),
-	.clk(clock),
-	.cout(wire_add_sub_cella_5cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[5:5]),
-	.datab(wire_add_sub_cella_datab[5:5]),
-	.ena(clken),
-	.inverta((~ add_sub)),
-	.regout(wire_add_sub_cella_regout[5:5]));
-	defparam
-		add_sub_cella_5.cin_used = "true",
-		add_sub_cella_5.lut_mask = "96e8",
-		add_sub_cella_5.operation_mode = "arithmetic",
-		add_sub_cella_5.sum_lutc_input = "cin",
-		add_sub_cella_5.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_6
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_5cout[0:0]),
-	.clk(clock),
-	.cout(wire_add_sub_cella_6cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[6:6]),
-	.datab(wire_add_sub_cella_datab[6:6]),
-	.ena(clken),
-	.inverta((~ add_sub)),
-	.regout(wire_add_sub_cella_regout[6:6]));
-	defparam
-		add_sub_cella_6.cin_used = "true",
-		add_sub_cella_6.lut_mask = "96e8",
-		add_sub_cella_6.operation_mode = "arithmetic",
-		add_sub_cella_6.sum_lutc_input = "cin",
-		add_sub_cella_6.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_7
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_6cout[0:0]),
-	.clk(clock),
-	.cout(wire_add_sub_cella_7cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[7:7]),
-	.datab(wire_add_sub_cella_datab[7:7]),
-	.ena(clken),
-	.inverta((~ add_sub)),
-	.regout(wire_add_sub_cella_regout[7:7]));
-	defparam
-		add_sub_cella_7.cin_used = "true",
-		add_sub_cella_7.lut_mask = "96e8",
-		add_sub_cella_7.operation_mode = "arithmetic",
-		add_sub_cella_7.sum_lutc_input = "cin",
-		add_sub_cella_7.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_8
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_7cout[0:0]),
-	.clk(clock),
-	.cout(wire_add_sub_cella_8cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[8:8]),
-	.datab(wire_add_sub_cella_datab[8:8]),
-	.ena(clken),
-	.inverta((~ add_sub)),
-	.regout(wire_add_sub_cella_regout[8:8]));
-	defparam
-		add_sub_cella_8.cin_used = "true",
-		add_sub_cella_8.lut_mask = "96e8",
-		add_sub_cella_8.operation_mode = "arithmetic",
-		add_sub_cella_8.sum_lutc_input = "cin",
-		add_sub_cella_8.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_9
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_8cout[0:0]),
-	.clk(clock),
-	.cout(wire_add_sub_cella_9cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[9:9]),
-	.datab(wire_add_sub_cella_datab[9:9]),
-	.ena(clken),
-	.inverta((~ add_sub)),
-	.regout(wire_add_sub_cella_regout[9:9]));
-	defparam
-		add_sub_cella_9.cin_used = "true",
-		add_sub_cella_9.lut_mask = "96e8",
-		add_sub_cella_9.operation_mode = "arithmetic",
-		add_sub_cella_9.sum_lutc_input = "cin",
-		add_sub_cella_9.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_10
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_9cout[0:0]),
-	.clk(clock),
-	.cout(wire_add_sub_cella_10cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[10:10]),
-	.datab(wire_add_sub_cella_datab[10:10]),
-	.ena(clken),
-	.inverta((~ add_sub)),
-	.regout(wire_add_sub_cella_regout[10:10]));
-	defparam
-		add_sub_cella_10.cin_used = "true",
-		add_sub_cella_10.lut_mask = "96e8",
-		add_sub_cella_10.operation_mode = "arithmetic",
-		add_sub_cella_10.sum_lutc_input = "cin",
-		add_sub_cella_10.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_11
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_10cout[0:0]),
-	.clk(clock),
-	.cout(wire_add_sub_cella_11cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[11:11]),
-	.datab(wire_add_sub_cella_datab[11:11]),
-	.ena(clken),
-	.inverta((~ add_sub)),
-	.regout(wire_add_sub_cella_regout[11:11]));
-	defparam
-		add_sub_cella_11.cin_used = "true",
-		add_sub_cella_11.lut_mask = "96e8",
-		add_sub_cella_11.operation_mode = "arithmetic",
-		add_sub_cella_11.sum_lutc_input = "cin",
-		add_sub_cella_11.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_12
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_11cout[0:0]),
-	.clk(clock),
-	.cout(wire_add_sub_cella_12cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[12:12]),
-	.datab(wire_add_sub_cella_datab[12:12]),
-	.ena(clken),
-	.inverta((~ add_sub)),
-	.regout(wire_add_sub_cella_regout[12:12]));
-	defparam
-		add_sub_cella_12.cin_used = "true",
-		add_sub_cella_12.lut_mask = "96e8",
-		add_sub_cella_12.operation_mode = "arithmetic",
-		add_sub_cella_12.sum_lutc_input = "cin",
-		add_sub_cella_12.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_13
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_12cout[0:0]),
-	.clk(clock),
-	.cout(wire_add_sub_cella_13cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[13:13]),
-	.datab(wire_add_sub_cella_datab[13:13]),
-	.ena(clken),
-	.inverta((~ add_sub)),
-	.regout(wire_add_sub_cella_regout[13:13]));
-	defparam
-		add_sub_cella_13.cin_used = "true",
-		add_sub_cella_13.lut_mask = "96e8",
-		add_sub_cella_13.operation_mode = "arithmetic",
-		add_sub_cella_13.sum_lutc_input = "cin",
-		add_sub_cella_13.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_14
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_13cout[0:0]),
-	.clk(clock),
-	.cout(wire_add_sub_cella_14cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[14:14]),
-	.datab(wire_add_sub_cella_datab[14:14]),
-	.ena(clken),
-	.inverta((~ add_sub)),
-	.regout(wire_add_sub_cella_regout[14:14]));
-	defparam
-		add_sub_cella_14.cin_used = "true",
-		add_sub_cella_14.lut_mask = "96e8",
-		add_sub_cella_14.operation_mode = "arithmetic",
-		add_sub_cella_14.sum_lutc_input = "cin",
-		add_sub_cella_14.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_15
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_14cout[0:0]),
-	.clk(clock),
-	.dataa(wire_add_sub_cella_dataa[15:15]),
-	.datab(wire_add_sub_cella_datab[15:15]),
-	.ena(clken),
-	.inverta((~ add_sub)),
-	.regout(wire_add_sub_cella_regout[15:15]));
-	defparam
-		add_sub_cella_15.cin_used = "true",
-		add_sub_cella_15.lut_mask = "9696",
-		add_sub_cella_15.operation_mode = "normal",
-		add_sub_cella_15.sum_lutc_input = "cin",
-		add_sub_cella_15.lpm_type = "stratix_lcell";
-	assign
-		wire_add_sub_cella_dataa = datab,
-		wire_add_sub_cella_datab = dataa;
-	stratix_lcell   strx_lcell1
-	( 
-	.cout(wire_strx_lcell1_cout),
-	.dataa(1'b0),
-	.datab((~ add_sub)),
-	.inverta((~ add_sub)));
-	defparam
-		strx_lcell1.cin_used = "false",
-		strx_lcell1.lut_mask = "00cc",
-		strx_lcell1.operation_mode = "arithmetic",
-		strx_lcell1.lpm_type = "stratix_lcell";
-	assign
-		result = wire_add_sub_cella_regout;
-endmodule //addsub16_add_sub_gp9
-//VALID FILE
-
-
-module addsub16 (
-	add_sub,
-	dataa,
-	datab,
-	clock,
-	aclr,
-	clken,
-	result)/* synthesis synthesis_clearbox = 1 */;
-
-	input	  add_sub;
-	input	[15:0]  dataa;
-	input	[15:0]  datab;
-	input	  clock;
-	input	  aclr;
-	input	  clken;
-	output	[15:0]  result;
-
-	wire [15:0] sub_wire0;
-	wire [15:0] result = sub_wire0[15:0];
-
-	addsub16_add_sub_gp9	addsub16_add_sub_gp9_component (
-				.dataa (dataa),
-				.add_sub (add_sub),
-				.datab (datab),
-				.clken (clken),
-				.aclr (aclr),
-				.clock (clock),
-				.result (sub_wire0));
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: nBit NUMERIC "16"
-// Retrieval info: PRIVATE: Function NUMERIC "2"
-// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
-// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
-// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
-// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
-// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
-// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-// Retrieval info: PRIVATE: Overflow NUMERIC "0"
-// Retrieval info: PRIVATE: Latency NUMERIC "1"
-// Retrieval info: PRIVATE: aclr NUMERIC "1"
-// Retrieval info: PRIVATE: clken NUMERIC "1"
-// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
-// Retrieval info: CONSTANT: LPM_DIRECTION STRING "UNUSED"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
-// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO"
-// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: USED_PORT: add_sub 0 0 0 0 INPUT NODEFVAL add_sub
-// Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL result[15..0]
-// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL dataa[15..0]
-// Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL datab[15..0]
-// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
-// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL clken
-// Retrieval info: CONNECT: @add_sub 0 0 0 0 add_sub 0 0 0 0
-// Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
-// Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0
-// Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0
-// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
-// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
diff --git a/fpga/usrp1/megacells/addsub16_bb.v b/fpga/usrp1/megacells/addsub16_bb.v
deleted file mode 100755
index 8e1e7c69f..000000000
--- a/fpga/usrp1/megacells/addsub16_bb.v
+++ /dev/null
@@ -1,39 +0,0 @@
-//Copyright (C) 1991-2003 Altera Corporation
-//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-//support information,  device programming or simulation file,  and any other
-//associated  documentation or information  provided by  Altera  or a partner
-//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-//other  use  of such  megafunction  design,  netlist,  support  information,
-//device programming or simulation file,  or any other  related documentation
-//or information  is prohibited  for  any  other purpose,  including, but not
-//limited to  modification,  reverse engineering,  de-compiling, or use  with
-//any other  silicon devices,  unless such use is  explicitly  licensed under
-//a separate agreement with  Altera  or a megafunction partner.  Title to the
-//intellectual property,  including patents,  copyrights,  trademarks,  trade
-//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-//support  information,  device programming or simulation file,  or any other
-//related documentation or information provided by  Altera  or a megafunction
-//partner, remains with Altera, the megafunction partner, or their respective
-//licensors. No other licenses, including any licenses needed under any third
-//party's intellectual property, are provided herein.
-
-module addsub16 (
-	add_sub,
-	dataa,
-	datab,
-	clock,
-	aclr,
-	clken,
-	result)/* synthesis synthesis_clearbox = 1 */;
-
-	input	  add_sub;
-	input	[15:0]  dataa;
-	input	[15:0]  datab;
-	input	  clock;
-	input	  aclr;
-	input	  clken;
-	output	[15:0]  result;
-
-endmodule
-
diff --git a/fpga/usrp1/megacells/addsub16_inst.v b/fpga/usrp1/megacells/addsub16_inst.v
deleted file mode 100755
index 4a81ff2ee..000000000
--- a/fpga/usrp1/megacells/addsub16_inst.v
+++ /dev/null
@@ -1,9 +0,0 @@
-addsub16	addsub16_inst (
-	.add_sub ( add_sub_sig ),
-	.dataa ( dataa_sig ),
-	.datab ( datab_sig ),
-	.clock ( clock_sig ),
-	.aclr ( aclr_sig ),
-	.clken ( clken_sig ),
-	.result ( result_sig )
-	);
diff --git a/fpga/usrp1/megacells/bustri.bsf b/fpga/usrp1/megacells/bustri.bsf
deleted file mode 100755
index f1bc3ca7f..000000000
--- a/fpga/usrp1/megacells/bustri.bsf
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 1991-2003 Altera Corporation
-Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-support information,  device programming or simulation file,  and any other
-associated  documentation or information  provided by  Altera  or a partner
-under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-other  use  of such  megafunction  design,  netlist,  support  information,
-device programming or simulation file,  or any other  related documentation
-or information  is prohibited  for  any  other purpose,  including, but not
-limited to  modification,  reverse engineering,  de-compiling, or use  with
-any other  silicon devices,  unless such use is  explicitly  licensed under
-a separate agreement with  Altera  or a megafunction partner.  Title to the
-intellectual property,  including patents,  copyrights,  trademarks,  trade
-secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-support  information,  device programming or simulation file,  or any other
-related documentation or information provided by  Altera  or a megafunction
-partner, remains with Altera, the megafunction partner, or their respective
-licensors. No other licenses, including any licenses needed under any third
-party's intellectual property, are provided herein.
-*/
-(header "symbol" (version "1.1"))
-(symbol
-	(rect 0 0 80 40)
-	(text "bustri" (rect 24 1 61 17)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 24 25 36)(font "Arial" ))
-	(port
-		(pt 40 40)
-		(input)
-		(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
-		(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
-		(line (pt 40 40)(pt 40 28)(line_width 1))
-	)
-	(port
-		(pt 0 24)
-		(input)
-		(text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
-		(text "data[15..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible))
-		(line (pt 0 24)(pt 32 24)(line_width 3))
-	)
-	(port
-		(pt 80 24)
-		(bidir)
-		(text "tridata[15..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
-		(text "tridata[15..0]" (rect 84 -36 97 24)(font "Arial" (font_size 8))(invisible))
-		(line (pt 80 24)(pt 48 24)(line_width 3))
-	)
-	(drawing
-		(text "16" (rect 61 25 71 37)(font "Arial" ))
-		(text "16" (rect 13 25 23 37)(font "Arial" ))
-		(line (pt 32 16)(pt 48 24)(line_width 1))
-		(line (pt 48 24)(pt 32 32)(line_width 1))
-		(line (pt 32 32)(pt 32 16)(line_width 1))
-		(line (pt 56 28)(pt 64 20)(line_width 1))
-		(line (pt 8 28)(pt 16 20)(line_width 1))
-	)
-)
diff --git a/fpga/usrp1/megacells/bustri.cmp b/fpga/usrp1/megacells/bustri.cmp
deleted file mode 100755
index 87599ca66..000000000
--- a/fpga/usrp1/megacells/bustri.cmp
+++ /dev/null
@@ -1,29 +0,0 @@
---Copyright (C) 1991-2003 Altera Corporation
---Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
---support information,  device programming or simulation file,  and any other
---associated  documentation or information  provided by  Altera  or a partner
---under  Altera's   Megafunction   Partnership   Program  may  be  used  only
---to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
---other  use  of such  megafunction  design,  netlist,  support  information,
---device programming or simulation file,  or any other  related documentation
---or information  is prohibited  for  any  other purpose,  including, but not
---limited to  modification,  reverse engineering,  de-compiling, or use  with
---any other  silicon devices,  unless such use is  explicitly  licensed under
---a separate agreement with  Altera  or a megafunction partner.  Title to the
---intellectual property,  including patents,  copyrights,  trademarks,  trade
---secrets,  or maskworks,  embodied in any such megafunction design, netlist,
---support  information,  device programming or simulation file,  or any other
---related documentation or information provided by  Altera  or a megafunction
---partner, remains with Altera, the megafunction partner, or their respective
---licensors. No other licenses, including any licenses needed under any third
---party's intellectual property, are provided herein.
-
-
-component bustri
-	PORT
-	(
-		data		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-		enabledt		: IN STD_LOGIC ;
-		tridata		: INOUT STD_LOGIC_VECTOR (15 DOWNTO 0)
-	);
-end component;
diff --git a/fpga/usrp1/megacells/bustri.inc b/fpga/usrp1/megacells/bustri.inc
deleted file mode 100755
index 399950389..000000000
--- a/fpga/usrp1/megacells/bustri.inc
+++ /dev/null
@@ -1,30 +0,0 @@
---Copyright (C) 1991-2003 Altera Corporation
---Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
---support information,  device programming or simulation file,  and any other
---associated  documentation or information  provided by  Altera  or a partner
---under  Altera's   Megafunction   Partnership   Program  may  be  used  only
---to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
---other  use  of such  megafunction  design,  netlist,  support  information,
---device programming or simulation file,  or any other  related documentation
---or information  is prohibited  for  any  other purpose,  including, but not
---limited to  modification,  reverse engineering,  de-compiling, or use  with
---any other  silicon devices,  unless such use is  explicitly  licensed under
---a separate agreement with  Altera  or a megafunction partner.  Title to the
---intellectual property,  including patents,  copyrights,  trademarks,  trade
---secrets,  or maskworks,  embodied in any such megafunction design, netlist,
---support  information,  device programming or simulation file,  or any other
---related documentation or information provided by  Altera  or a megafunction
---partner, remains with Altera, the megafunction partner, or their respective
---licensors. No other licenses, including any licenses needed under any third
---party's intellectual property, are provided herein.
-
-
-FUNCTION bustri 
-(
-	data[15..0],
-	enabledt
-)
-
-RETURNS (
-	tridata[15..0]
-);
diff --git a/fpga/usrp1/megacells/bustri.v b/fpga/usrp1/megacells/bustri.v
deleted file mode 100755
index e40c69476..000000000
--- a/fpga/usrp1/megacells/bustri.v
+++ /dev/null
@@ -1,71 +0,0 @@
-// megafunction wizard: %LPM_BUSTRI%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: lpm_bustri 
-
-// ============================================================
-// File Name: bustri.v
-// Megafunction Name(s):
-// 			lpm_bustri
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-// ************************************************************
-
-
-//Copyright (C) 1991-2003 Altera Corporation
-//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-//support information,  device programming or simulation file,  and any other
-//associated  documentation or information  provided by  Altera  or a partner
-//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-//other  use  of such  megafunction  design,  netlist,  support  information,
-//device programming or simulation file,  or any other  related documentation
-//or information  is prohibited  for  any  other purpose,  including, but not
-//limited to  modification,  reverse engineering,  de-compiling, or use  with
-//any other  silicon devices,  unless such use is  explicitly  licensed under
-//a separate agreement with  Altera  or a megafunction partner.  Title to the
-//intellectual property,  including patents,  copyrights,  trademarks,  trade
-//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-//support  information,  device programming or simulation file,  or any other
-//related documentation or information provided by  Altera  or a megafunction
-//partner, remains with Altera, the megafunction partner, or their respective
-//licensors. No other licenses, including any licenses needed under any third
-//party's intellectual property, are provided herein.
-
-
-module bustri (
-	data,
-	enabledt,
-	tridata);
-
-	input	[15:0]  data;
-	input	  enabledt;
-	inout	[15:0]  tridata;
-
-
-	lpm_bustri	lpm_bustri_component (
-				.tridata (tridata),
-				.enabledt (enabledt),
-				.data (data));
-	defparam
-		lpm_bustri_component.lpm_width = 16,
-		lpm_bustri_component.lpm_type = "LPM_BUSTRI";
-
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: nBit NUMERIC "16"
-// Retrieval info: PRIVATE: BiDir NUMERIC "0"
-// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
-// Retrieval info: USED_PORT: tridata 0 0 16 0 BIDIR NODEFVAL tridata[15..0]
-// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
-// Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
-// Retrieval info: CONNECT: tridata 0 0 16 0 @tridata 0 0 16 0
-// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
-// Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
-// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
diff --git a/fpga/usrp1/megacells/bustri_bb.v b/fpga/usrp1/megacells/bustri_bb.v
deleted file mode 100755
index 4cbc1609c..000000000
--- a/fpga/usrp1/megacells/bustri_bb.v
+++ /dev/null
@@ -1,31 +0,0 @@
-//Copyright (C) 1991-2003 Altera Corporation
-//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-//support information,  device programming or simulation file,  and any other
-//associated  documentation or information  provided by  Altera  or a partner
-//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-//other  use  of such  megafunction  design,  netlist,  support  information,
-//device programming or simulation file,  or any other  related documentation
-//or information  is prohibited  for  any  other purpose,  including, but not
-//limited to  modification,  reverse engineering,  de-compiling, or use  with
-//any other  silicon devices,  unless such use is  explicitly  licensed under
-//a separate agreement with  Altera  or a megafunction partner.  Title to the
-//intellectual property,  including patents,  copyrights,  trademarks,  trade
-//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-//support  information,  device programming or simulation file,  or any other
-//related documentation or information provided by  Altera  or a megafunction
-//partner, remains with Altera, the megafunction partner, or their respective
-//licensors. No other licenses, including any licenses needed under any third
-//party's intellectual property, are provided herein.
-
-module bustri (
-	data,
-	enabledt,
-	tridata);
-
-	input	[15:0]  data;
-	input	  enabledt;
-	inout	[15:0]  tridata;
-
-endmodule
-
diff --git a/fpga/usrp1/megacells/bustri_inst.v b/fpga/usrp1/megacells/bustri_inst.v
deleted file mode 100755
index 2b4e49638..000000000
--- a/fpga/usrp1/megacells/bustri_inst.v
+++ /dev/null
@@ -1,5 +0,0 @@
-bustri	bustri_inst (
-	.data ( data_sig ),
-	.enabledt ( enabledt_sig ),
-	.tridata ( tridata_sig )
-	);
diff --git a/fpga/usrp1/megacells/clk_doubler.v b/fpga/usrp1/megacells/clk_doubler.v
deleted file mode 100644
index b3762a960..000000000
--- a/fpga/usrp1/megacells/clk_doubler.v
+++ /dev/null
@@ -1,198 +0,0 @@
-// megafunction wizard: %ALTPLL%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: altpll 
-
-// ============================================================
-// File Name: clk_doubler.v
-// Megafunction Name(s):
-// 			altpll
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 4.2 Build 156 11/29/2004 SJ Web Edition
-// ************************************************************
-
-
-//Copyright (C) 1991-2004 Altera Corporation
-//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-//support information,  device programming or simulation file,  and any other
-//associated  documentation or information  provided by  Altera  or a partner
-//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-//other  use  of such  megafunction  design,  netlist,  support  information,
-//device programming or simulation file,  or any other  related documentation
-//or information  is prohibited  for  any  other purpose,  including, but not
-//limited to  modification,  reverse engineering,  de-compiling, or use  with
-//any other  silicon devices,  unless such use is  explicitly  licensed under
-//a separate agreement with  Altera  or a megafunction partner.  Title to the
-//intellectual property,  including patents,  copyrights,  trademarks,  trade
-//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-//support  information,  device programming or simulation file,  or any other
-//related documentation or information provided by  Altera  or a megafunction
-//partner, remains with Altera, the megafunction partner, or their respective
-//licensors. No other licenses, including any licenses needed under any third
-//party's intellectual property, are provided herein.
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module clk_doubler (
-	inclk0,
-	c0);
-
-	input	  inclk0;
-	output	  c0;
-
-	wire [5:0] sub_wire0;
-	wire [0:0] sub_wire4 = 1'h0;
-	wire [0:0] sub_wire1 = sub_wire0[0:0];
-	wire  c0 = sub_wire1;
-	wire  sub_wire2 = inclk0;
-	wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
-
-	altpll	altpll_component (
-				.inclk (sub_wire3),
-				.clk (sub_wire0)
-				// synopsys translate_off
-				,
-				.activeclock (),
-				.areset (),
-				.clkbad (),
-				.clkena (),
-				.clkloss (),
-				.clkswitch (),
-				.enable0 (),
-				.enable1 (),
-				.extclk (),
-				.extclkena (),
-				.fbin (),
-				.locked (),
-				.pfdena (),
-				.pllena (),
-				.scanaclr (),
-				.scanclk (),
-				.scandata (),
-				.scandataout (),
-				.scandone (),
-				.scanread (),
-				.scanwrite (),
-				.sclkout0 (),
-				.sclkout1 ()
-				// synopsys translate_on
-				);
-	defparam
-		altpll_component.clk0_duty_cycle = 50,
-		altpll_component.lpm_type = "altpll",
-		altpll_component.clk0_multiply_by = 2,
-		altpll_component.inclk0_input_frequency = 15625,
-		altpll_component.clk0_divide_by = 1,
-		altpll_component.pll_type = "AUTO",
-		altpll_component.intended_device_family = "Cyclone",
-		altpll_component.operation_mode = "NORMAL",
-		altpll_component.compensate_clock = "CLK0",
-		altpll_component.clk0_phase_shift = "0";
-
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
-// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "512.000"
-// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "64.000"
-// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
-// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
-// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
-// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
-// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15625"
-// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
-// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
-// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
-// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
-// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.v TRUE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.inc FALSE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.cmp FALSE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.bsf FALSE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_inst.v FALSE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_bb.v TRUE FALSE
diff --git a/fpga/usrp1/megacells/clk_doubler_bb.v b/fpga/usrp1/megacells/clk_doubler_bb.v
deleted file mode 100644
index 48c52e795..000000000
--- a/fpga/usrp1/megacells/clk_doubler_bb.v
+++ /dev/null
@@ -1,143 +0,0 @@
-// megafunction wizard: %ALTPLL%VBB%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: altpll 
-
-// ============================================================
-// File Name: clk_doubler.v
-// Megafunction Name(s):
-// 			altpll
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 4.2 Build 156 11/29/2004 SJ Web Edition
-// ************************************************************
-
-//Copyright (C) 1991-2004 Altera Corporation
-//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-//support information,  device programming or simulation file,  and any other
-//associated  documentation or information  provided by  Altera  or a partner
-//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-//other  use  of such  megafunction  design,  netlist,  support  information,
-//device programming or simulation file,  or any other  related documentation
-//or information  is prohibited  for  any  other purpose,  including, but not
-//limited to  modification,  reverse engineering,  de-compiling, or use  with
-//any other  silicon devices,  unless such use is  explicitly  licensed under
-//a separate agreement with  Altera  or a megafunction partner.  Title to the
-//intellectual property,  including patents,  copyrights,  trademarks,  trade
-//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-//support  information,  device programming or simulation file,  or any other
-//related documentation or information provided by  Altera  or a megafunction
-//partner, remains with Altera, the megafunction partner, or their respective
-//licensors. No other licenses, including any licenses needed under any third
-//party's intellectual property, are provided herein.
-
-module clk_doubler (
-	inclk0,
-	c0);
-
-	input	  inclk0;
-	output	  c0;
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
-// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "512.000"
-// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "64.000"
-// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
-// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
-// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
-// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
-// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15625"
-// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
-// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
-// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
-// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
-// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.v TRUE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.inc FALSE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.cmp FALSE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.bsf FALSE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_inst.v FALSE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_bb.v TRUE FALSE
diff --git a/fpga/usrp1/megacells/dspclkpll.v b/fpga/usrp1/megacells/dspclkpll.v
deleted file mode 100644
index 81e622137..000000000
--- a/fpga/usrp1/megacells/dspclkpll.v
+++ /dev/null
@@ -1,237 +0,0 @@
-// megafunction wizard: %ALTPLL%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: altpll 
-
-// ============================================================
-// File Name: dspclkpll.v
-// Megafunction Name(s):
-// 			altpll
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 4.0 Build 214 3/25/2004 SP 1 SJ Web Edition
-// ************************************************************
-
-
-//Copyright (C) 1991-2004 Altera Corporation
-//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-//support information,  device programming or simulation file,  and any other
-//associated  documentation or information  provided by  Altera  or a partner
-//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-//other  use  of such  megafunction  design,  netlist,  support  information,
-//device programming or simulation file,  or any other  related documentation
-//or information  is prohibited  for  any  other purpose,  including, but not
-//limited to  modification,  reverse engineering,  de-compiling, or use  with
-//any other  silicon devices,  unless such use is  explicitly  licensed under
-//a separate agreement with  Altera  or a megafunction partner.  Title to the
-//intellectual property,  including patents,  copyrights,  trademarks,  trade
-//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-//support  information,  device programming or simulation file,  or any other
-//related documentation or information provided by  Altera  or a megafunction
-//partner, remains with Altera, the megafunction partner, or their respective
-//licensors. No other licenses, including any licenses needed under any third
-//party's intellectual property, are provided herein.
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module dspclkpll (
-	inclk0,
-	c0,
-	c1);
-
-	input	  inclk0;
-	output	  c0;
-	output	  c1;
-
-	wire [5:0] sub_wire0;
-	wire [0:0] sub_wire5 = 1'h0;
-	wire [1:1] sub_wire2 = sub_wire0[1:1];
-	wire [0:0] sub_wire1 = sub_wire0[0:0];
-	wire  c0 = sub_wire1;
-	wire  c1 = sub_wire2;
-	wire  sub_wire3 = inclk0;
-	wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
-
-	altpll	altpll_component (
-				.inclk (sub_wire4),
-				.clk (sub_wire0)
-				// synopsys translate_off
-,
-				.fbin (),
-				.pllena (),
-				.clkswitch (),
-				.areset (),
-				.pfdena (),
-				.clkena (),
-				.extclkena (),
-				.scanclk (),
-				.scanaclr (),
-				.scandata (),
-				.scanread (),
-				.scanwrite (),
-				.extclk (),
-				.clkbad (),
-				.activeclock (),
-				.locked (),
-				.clkloss (),
-				.scandataout (),
-				.scandone (),
-				.sclkout1 (),
-				.sclkout0 (),
-				.enable0 (),
-				.enable1 ()
-				// synopsys translate_on
-
-);
-	defparam
-		altpll_component.clk1_divide_by = 1,
-		altpll_component.clk1_phase_shift = "0",
-		altpll_component.clk0_duty_cycle = 50,
-		altpll_component.lpm_type = "altpll",
-		altpll_component.clk0_multiply_by = 1,
-		altpll_component.inclk0_input_frequency = 15625,
-		altpll_component.clk0_divide_by = 1,
-		altpll_component.clk1_duty_cycle = 50,
-		altpll_component.pll_type = "AUTO",
-		altpll_component.clk1_multiply_by = 2,
-		altpll_component.clk0_time_delay = "0",
-		altpll_component.intended_device_family = "Cyclone",
-		altpll_component.operation_mode = "NORMAL",
-		altpll_component.compensate_clock = "CLK0",
-		altpll_component.clk1_time_delay = "0",
-		altpll_component.clk0_phase_shift = "0";
-
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-// Retrieval info: PRIVATE: TIME_SHIFT0 STRING "0.00000000"
-// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-// Retrieval info: PRIVATE: TIME_SHIFT1 STRING "0.00000000"
-// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_0 STRING "inclk;fbin;pllena;clkswitch;areset"
-// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
-// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_1 STRING "pfdena;clkena;extclkena;scanclk;scanaclr"
-// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_2 STRING "scandata;scanread;scanwrite;clk;extclk"
-// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "512.000"
-// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_3 STRING "clkbad;activeclock;locked;clkloss;scandataout"
-// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "64.000"
-// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_4 STRING "scandone;sclkout1;sclkout0;enable0;enable1"
-// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
-// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
-// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.000"
-// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
-// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15625"
-// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
-// Retrieval info: CONSTANT: CLK0_TIME_DELAY STRING "0"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-// Retrieval info: CONSTANT: CLK1_TIME_DELAY STRING "0"
-// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
-// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
-// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT VCC "c1"
-// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
-// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
-// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll.v TRUE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll.inc FALSE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll.cmp FALSE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll.bsf FALSE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll_inst.v FALSE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll_bb.v TRUE FALSE
diff --git a/fpga/usrp1/megacells/dspclkpll_bb.v b/fpga/usrp1/megacells/dspclkpll_bb.v
deleted file mode 100644
index 489be7bd4..000000000
--- a/fpga/usrp1/megacells/dspclkpll_bb.v
+++ /dev/null
@@ -1,31 +0,0 @@
-//Copyright (C) 1991-2004 Altera Corporation
-//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-//support information,  device programming or simulation file,  and any other
-//associated  documentation or information  provided by  Altera  or a partner
-//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-//other  use  of such  megafunction  design,  netlist,  support  information,
-//device programming or simulation file,  or any other  related documentation
-//or information  is prohibited  for  any  other purpose,  including, but not
-//limited to  modification,  reverse engineering,  de-compiling, or use  with
-//any other  silicon devices,  unless such use is  explicitly  licensed under
-//a separate agreement with  Altera  or a megafunction partner.  Title to the
-//intellectual property,  including patents,  copyrights,  trademarks,  trade
-//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-//support  information,  device programming or simulation file,  or any other
-//related documentation or information provided by  Altera  or a megafunction
-//partner, remains with Altera, the megafunction partner, or their respective
-//licensors. No other licenses, including any licenses needed under any third
-//party's intellectual property, are provided herein.
-
-module dspclkpll (
-	inclk0,
-	c0,
-	c1);
-
-	input	  inclk0;
-	output	  c0;
-	output	  c1;
-
-endmodule
-
diff --git a/fpga/usrp1/megacells/fifo_1kx16.bsf b/fpga/usrp1/megacells/fifo_1kx16.bsf
deleted file mode 100755
index 2de80816f..000000000
--- a/fpga/usrp1/megacells/fifo_1kx16.bsf
+++ /dev/null
@@ -1,107 +0,0 @@
-/*

-WARNING: Do NOT edit the input and output ports in this file in a text

-editor if you plan to continue editing the block that represents it in

-the Block Editor! File corruption is VERY likely to occur.

-*/

-/*

-Copyright (C) 1991-2006 Altera Corporation

-Your use of Altera Corporation's design tools, logic functions 

-and other software and tools, and its AMPP partner logic 

-functions, and any output files any of the foregoing 

-(including device programming or simulation files), and any 

-associated documentation or information are expressly subject 

-to the terms and conditions of the Altera Program License 

-Subscription Agreement, Altera MegaCore Function License 

-Agreement, or other applicable license agreement, including, 

-without limitation, that your use is for the sole purpose of 

-programming logic devices manufactured by Altera and sold by 

-Altera or its authorized distributors.  Please refer to the 

-applicable agreement for further details.

-*/

-(header "symbol" (version "1.1"))

-(symbol

-	(rect 0 0 160 160)

-	(text "fifo_1kx16" (rect 51 1 119 17)(font "Arial" (font_size 10)))

-	(text "inst" (rect 8 144 25 156)(font "Arial" ))

-	(port

-		(pt 0 32)

-		(input)

-		(text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))

-		(text "data[15..0]" (rect 20 26 71 39)(font "Arial" (font_size 8)))

-		(line (pt 0 32)(pt 16 32)(line_width 3))

-	)

-	(port

-		(pt 0 56)

-		(input)

-		(text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8)))

-		(text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8)))

-		(line (pt 0 56)(pt 16 56)(line_width 1))

-	)

-	(port

-		(pt 0 72)

-		(input)

-		(text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8)))

-		(text "rdreq" (rect 20 66 44 79)(font "Arial" (font_size 8)))

-		(line (pt 0 72)(pt 16 72)(line_width 1))

-	)

-	(port

-		(pt 0 96)

-		(input)

-		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))

-		(text "clock" (rect 26 90 49 103)(font "Arial" (font_size 8)))

-		(line (pt 0 96)(pt 16 96)(line_width 1))

-	)

-	(port

-		(pt 0 128)

-		(input)

-		(text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8)))

-		(text "aclr" (rect 20 122 37 135)(font "Arial" (font_size 8)))

-		(line (pt 0 128)(pt 16 128)(line_width 1))

-	)

-	(port

-		(pt 160 32)

-		(output)

-		(text "q[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))

-		(text "q[15..0]" (rect 105 26 141 39)(font "Arial" (font_size 8)))

-		(line (pt 160 32)(pt 144 32)(line_width 3))

-	)

-	(port

-		(pt 160 56)

-		(output)

-		(text "full" (rect 0 0 16 14)(font "Arial" (font_size 8)))

-		(text "full" (rect 127 50 142 63)(font "Arial" (font_size 8)))

-		(line (pt 160 56)(pt 144 56)(line_width 1))

-	)

-	(port

-		(pt 160 72)

-		(output)

-		(text "empty" (rect 0 0 34 14)(font "Arial" (font_size 8)))

-		(text "empty" (rect 112 66 141 79)(font "Arial" (font_size 8)))

-		(line (pt 160 72)(pt 144 72)(line_width 1))

-	)

-	(port

-		(pt 160 88)

-		(output)

-		(text "almost_empty" (rect 0 0 77 14)(font "Arial" (font_size 8)))

-		(text "almost_empty" (rect 75 82 141 95)(font "Arial" (font_size 8)))

-		(line (pt 160 88)(pt 144 88)(line_width 1))

-	)

-	(port

-		(pt 160 104)

-		(output)

-		(text "usedw[9..0]" (rect 0 0 68 14)(font "Arial" (font_size 8)))

-		(text "usedw[9..0]" (rect 83 98 136 111)(font "Arial" (font_size 8)))

-		(line (pt 160 104)(pt 144 104)(line_width 3))

-	)

-	(drawing

-		(text "16 bits x 1024 words" (rect 58 132 144 144)(font "Arial" ))

-		(text "almost_empty < 504" (rect 58 122 144 134)(font "Arial" ))

-		(line (pt 16 16)(pt 144 16)(line_width 1))

-		(line (pt 144 16)(pt 144 144)(line_width 1))

-		(line (pt 144 144)(pt 16 144)(line_width 1))

-		(line (pt 16 144)(pt 16 16)(line_width 1))

-		(line (pt 16 116)(pt 144 116)(line_width 1))

-		(line (pt 16 90)(pt 22 96)(line_width 1))

-		(line (pt 22 96)(pt 16 102)(line_width 1))

-	)

-)

diff --git a/fpga/usrp1/megacells/fifo_1kx16.cmp b/fpga/usrp1/megacells/fifo_1kx16.cmp
deleted file mode 100755
index 9b2c2c0c3..000000000
--- a/fpga/usrp1/megacells/fifo_1kx16.cmp
+++ /dev/null
@@ -1,30 +0,0 @@
---Copyright (C) 1991-2006 Altera Corporation

---Your use of Altera Corporation's design tools, logic functions 

---and other software and tools, and its AMPP partner logic 

---functions, and any output files any of the foregoing 

---(including device programming or simulation files), and any 

---associated documentation or information are expressly subject 

---to the terms and conditions of the Altera Program License 

---Subscription Agreement, Altera MegaCore Function License 

---Agreement, or other applicable license agreement, including, 

---without limitation, that your use is for the sole purpose of 

---programming logic devices manufactured by Altera and sold by 

---Altera or its authorized distributors.  Please refer to the 

---applicable agreement for further details.

-

-

-component fifo_1kx16

-	PORT

-	(

-		aclr		: IN STD_LOGIC ;

-		clock		: IN STD_LOGIC ;

-		data		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);

-		rdreq		: IN STD_LOGIC ;

-		wrreq		: IN STD_LOGIC ;

-		almost_empty		: OUT STD_LOGIC ;

-		empty		: OUT STD_LOGIC ;

-		full		: OUT STD_LOGIC ;

-		q		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0);

-		usedw		: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)

-	);

-end component;

diff --git a/fpga/usrp1/megacells/fifo_1kx16.inc b/fpga/usrp1/megacells/fifo_1kx16.inc
deleted file mode 100755
index 0b70afe62..000000000
--- a/fpga/usrp1/megacells/fifo_1kx16.inc
+++ /dev/null
@@ -1,31 +0,0 @@
---Copyright (C) 1991-2006 Altera Corporation

---Your use of Altera Corporation's design tools, logic functions 

---and other software and tools, and its AMPP partner logic 

---functions, and any output files any of the foregoing 

---(including device programming or simulation files), and any 

---associated documentation or information are expressly subject 

---to the terms and conditions of the Altera Program License 

---Subscription Agreement, Altera MegaCore Function License 

---Agreement, or other applicable license agreement, including, 

---without limitation, that your use is for the sole purpose of 

---programming logic devices manufactured by Altera and sold by 

---Altera or its authorized distributors.  Please refer to the 

---applicable agreement for further details.

-

-

-FUNCTION fifo_1kx16 

-(

-	aclr,

-	clock,

-	data[15..0],

-	rdreq,

-	wrreq

-)

-

-RETURNS (

-	almost_empty,

-	empty,

-	full,

-	q[15..0],

-	usedw[9..0]

-);

diff --git a/fpga/usrp1/megacells/fifo_1kx16.v b/fpga/usrp1/megacells/fifo_1kx16.v
deleted file mode 100755
index 4f7e94ef5..000000000
--- a/fpga/usrp1/megacells/fifo_1kx16.v
+++ /dev/null
@@ -1,175 +0,0 @@
-// megafunction wizard: %FIFO%

-// GENERATION: STANDARD

-// VERSION: WM1.0

-// MODULE: scfifo 

-

-// ============================================================

-// File Name: fifo_1kx16.v

-// Megafunction Name(s):

-// 			scfifo

-// ============================================================

-// ************************************************************

-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!

-//

-// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition

-// ************************************************************

-

-

-//Copyright (C) 1991-2006 Altera Corporation

-//Your use of Altera Corporation's design tools, logic functions 

-//and other software and tools, and its AMPP partner logic 

-//functions, and any output files any of the foregoing 

-//(including device programming or simulation files), and any 

-//associated documentation or information are expressly subject 

-//to the terms and conditions of the Altera Program License 

-//Subscription Agreement, Altera MegaCore Function License 

-//Agreement, or other applicable license agreement, including, 

-//without limitation, that your use is for the sole purpose of 

-//programming logic devices manufactured by Altera and sold by 

-//Altera or its authorized distributors.  Please refer to the 

-//applicable agreement for further details.

-

-

-// synopsys translate_off

-`timescale 1 ps / 1 ps

-// synopsys translate_on

-module fifo_1kx16 (

-	aclr,

-	clock,

-	data,

-	rdreq,

-	wrreq,

-	almost_empty,

-	empty,

-	full,

-	q,

-	usedw);

-

-	input	  aclr;

-	input	  clock;

-	input	[15:0]  data;

-	input	  rdreq;

-	input	  wrreq;

-	output	  almost_empty;

-	output	  empty;

-	output	  full;

-	output	[15:0]  q;

-	output	[9:0]  usedw;

-

-	wire [9:0] sub_wire0;

-	wire  sub_wire1;

-	wire  sub_wire2;

-	wire [15:0] sub_wire3;

-	wire  sub_wire4;

-	wire [9:0] usedw = sub_wire0[9:0];

-	wire  empty = sub_wire1;

-	wire  almost_empty = sub_wire2;

-	wire [15:0] q = sub_wire3[15:0];

-	wire  full = sub_wire4;

-

-	scfifo	scfifo_component (

-				.rdreq (rdreq),

-				.aclr (aclr),

-				.clock (clock),

-				.wrreq (wrreq),

-				.data (data),

-				.usedw (sub_wire0),

-				.empty (sub_wire1),

-				.almost_empty (sub_wire2),

-				.q (sub_wire3),

-				.full (sub_wire4)

-				// synopsys translate_off

-				,

-				.sclr (),

-				.almost_full ()

-				// synopsys translate_on

-				);

-	defparam

-		scfifo_component.add_ram_output_register = "OFF",

-		scfifo_component.almost_empty_value = 504,

-		scfifo_component.intended_device_family = "Cyclone",

-		scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K",

-		scfifo_component.lpm_numwords = 1024,

-		scfifo_component.lpm_showahead = "OFF",

-		scfifo_component.lpm_type = "scfifo",

-		scfifo_component.lpm_width = 16,

-		scfifo_component.lpm_widthu = 10,

-		scfifo_component.overflow_checking = "ON",

-		scfifo_component.underflow_checking = "ON",

-		scfifo_component.use_eab = "ON";

-

-

-endmodule

-

-// ============================================================

-// CNX file retrieval info

-// ============================================================

-// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1"

-// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "504"

-// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"

-// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"

-// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"

-// Retrieval info: PRIVATE: Clock NUMERIC "0"

-// Retrieval info: PRIVATE: Depth NUMERIC "1024"

-// Retrieval info: PRIVATE: Empty NUMERIC "1"

-// Retrieval info: PRIVATE: Full NUMERIC "1"

-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"

-// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"

-// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"

-// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"

-// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"

-// Retrieval info: PRIVATE: Optimize NUMERIC "2"

-// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"

-// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"

-// Retrieval info: PRIVATE: UsedW NUMERIC "1"

-// Retrieval info: PRIVATE: Width NUMERIC "16"

-// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"

-// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"

-// Retrieval info: PRIVATE: rsFull NUMERIC "0"

-// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"

-// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"

-// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"

-// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"

-// Retrieval info: PRIVATE: wsFull NUMERIC "1"

-// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"

-// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"

-// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "504"

-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"

-// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"

-// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"

-// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"

-// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"

-// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"

-// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"

-// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"

-// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"

-// Retrieval info: CONSTANT: USE_EAB STRING "ON"

-// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr

-// Retrieval info: USED_PORT: almost_empty 0 0 0 0 OUTPUT NODEFVAL almost_empty

-// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock

-// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]

-// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty

-// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full

-// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]

-// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq

-// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL usedw[9..0]

-// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq

-// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0

-// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0

-// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0

-// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0

-// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0

-// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0

-// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0

-// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0

-// Retrieval info: CONNECT: almost_empty 0 0 0 0 @almost_empty 0 0 0 0

-// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0

-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all

-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.v TRUE

-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.inc TRUE

-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.cmp TRUE

-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.bsf TRUE FALSE

-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_inst.v TRUE

-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_bb.v TRUE

-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_waveforms.html FALSE

-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_wave*.jpg FALSE

diff --git a/fpga/usrp1/megacells/fifo_1kx16_bb.v b/fpga/usrp1/megacells/fifo_1kx16_bb.v
deleted file mode 100755
index 9d9912bc2..000000000
--- a/fpga/usrp1/megacells/fifo_1kx16_bb.v
+++ /dev/null
@@ -1,127 +0,0 @@
-// megafunction wizard: %FIFO%VBB%

-// GENERATION: STANDARD

-// VERSION: WM1.0

-// MODULE: scfifo 

-

-// ============================================================

-// File Name: fifo_1kx16.v

-// Megafunction Name(s):

-// 			scfifo

-// ============================================================

-// ************************************************************

-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!

-//

-// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition

-// ************************************************************

-

-//Copyright (C) 1991-2006 Altera Corporation

-//Your use of Altera Corporation's design tools, logic functions 

-//and other software and tools, and its AMPP partner logic 

-//functions, and any output files any of the foregoing 

-//(including device programming or simulation files), and any 

-//associated documentation or information are expressly subject 

-//to the terms and conditions of the Altera Program License 

-//Subscription Agreement, Altera MegaCore Function License 

-//Agreement, or other applicable license agreement, including, 

-//without limitation, that your use is for the sole purpose of 

-//programming logic devices manufactured by Altera and sold by 

-//Altera or its authorized distributors.  Please refer to the 

-//applicable agreement for further details.

-

-module fifo_1kx16 (

-	aclr,

-	clock,

-	data,

-	rdreq,

-	wrreq,

-	almost_empty,

-	empty,

-	full,

-	q,

-	usedw);

-

-	input	  aclr;

-	input	  clock;

-	input	[15:0]  data;

-	input	  rdreq;

-	input	  wrreq;

-	output	  almost_empty;

-	output	  empty;

-	output	  full;

-	output	[15:0]  q;

-	output	[9:0]  usedw;

-

-endmodule

-

-// ============================================================

-// CNX file retrieval info

-// ============================================================

-// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1"

-// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "504"

-// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"

-// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"

-// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"

-// Retrieval info: PRIVATE: Clock NUMERIC "0"

-// Retrieval info: PRIVATE: Depth NUMERIC "1024"

-// Retrieval info: PRIVATE: Empty NUMERIC "1"

-// Retrieval info: PRIVATE: Full NUMERIC "1"

-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"

-// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"

-// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"

-// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"

-// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"

-// Retrieval info: PRIVATE: Optimize NUMERIC "2"

-// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"

-// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"

-// Retrieval info: PRIVATE: UsedW NUMERIC "1"

-// Retrieval info: PRIVATE: Width NUMERIC "16"

-// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"

-// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"

-// Retrieval info: PRIVATE: rsFull NUMERIC "0"

-// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"

-// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"

-// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"

-// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"

-// Retrieval info: PRIVATE: wsFull NUMERIC "1"

-// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"

-// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"

-// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "504"

-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"

-// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"

-// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"

-// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"

-// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"

-// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"

-// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"

-// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"

-// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"

-// Retrieval info: CONSTANT: USE_EAB STRING "ON"

-// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr

-// Retrieval info: USED_PORT: almost_empty 0 0 0 0 OUTPUT NODEFVAL almost_empty

-// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock

-// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]

-// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty

-// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full

-// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]

-// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq

-// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL usedw[9..0]

-// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq

-// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0

-// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0

-// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0

-// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0

-// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0

-// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0

-// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0

-// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0

-// Retrieval info: CONNECT: almost_empty 0 0 0 0 @almost_empty 0 0 0 0

-// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0

-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all

-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.v TRUE

-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.inc TRUE

-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.cmp TRUE

-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.bsf TRUE FALSE

-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_inst.v TRUE

-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_bb.v TRUE

-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_waveforms.html FALSE

-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_wave*.jpg FALSE

diff --git a/fpga/usrp1/megacells/fifo_1kx16_inst.v b/fpga/usrp1/megacells/fifo_1kx16_inst.v
deleted file mode 100755
index 73662dea3..000000000
--- a/fpga/usrp1/megacells/fifo_1kx16_inst.v
+++ /dev/null
@@ -1,12 +0,0 @@
-fifo_1kx16	fifo_1kx16_inst (

-	.aclr ( aclr_sig ),

-	.clock ( clock_sig ),

-	.data ( data_sig ),

-	.rdreq ( rdreq_sig ),

-	.wrreq ( wrreq_sig ),

-	.almost_empty ( almost_empty_sig ),

-	.empty ( empty_sig ),

-	.full ( full_sig ),

-	.q ( q_sig ),

-	.usedw ( usedw_sig )

-	);

diff --git a/fpga/usrp1/megacells/fifo_2k.v b/fpga/usrp1/megacells/fifo_2k.v
deleted file mode 100644
index 5e2a38520..000000000
--- a/fpga/usrp1/megacells/fifo_2k.v
+++ /dev/null
@@ -1,3343 +0,0 @@
-// megafunction wizard: %FIFO%CBX%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: dcfifo 
-
-// ============================================================
-// File Name: fifo_2k.v
-// Megafunction Name(s):
-// 			dcfifo
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition
-// ************************************************************
-
-
-//Copyright (C) 1991-2005 Altera Corporation
-//Your use of Altera Corporation's design tools, logic functions 
-//and other software and tools, and its AMPP partner logic       
-//functions, and any output files any of the foregoing           
-//(including device programming or simulation files), and any    
-//associated documentation or information are expressly subject  
-//to the terms and conditions of the Altera Program License      
-//Subscription Agreement, Altera MegaCore Function License       
-//Agreement, or other applicable license agreement, including,   
-//without limitation, that your use is for the sole purpose of   
-//programming logic devices manufactured by Altera and sold by   
-//Altera or its authorized distributors.  Please refer to the    
-//applicable agreement for further details.
-
-
-//dcfifo ADD_RAM_OUTPUT_REGISTER="OFF" CLOCKS_ARE_SYNCHRONIZED="FALSE" DEVICE_FAMILY="Cyclone" LPM_NUMWORDS=2048 LPM_SHOWAHEAD="ON" LPM_WIDTH=16 LPM_WIDTHU=11 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" USE_EAB="ON" aclr data q rdclk rdempty rdreq rdusedw wrclk wrfull wrreq wrusedw
-//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END
-
-
-//a_gray2bin device_family="Cyclone" WIDTH=11 bin gray
-//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_mgl 2005:05:19:13:51:58:SJ  VERSION_END
-
-//synthesis_resources = 
-//synopsys translate_off
-`timescale 1 ps / 1 ps
-//synopsys translate_on
-module  fifo_2k_a_gray2bin_8m4
-	( 
-	bin,
-	gray) /* synthesis synthesis_clearbox=1 */;
-	output   [10:0]  bin;
-	input   [10:0]  gray;
-
-	wire  xor0;
-	wire  xor1;
-	wire  xor2;
-	wire  xor3;
-	wire  xor4;
-	wire  xor5;
-	wire  xor6;
-	wire  xor7;
-	wire  xor8;
-	wire  xor9;
-
-	assign
-		bin = {gray[10], xor9, xor8, xor7, xor6, xor5, xor4, xor3, xor2, xor1, xor0},
-		xor0 = (gray[0] ^ xor1),
-		xor1 = (gray[1] ^ xor2),
-		xor2 = (gray[2] ^ xor3),
-		xor3 = (gray[3] ^ xor4),
-		xor4 = (gray[4] ^ xor5),
-		xor5 = (gray[5] ^ xor6),
-		xor6 = (gray[6] ^ xor7),
-		xor7 = (gray[7] ^ xor8),
-		xor8 = (gray[8] ^ xor9),
-		xor9 = (gray[10] ^ gray[9]);
-endmodule //fifo_2k_a_gray2bin_8m4
-
-
-//a_graycounter DEVICE_FAMILY="Cyclone" WIDTH=11 aclr clock cnt_en q
-//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END
-
-//synthesis_resources = lut 12 
-//synopsys translate_off
-`timescale 1 ps / 1 ps
-//synopsys translate_on
-module  fifo_2k_a_graycounter_726
-	( 
-	aclr,
-	clock,
-	cnt_en,
-	q) /* synthesis synthesis_clearbox=1 */;
-	input   aclr;
-	input   clock;
-	input   cnt_en;
-	output   [10:0]  q;
-
-	wire  [0:0]   wire_countera_0cout;
-	wire  [0:0]   wire_countera_1cout;
-	wire  [0:0]   wire_countera_2cout;
-	wire  [0:0]   wire_countera_3cout;
-	wire  [0:0]   wire_countera_4cout;
-	wire  [0:0]   wire_countera_5cout;
-	wire  [0:0]   wire_countera_6cout;
-	wire  [0:0]   wire_countera_7cout;
-	wire  [0:0]   wire_countera_8cout;
-	wire  [0:0]   wire_countera_9cout;
-	wire  [10:0]   wire_countera_regout;
-	wire  wire_parity_cout;
-	wire  wire_parity_regout;
-	wire  [10:0]  power_modified_counter_values;
-	wire sclr;
-	wire updown;
-
-	cyclone_lcell   countera_0
-	( 
-	.aclr(aclr),
-	.cin(wire_parity_cout),
-	.clk(clock),
-	.combout(),
-	.cout(wire_countera_0cout[0:0]),
-	.dataa(cnt_en),
-	.datab(wire_countera_regout[0:0]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[0:0]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_0.cin_used = "true",
-		countera_0.lut_mask = "c6a0",
-		countera_0.operation_mode = "arithmetic",
-		countera_0.sum_lutc_input = "cin",
-		countera_0.synch_mode = "on",
-		countera_0.lpm_type = "cyclone_lcell";
-	cyclone_lcell   countera_1
-	( 
-	.aclr(aclr),
-	.cin(wire_countera_0cout[0:0]),
-	.clk(clock),
-	.combout(),
-	.cout(wire_countera_1cout[0:0]),
-	.dataa(power_modified_counter_values[0]),
-	.datab(power_modified_counter_values[1]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[1:1]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_1.cin_used = "true",
-		countera_1.lut_mask = "6c50",
-		countera_1.operation_mode = "arithmetic",
-		countera_1.sum_lutc_input = "cin",
-		countera_1.synch_mode = "on",
-		countera_1.lpm_type = "cyclone_lcell";
-	cyclone_lcell   countera_2
-	( 
-	.aclr(aclr),
-	.cin(wire_countera_1cout[0:0]),
-	.clk(clock),
-	.combout(),
-	.cout(wire_countera_2cout[0:0]),
-	.dataa(power_modified_counter_values[1]),
-	.datab(power_modified_counter_values[2]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[2:2]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_2.cin_used = "true",
-		countera_2.lut_mask = "6c50",
-		countera_2.operation_mode = "arithmetic",
-		countera_2.sum_lutc_input = "cin",
-		countera_2.synch_mode = "on",
-		countera_2.lpm_type = "cyclone_lcell";
-	cyclone_lcell   countera_3
-	( 
-	.aclr(aclr),
-	.cin(wire_countera_2cout[0:0]),
-	.clk(clock),
-	.combout(),
-	.cout(wire_countera_3cout[0:0]),
-	.dataa(power_modified_counter_values[2]),
-	.datab(power_modified_counter_values[3]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[3:3]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_3.cin_used = "true",
-		countera_3.lut_mask = "6c50",
-		countera_3.operation_mode = "arithmetic",
-		countera_3.sum_lutc_input = "cin",
-		countera_3.synch_mode = "on",
-		countera_3.lpm_type = "cyclone_lcell";
-	cyclone_lcell   countera_4
-	( 
-	.aclr(aclr),
-	.cin(wire_countera_3cout[0:0]),
-	.clk(clock),
-	.combout(),
-	.cout(wire_countera_4cout[0:0]),
-	.dataa(power_modified_counter_values[3]),
-	.datab(power_modified_counter_values[4]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[4:4]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_4.cin_used = "true",
-		countera_4.lut_mask = "6c50",
-		countera_4.operation_mode = "arithmetic",
-		countera_4.sum_lutc_input = "cin",
-		countera_4.synch_mode = "on",
-		countera_4.lpm_type = "cyclone_lcell";
-	cyclone_lcell   countera_5
-	( 
-	.aclr(aclr),
-	.cin(wire_countera_4cout[0:0]),
-	.clk(clock),
-	.combout(),
-	.cout(wire_countera_5cout[0:0]),
-	.dataa(power_modified_counter_values[4]),
-	.datab(power_modified_counter_values[5]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[5:5]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_5.cin_used = "true",
-		countera_5.lut_mask = "6c50",
-		countera_5.operation_mode = "arithmetic",
-		countera_5.sum_lutc_input = "cin",
-		countera_5.synch_mode = "on",
-		countera_5.lpm_type = "cyclone_lcell";
-	cyclone_lcell   countera_6
-	( 
-	.aclr(aclr),
-	.cin(wire_countera_5cout[0:0]),
-	.clk(clock),
-	.combout(),
-	.cout(wire_countera_6cout[0:0]),
-	.dataa(power_modified_counter_values[5]),
-	.datab(power_modified_counter_values[6]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[6:6]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_6.cin_used = "true",
-		countera_6.lut_mask = "6c50",
-		countera_6.operation_mode = "arithmetic",
-		countera_6.sum_lutc_input = "cin",
-		countera_6.synch_mode = "on",
-		countera_6.lpm_type = "cyclone_lcell";
-	cyclone_lcell   countera_7
-	( 
-	.aclr(aclr),
-	.cin(wire_countera_6cout[0:0]),
-	.clk(clock),
-	.combout(),
-	.cout(wire_countera_7cout[0:0]),
-	.dataa(power_modified_counter_values[6]),
-	.datab(power_modified_counter_values[7]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[7:7]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_7.cin_used = "true",
-		countera_7.lut_mask = "6c50",
-		countera_7.operation_mode = "arithmetic",
-		countera_7.sum_lutc_input = "cin",
-		countera_7.synch_mode = "on",
-		countera_7.lpm_type = "cyclone_lcell";
-	cyclone_lcell   countera_8
-	( 
-	.aclr(aclr),
-	.cin(wire_countera_7cout[0:0]),
-	.clk(clock),
-	.combout(),
-	.cout(wire_countera_8cout[0:0]),
-	.dataa(power_modified_counter_values[7]),
-	.datab(power_modified_counter_values[8]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[8:8]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_8.cin_used = "true",
-		countera_8.lut_mask = "6c50",
-		countera_8.operation_mode = "arithmetic",
-		countera_8.sum_lutc_input = "cin",
-		countera_8.synch_mode = "on",
-		countera_8.lpm_type = "cyclone_lcell";
-	cyclone_lcell   countera_9
-	( 
-	.aclr(aclr),
-	.cin(wire_countera_8cout[0:0]),
-	.clk(clock),
-	.combout(),
-	.cout(wire_countera_9cout[0:0]),
-	.dataa(power_modified_counter_values[8]),
-	.datab(power_modified_counter_values[9]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[9:9]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_9.cin_used = "true",
-		countera_9.lut_mask = "6c50",
-		countera_9.operation_mode = "arithmetic",
-		countera_9.sum_lutc_input = "cin",
-		countera_9.synch_mode = "on",
-		countera_9.lpm_type = "cyclone_lcell";
-	cyclone_lcell   countera_10
-	( 
-	.aclr(aclr),
-	.cin(wire_countera_9cout[0:0]),
-	.clk(clock),
-	.combout(),
-	.cout(),
-	.dataa(power_modified_counter_values[10]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[10:10]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datab(1'b1),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_10.cin_used = "true",
-		countera_10.lut_mask = "5a5a",
-		countera_10.operation_mode = "normal",
-		countera_10.sum_lutc_input = "cin",
-		countera_10.synch_mode = "on",
-		countera_10.lpm_type = "cyclone_lcell";
-	cyclone_lcell   parity
-	( 
-	.aclr(aclr),
-	.cin(updown),
-	.clk(clock),
-	.combout(),
-	.cout(wire_parity_cout),
-	.dataa(cnt_en),
-	.datab(wire_parity_regout),
-	.ena(1'b1),
-	.regout(wire_parity_regout),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		parity.cin_used = "true",
-		parity.lut_mask = "6682",
-		parity.operation_mode = "arithmetic",
-		parity.synch_mode = "on",
-		parity.lpm_type = "cyclone_lcell";
-	assign
-		power_modified_counter_values = {wire_countera_regout[10:0]},
-		q = power_modified_counter_values,
-		sclr = 1'b0,
-		updown = 1'b1;
-endmodule //fifo_2k_a_graycounter_726
-
-
-//a_graycounter DEVICE_FAMILY="Cyclone" PVALUE=1 WIDTH=11 aclr clock cnt_en q
-//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END
-
-//synthesis_resources = lut 12 
-//synopsys translate_off
-`timescale 1 ps / 1 ps
-//synopsys translate_on
-module  fifo_2k_a_graycounter_2r6
-	( 
-	aclr,
-	clock,
-	cnt_en,
-	q) /* synthesis synthesis_clearbox=1 */;
-	input   aclr;
-	input   clock;
-	input   cnt_en;
-	output   [10:0]  q;
-
-	wire  [0:0]   wire_countera_0cout;
-	wire  [0:0]   wire_countera_1cout;
-	wire  [0:0]   wire_countera_2cout;
-	wire  [0:0]   wire_countera_3cout;
-	wire  [0:0]   wire_countera_4cout;
-	wire  [0:0]   wire_countera_5cout;
-	wire  [0:0]   wire_countera_6cout;
-	wire  [0:0]   wire_countera_7cout;
-	wire  [0:0]   wire_countera_8cout;
-	wire  [0:0]   wire_countera_9cout;
-	wire  [10:0]   wire_countera_regout;
-	wire  wire_parity_cout;
-	wire  wire_parity_regout;
-	wire  [10:0]  power_modified_counter_values;
-	wire sclr;
-	wire updown;
-
-	cyclone_lcell   countera_0
-	( 
-	.aclr(aclr),
-	.cin(wire_parity_cout),
-	.clk(clock),
-	.combout(),
-	.cout(wire_countera_0cout[0:0]),
-	.dataa(cnt_en),
-	.datab(wire_countera_regout[0:0]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[0:0]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_0.cin_used = "true",
-		countera_0.lut_mask = "c6a0",
-		countera_0.operation_mode = "arithmetic",
-		countera_0.sum_lutc_input = "cin",
-		countera_0.synch_mode = "on",
-		countera_0.lpm_type = "cyclone_lcell";
-	cyclone_lcell   countera_1
-	( 
-	.aclr(aclr),
-	.cin(wire_countera_0cout[0:0]),
-	.clk(clock),
-	.combout(),
-	.cout(wire_countera_1cout[0:0]),
-	.dataa(power_modified_counter_values[0]),
-	.datab(power_modified_counter_values[1]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[1:1]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_1.cin_used = "true",
-		countera_1.lut_mask = "6c50",
-		countera_1.operation_mode = "arithmetic",
-		countera_1.sum_lutc_input = "cin",
-		countera_1.synch_mode = "on",
-		countera_1.lpm_type = "cyclone_lcell";
-	cyclone_lcell   countera_2
-	( 
-	.aclr(aclr),
-	.cin(wire_countera_1cout[0:0]),
-	.clk(clock),
-	.combout(),
-	.cout(wire_countera_2cout[0:0]),
-	.dataa(power_modified_counter_values[1]),
-	.datab(power_modified_counter_values[2]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[2:2]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_2.cin_used = "true",
-		countera_2.lut_mask = "6c50",
-		countera_2.operation_mode = "arithmetic",
-		countera_2.sum_lutc_input = "cin",
-		countera_2.synch_mode = "on",
-		countera_2.lpm_type = "cyclone_lcell";
-	cyclone_lcell   countera_3
-	( 
-	.aclr(aclr),
-	.cin(wire_countera_2cout[0:0]),
-	.clk(clock),
-	.combout(),
-	.cout(wire_countera_3cout[0:0]),
-	.dataa(power_modified_counter_values[2]),
-	.datab(power_modified_counter_values[3]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[3:3]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_3.cin_used = "true",
-		countera_3.lut_mask = "6c50",
-		countera_3.operation_mode = "arithmetic",
-		countera_3.sum_lutc_input = "cin",
-		countera_3.synch_mode = "on",
-		countera_3.lpm_type = "cyclone_lcell";
-	cyclone_lcell   countera_4
-	( 
-	.aclr(aclr),
-	.cin(wire_countera_3cout[0:0]),
-	.clk(clock),
-	.combout(),
-	.cout(wire_countera_4cout[0:0]),
-	.dataa(power_modified_counter_values[3]),
-	.datab(power_modified_counter_values[4]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[4:4]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_4.cin_used = "true",
-		countera_4.lut_mask = "6c50",
-		countera_4.operation_mode = "arithmetic",
-		countera_4.sum_lutc_input = "cin",
-		countera_4.synch_mode = "on",
-		countera_4.lpm_type = "cyclone_lcell";
-	cyclone_lcell   countera_5
-	( 
-	.aclr(aclr),
-	.cin(wire_countera_4cout[0:0]),
-	.clk(clock),
-	.combout(),
-	.cout(wire_countera_5cout[0:0]),
-	.dataa(power_modified_counter_values[4]),
-	.datab(power_modified_counter_values[5]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[5:5]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_5.cin_used = "true",
-		countera_5.lut_mask = "6c50",
-		countera_5.operation_mode = "arithmetic",
-		countera_5.sum_lutc_input = "cin",
-		countera_5.synch_mode = "on",
-		countera_5.lpm_type = "cyclone_lcell";
-	cyclone_lcell   countera_6
-	( 
-	.aclr(aclr),
-	.cin(wire_countera_5cout[0:0]),
-	.clk(clock),
-	.combout(),
-	.cout(wire_countera_6cout[0:0]),
-	.dataa(power_modified_counter_values[5]),
-	.datab(power_modified_counter_values[6]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[6:6]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_6.cin_used = "true",
-		countera_6.lut_mask = "6c50",
-		countera_6.operation_mode = "arithmetic",
-		countera_6.sum_lutc_input = "cin",
-		countera_6.synch_mode = "on",
-		countera_6.lpm_type = "cyclone_lcell";
-	cyclone_lcell   countera_7
-	( 
-	.aclr(aclr),
-	.cin(wire_countera_6cout[0:0]),
-	.clk(clock),
-	.combout(),
-	.cout(wire_countera_7cout[0:0]),
-	.dataa(power_modified_counter_values[6]),
-	.datab(power_modified_counter_values[7]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[7:7]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_7.cin_used = "true",
-		countera_7.lut_mask = "6c50",
-		countera_7.operation_mode = "arithmetic",
-		countera_7.sum_lutc_input = "cin",
-		countera_7.synch_mode = "on",
-		countera_7.lpm_type = "cyclone_lcell";
-	cyclone_lcell   countera_8
-	( 
-	.aclr(aclr),
-	.cin(wire_countera_7cout[0:0]),
-	.clk(clock),
-	.combout(),
-	.cout(wire_countera_8cout[0:0]),
-	.dataa(power_modified_counter_values[7]),
-	.datab(power_modified_counter_values[8]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[8:8]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_8.cin_used = "true",
-		countera_8.lut_mask = "6c50",
-		countera_8.operation_mode = "arithmetic",
-		countera_8.sum_lutc_input = "cin",
-		countera_8.synch_mode = "on",
-		countera_8.lpm_type = "cyclone_lcell";
-	cyclone_lcell   countera_9
-	( 
-	.aclr(aclr),
-	.cin(wire_countera_8cout[0:0]),
-	.clk(clock),
-	.combout(),
-	.cout(wire_countera_9cout[0:0]),
-	.dataa(power_modified_counter_values[8]),
-	.datab(power_modified_counter_values[9]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[9:9]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_9.cin_used = "true",
-		countera_9.lut_mask = "6c50",
-		countera_9.operation_mode = "arithmetic",
-		countera_9.sum_lutc_input = "cin",
-		countera_9.synch_mode = "on",
-		countera_9.lpm_type = "cyclone_lcell";
-	cyclone_lcell   countera_10
-	( 
-	.aclr(aclr),
-	.cin(wire_countera_9cout[0:0]),
-	.clk(clock),
-	.combout(),
-	.cout(),
-	.dataa(power_modified_counter_values[10]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[10:10]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datab(1'b1),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_10.cin_used = "true",
-		countera_10.lut_mask = "5a5a",
-		countera_10.operation_mode = "normal",
-		countera_10.sum_lutc_input = "cin",
-		countera_10.synch_mode = "on",
-		countera_10.lpm_type = "cyclone_lcell";
-	cyclone_lcell   parity
-	( 
-	.aclr(aclr),
-	.cin(updown),
-	.clk(clock),
-	.combout(),
-	.cout(wire_parity_cout),
-	.dataa(cnt_en),
-	.datab((~ wire_parity_regout)),
-	.ena(1'b1),
-	.regout(wire_parity_regout),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		parity.cin_used = "true",
-		parity.lut_mask = "9982",
-		parity.operation_mode = "arithmetic",
-		parity.synch_mode = "on",
-		parity.lpm_type = "cyclone_lcell";
-	assign
-		power_modified_counter_values = {wire_countera_regout[10:1], (~ wire_countera_regout[0])},
-		q = power_modified_counter_values,
-		sclr = 1'b0,
-		updown = 1'b1;
-endmodule //fifo_2k_a_graycounter_2r6
-
-
-//altsyncram ADDRESS_REG_B="CLOCK1" DEVICE_FAMILY="Cyclone" OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" WIDTH_A=16 WIDTH_B=16 WIDTH_BYTEENA_A=1 WIDTHAD_A=11 WIDTHAD_B=11 address_a address_b clock0 clock1 clocken1 data_a q_b wren_a
-//VERSION_BEGIN 5.0 cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END
-
-//synthesis_resources = M4K 8 
-//synopsys translate_off
-`timescale 1 ps / 1 ps
-//synopsys translate_on
-module  fifo_2k_altsyncram_6pl
-	( 
-	address_a,
-	address_b,
-	clock0,
-	clock1,
-	clocken1,
-	data_a,
-	q_b,
-	wren_a) /* synthesis synthesis_clearbox=1 */;
-	input   [10:0]  address_a;
-	input   [10:0]  address_b;
-	input   clock0;
-	input   clock1;
-	input   clocken1;
-	input   [15:0]  data_a;
-	output   [15:0]  q_b;
-	input   wren_a;
-
-	wire  [0:0]   wire_ram_block3a_0portbdataout;
-	wire  [0:0]   wire_ram_block3a_1portbdataout;
-	wire  [0:0]   wire_ram_block3a_2portbdataout;
-	wire  [0:0]   wire_ram_block3a_3portbdataout;
-	wire  [0:0]   wire_ram_block3a_4portbdataout;
-	wire  [0:0]   wire_ram_block3a_5portbdataout;
-	wire  [0:0]   wire_ram_block3a_6portbdataout;
-	wire  [0:0]   wire_ram_block3a_7portbdataout;
-	wire  [0:0]   wire_ram_block3a_8portbdataout;
-	wire  [0:0]   wire_ram_block3a_9portbdataout;
-	wire  [0:0]   wire_ram_block3a_10portbdataout;
-	wire  [0:0]   wire_ram_block3a_11portbdataout;
-	wire  [0:0]   wire_ram_block3a_12portbdataout;
-	wire  [0:0]   wire_ram_block3a_13portbdataout;
-	wire  [0:0]   wire_ram_block3a_14portbdataout;
-	wire  [0:0]   wire_ram_block3a_15portbdataout;
-	wire  [10:0]  address_a_wire;
-	wire  [10:0]  address_b_wire;
-
-	cyclone_ram_block   ram_block3a_0
-	( 
-	.clk0(clock0),
-	.clk1(clock1),
-	.ena0(wren_a),
-	.ena1(clocken1),
-	.portaaddr({address_a_wire[10:0]}),
-	.portadatain({data_a[0]}),
-	.portadataout(),
-	.portawe(1'b1),
-	.portbaddr({address_b_wire[10:0]}),
-	.portbdataout(wire_ram_block3a_0portbdataout[0:0]),
-	.portbrewe(1'b1)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.clr0(1'b0),
-	.clr1(1'b0),
-	.portabyteenamasks(1'b1),
-	.portbbyteenamasks(1'b1),
-	.portbdatain(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		ram_block3a_0.connectivity_checking = "OFF",
-		ram_block3a_0.logical_ram_name = "ALTSYNCRAM",
-		ram_block3a_0.mixed_port_feed_through_mode = "dont_care",
-		ram_block3a_0.operation_mode = "dual_port",
-		ram_block3a_0.port_a_address_width = 11,
-		ram_block3a_0.port_a_data_width = 1,
-		ram_block3a_0.port_a_first_address = 0,
-		ram_block3a_0.port_a_first_bit_number = 0,
-		ram_block3a_0.port_a_last_address = 2047,
-		ram_block3a_0.port_a_logical_ram_depth = 2048,
-		ram_block3a_0.port_a_logical_ram_width = 16,
-		ram_block3a_0.port_b_address_clear = "none",
-		ram_block3a_0.port_b_address_clock = "clock1",
-		ram_block3a_0.port_b_address_width = 11,
-		ram_block3a_0.port_b_data_out_clear = "none",
-		ram_block3a_0.port_b_data_out_clock = "none",
-		ram_block3a_0.port_b_data_width = 1,
-		ram_block3a_0.port_b_first_address = 0,
-		ram_block3a_0.port_b_first_bit_number = 0,
-		ram_block3a_0.port_b_last_address = 2047,
-		ram_block3a_0.port_b_logical_ram_depth = 2048,
-		ram_block3a_0.port_b_logical_ram_width = 16,
-		ram_block3a_0.port_b_read_enable_write_enable_clock = "clock1",
-		ram_block3a_0.ram_block_type = "auto",
-		ram_block3a_0.lpm_type = "cyclone_ram_block";
-	cyclone_ram_block   ram_block3a_1
-	( 
-	.clk0(clock0),
-	.clk1(clock1),
-	.ena0(wren_a),
-	.ena1(clocken1),
-	.portaaddr({address_a_wire[10:0]}),
-	.portadatain({data_a[1]}),
-	.portadataout(),
-	.portawe(1'b1),
-	.portbaddr({address_b_wire[10:0]}),
-	.portbdataout(wire_ram_block3a_1portbdataout[0:0]),
-	.portbrewe(1'b1)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.clr0(1'b0),
-	.clr1(1'b0),
-	.portabyteenamasks(1'b1),
-	.portbbyteenamasks(1'b1),
-	.portbdatain(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		ram_block3a_1.connectivity_checking = "OFF",
-		ram_block3a_1.logical_ram_name = "ALTSYNCRAM",
-		ram_block3a_1.mixed_port_feed_through_mode = "dont_care",
-		ram_block3a_1.operation_mode = "dual_port",
-		ram_block3a_1.port_a_address_width = 11,
-		ram_block3a_1.port_a_data_width = 1,
-		ram_block3a_1.port_a_first_address = 0,
-		ram_block3a_1.port_a_first_bit_number = 1,
-		ram_block3a_1.port_a_last_address = 2047,
-		ram_block3a_1.port_a_logical_ram_depth = 2048,
-		ram_block3a_1.port_a_logical_ram_width = 16,
-		ram_block3a_1.port_b_address_clear = "none",
-		ram_block3a_1.port_b_address_clock = "clock1",
-		ram_block3a_1.port_b_address_width = 11,
-		ram_block3a_1.port_b_data_out_clear = "none",
-		ram_block3a_1.port_b_data_out_clock = "none",
-		ram_block3a_1.port_b_data_width = 1,
-		ram_block3a_1.port_b_first_address = 0,
-		ram_block3a_1.port_b_first_bit_number = 1,
-		ram_block3a_1.port_b_last_address = 2047,
-		ram_block3a_1.port_b_logical_ram_depth = 2048,
-		ram_block3a_1.port_b_logical_ram_width = 16,
-		ram_block3a_1.port_b_read_enable_write_enable_clock = "clock1",
-		ram_block3a_1.ram_block_type = "auto",
-		ram_block3a_1.lpm_type = "cyclone_ram_block";
-	cyclone_ram_block   ram_block3a_2
-	( 
-	.clk0(clock0),
-	.clk1(clock1),
-	.ena0(wren_a),
-	.ena1(clocken1),
-	.portaaddr({address_a_wire[10:0]}),
-	.portadatain({data_a[2]}),
-	.portadataout(),
-	.portawe(1'b1),
-	.portbaddr({address_b_wire[10:0]}),
-	.portbdataout(wire_ram_block3a_2portbdataout[0:0]),
-	.portbrewe(1'b1)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.clr0(1'b0),
-	.clr1(1'b0),
-	.portabyteenamasks(1'b1),
-	.portbbyteenamasks(1'b1),
-	.portbdatain(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		ram_block3a_2.connectivity_checking = "OFF",
-		ram_block3a_2.logical_ram_name = "ALTSYNCRAM",
-		ram_block3a_2.mixed_port_feed_through_mode = "dont_care",
-		ram_block3a_2.operation_mode = "dual_port",
-		ram_block3a_2.port_a_address_width = 11,
-		ram_block3a_2.port_a_data_width = 1,
-		ram_block3a_2.port_a_first_address = 0,
-		ram_block3a_2.port_a_first_bit_number = 2,
-		ram_block3a_2.port_a_last_address = 2047,
-		ram_block3a_2.port_a_logical_ram_depth = 2048,
-		ram_block3a_2.port_a_logical_ram_width = 16,
-		ram_block3a_2.port_b_address_clear = "none",
-		ram_block3a_2.port_b_address_clock = "clock1",
-		ram_block3a_2.port_b_address_width = 11,
-		ram_block3a_2.port_b_data_out_clear = "none",
-		ram_block3a_2.port_b_data_out_clock = "none",
-		ram_block3a_2.port_b_data_width = 1,
-		ram_block3a_2.port_b_first_address = 0,
-		ram_block3a_2.port_b_first_bit_number = 2,
-		ram_block3a_2.port_b_last_address = 2047,
-		ram_block3a_2.port_b_logical_ram_depth = 2048,
-		ram_block3a_2.port_b_logical_ram_width = 16,
-		ram_block3a_2.port_b_read_enable_write_enable_clock = "clock1",
-		ram_block3a_2.ram_block_type = "auto",
-		ram_block3a_2.lpm_type = "cyclone_ram_block";
-	cyclone_ram_block   ram_block3a_3
-	( 
-	.clk0(clock0),
-	.clk1(clock1),
-	.ena0(wren_a),
-	.ena1(clocken1),
-	.portaaddr({address_a_wire[10:0]}),
-	.portadatain({data_a[3]}),
-	.portadataout(),
-	.portawe(1'b1),
-	.portbaddr({address_b_wire[10:0]}),
-	.portbdataout(wire_ram_block3a_3portbdataout[0:0]),
-	.portbrewe(1'b1)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.clr0(1'b0),
-	.clr1(1'b0),
-	.portabyteenamasks(1'b1),
-	.portbbyteenamasks(1'b1),
-	.portbdatain(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		ram_block3a_3.connectivity_checking = "OFF",
-		ram_block3a_3.logical_ram_name = "ALTSYNCRAM",
-		ram_block3a_3.mixed_port_feed_through_mode = "dont_care",
-		ram_block3a_3.operation_mode = "dual_port",
-		ram_block3a_3.port_a_address_width = 11,
-		ram_block3a_3.port_a_data_width = 1,
-		ram_block3a_3.port_a_first_address = 0,
-		ram_block3a_3.port_a_first_bit_number = 3,
-		ram_block3a_3.port_a_last_address = 2047,
-		ram_block3a_3.port_a_logical_ram_depth = 2048,
-		ram_block3a_3.port_a_logical_ram_width = 16,
-		ram_block3a_3.port_b_address_clear = "none",
-		ram_block3a_3.port_b_address_clock = "clock1",
-		ram_block3a_3.port_b_address_width = 11,
-		ram_block3a_3.port_b_data_out_clear = "none",
-		ram_block3a_3.port_b_data_out_clock = "none",
-		ram_block3a_3.port_b_data_width = 1,
-		ram_block3a_3.port_b_first_address = 0,
-		ram_block3a_3.port_b_first_bit_number = 3,
-		ram_block3a_3.port_b_last_address = 2047,
-		ram_block3a_3.port_b_logical_ram_depth = 2048,
-		ram_block3a_3.port_b_logical_ram_width = 16,
-		ram_block3a_3.port_b_read_enable_write_enable_clock = "clock1",
-		ram_block3a_3.ram_block_type = "auto",
-		ram_block3a_3.lpm_type = "cyclone_ram_block";
-	cyclone_ram_block   ram_block3a_4
-	( 
-	.clk0(clock0),
-	.clk1(clock1),
-	.ena0(wren_a),
-	.ena1(clocken1),
-	.portaaddr({address_a_wire[10:0]}),
-	.portadatain({data_a[4]}),
-	.portadataout(),
-	.portawe(1'b1),
-	.portbaddr({address_b_wire[10:0]}),
-	.portbdataout(wire_ram_block3a_4portbdataout[0:0]),
-	.portbrewe(1'b1)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.clr0(1'b0),
-	.clr1(1'b0),
-	.portabyteenamasks(1'b1),
-	.portbbyteenamasks(1'b1),
-	.portbdatain(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		ram_block3a_4.connectivity_checking = "OFF",
-		ram_block3a_4.logical_ram_name = "ALTSYNCRAM",
-		ram_block3a_4.mixed_port_feed_through_mode = "dont_care",
-		ram_block3a_4.operation_mode = "dual_port",
-		ram_block3a_4.port_a_address_width = 11,
-		ram_block3a_4.port_a_data_width = 1,
-		ram_block3a_4.port_a_first_address = 0,
-		ram_block3a_4.port_a_first_bit_number = 4,
-		ram_block3a_4.port_a_last_address = 2047,
-		ram_block3a_4.port_a_logical_ram_depth = 2048,
-		ram_block3a_4.port_a_logical_ram_width = 16,
-		ram_block3a_4.port_b_address_clear = "none",
-		ram_block3a_4.port_b_address_clock = "clock1",
-		ram_block3a_4.port_b_address_width = 11,
-		ram_block3a_4.port_b_data_out_clear = "none",
-		ram_block3a_4.port_b_data_out_clock = "none",
-		ram_block3a_4.port_b_data_width = 1,
-		ram_block3a_4.port_b_first_address = 0,
-		ram_block3a_4.port_b_first_bit_number = 4,
-		ram_block3a_4.port_b_last_address = 2047,
-		ram_block3a_4.port_b_logical_ram_depth = 2048,
-		ram_block3a_4.port_b_logical_ram_width = 16,
-		ram_block3a_4.port_b_read_enable_write_enable_clock = "clock1",
-		ram_block3a_4.ram_block_type = "auto",
-		ram_block3a_4.lpm_type = "cyclone_ram_block";
-	cyclone_ram_block   ram_block3a_5
-	( 
-	.clk0(clock0),
-	.clk1(clock1),
-	.ena0(wren_a),
-	.ena1(clocken1),
-	.portaaddr({address_a_wire[10:0]}),
-	.portadatain({data_a[5]}),
-	.portadataout(),
-	.portawe(1'b1),
-	.portbaddr({address_b_wire[10:0]}),
-	.portbdataout(wire_ram_block3a_5portbdataout[0:0]),
-	.portbrewe(1'b1)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.clr0(1'b0),
-	.clr1(1'b0),
-	.portabyteenamasks(1'b1),
-	.portbbyteenamasks(1'b1),
-	.portbdatain(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		ram_block3a_5.connectivity_checking = "OFF",
-		ram_block3a_5.logical_ram_name = "ALTSYNCRAM",
-		ram_block3a_5.mixed_port_feed_through_mode = "dont_care",
-		ram_block3a_5.operation_mode = "dual_port",
-		ram_block3a_5.port_a_address_width = 11,
-		ram_block3a_5.port_a_data_width = 1,
-		ram_block3a_5.port_a_first_address = 0,
-		ram_block3a_5.port_a_first_bit_number = 5,
-		ram_block3a_5.port_a_last_address = 2047,
-		ram_block3a_5.port_a_logical_ram_depth = 2048,
-		ram_block3a_5.port_a_logical_ram_width = 16,
-		ram_block3a_5.port_b_address_clear = "none",
-		ram_block3a_5.port_b_address_clock = "clock1",
-		ram_block3a_5.port_b_address_width = 11,
-		ram_block3a_5.port_b_data_out_clear = "none",
-		ram_block3a_5.port_b_data_out_clock = "none",
-		ram_block3a_5.port_b_data_width = 1,
-		ram_block3a_5.port_b_first_address = 0,
-		ram_block3a_5.port_b_first_bit_number = 5,
-		ram_block3a_5.port_b_last_address = 2047,
-		ram_block3a_5.port_b_logical_ram_depth = 2048,
-		ram_block3a_5.port_b_logical_ram_width = 16,
-		ram_block3a_5.port_b_read_enable_write_enable_clock = "clock1",
-		ram_block3a_5.ram_block_type = "auto",
-		ram_block3a_5.lpm_type = "cyclone_ram_block";
-	cyclone_ram_block   ram_block3a_6
-	( 
-	.clk0(clock0),
-	.clk1(clock1),
-	.ena0(wren_a),
-	.ena1(clocken1),
-	.portaaddr({address_a_wire[10:0]}),
-	.portadatain({data_a[6]}),
-	.portadataout(),
-	.portawe(1'b1),
-	.portbaddr({address_b_wire[10:0]}),
-	.portbdataout(wire_ram_block3a_6portbdataout[0:0]),
-	.portbrewe(1'b1)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.clr0(1'b0),
-	.clr1(1'b0),
-	.portabyteenamasks(1'b1),
-	.portbbyteenamasks(1'b1),
-	.portbdatain(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		ram_block3a_6.connectivity_checking = "OFF",
-		ram_block3a_6.logical_ram_name = "ALTSYNCRAM",
-		ram_block3a_6.mixed_port_feed_through_mode = "dont_care",
-		ram_block3a_6.operation_mode = "dual_port",
-		ram_block3a_6.port_a_address_width = 11,
-		ram_block3a_6.port_a_data_width = 1,
-		ram_block3a_6.port_a_first_address = 0,
-		ram_block3a_6.port_a_first_bit_number = 6,
-		ram_block3a_6.port_a_last_address = 2047,
-		ram_block3a_6.port_a_logical_ram_depth = 2048,
-		ram_block3a_6.port_a_logical_ram_width = 16,
-		ram_block3a_6.port_b_address_clear = "none",
-		ram_block3a_6.port_b_address_clock = "clock1",
-		ram_block3a_6.port_b_address_width = 11,
-		ram_block3a_6.port_b_data_out_clear = "none",
-		ram_block3a_6.port_b_data_out_clock = "none",
-		ram_block3a_6.port_b_data_width = 1,
-		ram_block3a_6.port_b_first_address = 0,
-		ram_block3a_6.port_b_first_bit_number = 6,
-		ram_block3a_6.port_b_last_address = 2047,
-		ram_block3a_6.port_b_logical_ram_depth = 2048,
-		ram_block3a_6.port_b_logical_ram_width = 16,
-		ram_block3a_6.port_b_read_enable_write_enable_clock = "clock1",
-		ram_block3a_6.ram_block_type = "auto",
-		ram_block3a_6.lpm_type = "cyclone_ram_block";
-	cyclone_ram_block   ram_block3a_7
-	( 
-	.clk0(clock0),
-	.clk1(clock1),
-	.ena0(wren_a),
-	.ena1(clocken1),
-	.portaaddr({address_a_wire[10:0]}),
-	.portadatain({data_a[7]}),
-	.portadataout(),
-	.portawe(1'b1),
-	.portbaddr({address_b_wire[10:0]}),
-	.portbdataout(wire_ram_block3a_7portbdataout[0:0]),
-	.portbrewe(1'b1)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.clr0(1'b0),
-	.clr1(1'b0),
-	.portabyteenamasks(1'b1),
-	.portbbyteenamasks(1'b1),
-	.portbdatain(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		ram_block3a_7.connectivity_checking = "OFF",
-		ram_block3a_7.logical_ram_name = "ALTSYNCRAM",
-		ram_block3a_7.mixed_port_feed_through_mode = "dont_care",
-		ram_block3a_7.operation_mode = "dual_port",
-		ram_block3a_7.port_a_address_width = 11,
-		ram_block3a_7.port_a_data_width = 1,
-		ram_block3a_7.port_a_first_address = 0,
-		ram_block3a_7.port_a_first_bit_number = 7,
-		ram_block3a_7.port_a_last_address = 2047,
-		ram_block3a_7.port_a_logical_ram_depth = 2048,
-		ram_block3a_7.port_a_logical_ram_width = 16,
-		ram_block3a_7.port_b_address_clear = "none",
-		ram_block3a_7.port_b_address_clock = "clock1",
-		ram_block3a_7.port_b_address_width = 11,
-		ram_block3a_7.port_b_data_out_clear = "none",
-		ram_block3a_7.port_b_data_out_clock = "none",
-		ram_block3a_7.port_b_data_width = 1,
-		ram_block3a_7.port_b_first_address = 0,
-		ram_block3a_7.port_b_first_bit_number = 7,
-		ram_block3a_7.port_b_last_address = 2047,
-		ram_block3a_7.port_b_logical_ram_depth = 2048,
-		ram_block3a_7.port_b_logical_ram_width = 16,
-		ram_block3a_7.port_b_read_enable_write_enable_clock = "clock1",
-		ram_block3a_7.ram_block_type = "auto",
-		ram_block3a_7.lpm_type = "cyclone_ram_block";
-	cyclone_ram_block   ram_block3a_8
-	( 
-	.clk0(clock0),
-	.clk1(clock1),
-	.ena0(wren_a),
-	.ena1(clocken1),
-	.portaaddr({address_a_wire[10:0]}),
-	.portadatain({data_a[8]}),
-	.portadataout(),
-	.portawe(1'b1),
-	.portbaddr({address_b_wire[10:0]}),
-	.portbdataout(wire_ram_block3a_8portbdataout[0:0]),
-	.portbrewe(1'b1)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.clr0(1'b0),
-	.clr1(1'b0),
-	.portabyteenamasks(1'b1),
-	.portbbyteenamasks(1'b1),
-	.portbdatain(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		ram_block3a_8.connectivity_checking = "OFF",
-		ram_block3a_8.logical_ram_name = "ALTSYNCRAM",
-		ram_block3a_8.mixed_port_feed_through_mode = "dont_care",
-		ram_block3a_8.operation_mode = "dual_port",
-		ram_block3a_8.port_a_address_width = 11,
-		ram_block3a_8.port_a_data_width = 1,
-		ram_block3a_8.port_a_first_address = 0,
-		ram_block3a_8.port_a_first_bit_number = 8,
-		ram_block3a_8.port_a_last_address = 2047,
-		ram_block3a_8.port_a_logical_ram_depth = 2048,
-		ram_block3a_8.port_a_logical_ram_width = 16,
-		ram_block3a_8.port_b_address_clear = "none",
-		ram_block3a_8.port_b_address_clock = "clock1",
-		ram_block3a_8.port_b_address_width = 11,
-		ram_block3a_8.port_b_data_out_clear = "none",
-		ram_block3a_8.port_b_data_out_clock = "none",
-		ram_block3a_8.port_b_data_width = 1,
-		ram_block3a_8.port_b_first_address = 0,
-		ram_block3a_8.port_b_first_bit_number = 8,
-		ram_block3a_8.port_b_last_address = 2047,
-		ram_block3a_8.port_b_logical_ram_depth = 2048,
-		ram_block3a_8.port_b_logical_ram_width = 16,
-		ram_block3a_8.port_b_read_enable_write_enable_clock = "clock1",
-		ram_block3a_8.ram_block_type = "auto",
-		ram_block3a_8.lpm_type = "cyclone_ram_block";
-	cyclone_ram_block   ram_block3a_9
-	( 
-	.clk0(clock0),
-	.clk1(clock1),
-	.ena0(wren_a),
-	.ena1(clocken1),
-	.portaaddr({address_a_wire[10:0]}),
-	.portadatain({data_a[9]}),
-	.portadataout(),
-	.portawe(1'b1),
-	.portbaddr({address_b_wire[10:0]}),
-	.portbdataout(wire_ram_block3a_9portbdataout[0:0]),
-	.portbrewe(1'b1)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.clr0(1'b0),
-	.clr1(1'b0),
-	.portabyteenamasks(1'b1),
-	.portbbyteenamasks(1'b1),
-	.portbdatain(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		ram_block3a_9.connectivity_checking = "OFF",
-		ram_block3a_9.logical_ram_name = "ALTSYNCRAM",
-		ram_block3a_9.mixed_port_feed_through_mode = "dont_care",
-		ram_block3a_9.operation_mode = "dual_port",
-		ram_block3a_9.port_a_address_width = 11,
-		ram_block3a_9.port_a_data_width = 1,
-		ram_block3a_9.port_a_first_address = 0,
-		ram_block3a_9.port_a_first_bit_number = 9,
-		ram_block3a_9.port_a_last_address = 2047,
-		ram_block3a_9.port_a_logical_ram_depth = 2048,
-		ram_block3a_9.port_a_logical_ram_width = 16,
-		ram_block3a_9.port_b_address_clear = "none",
-		ram_block3a_9.port_b_address_clock = "clock1",
-		ram_block3a_9.port_b_address_width = 11,
-		ram_block3a_9.port_b_data_out_clear = "none",
-		ram_block3a_9.port_b_data_out_clock = "none",
-		ram_block3a_9.port_b_data_width = 1,
-		ram_block3a_9.port_b_first_address = 0,
-		ram_block3a_9.port_b_first_bit_number = 9,
-		ram_block3a_9.port_b_last_address = 2047,
-		ram_block3a_9.port_b_logical_ram_depth = 2048,
-		ram_block3a_9.port_b_logical_ram_width = 16,
-		ram_block3a_9.port_b_read_enable_write_enable_clock = "clock1",
-		ram_block3a_9.ram_block_type = "auto",
-		ram_block3a_9.lpm_type = "cyclone_ram_block";
-	cyclone_ram_block   ram_block3a_10
-	( 
-	.clk0(clock0),
-	.clk1(clock1),
-	.ena0(wren_a),
-	.ena1(clocken1),
-	.portaaddr({address_a_wire[10:0]}),
-	.portadatain({data_a[10]}),
-	.portadataout(),
-	.portawe(1'b1),
-	.portbaddr({address_b_wire[10:0]}),
-	.portbdataout(wire_ram_block3a_10portbdataout[0:0]),
-	.portbrewe(1'b1)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.clr0(1'b0),
-	.clr1(1'b0),
-	.portabyteenamasks(1'b1),
-	.portbbyteenamasks(1'b1),
-	.portbdatain(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		ram_block3a_10.connectivity_checking = "OFF",
-		ram_block3a_10.logical_ram_name = "ALTSYNCRAM",
-		ram_block3a_10.mixed_port_feed_through_mode = "dont_care",
-		ram_block3a_10.operation_mode = "dual_port",
-		ram_block3a_10.port_a_address_width = 11,
-		ram_block3a_10.port_a_data_width = 1,
-		ram_block3a_10.port_a_first_address = 0,
-		ram_block3a_10.port_a_first_bit_number = 10,
-		ram_block3a_10.port_a_last_address = 2047,
-		ram_block3a_10.port_a_logical_ram_depth = 2048,
-		ram_block3a_10.port_a_logical_ram_width = 16,
-		ram_block3a_10.port_b_address_clear = "none",
-		ram_block3a_10.port_b_address_clock = "clock1",
-		ram_block3a_10.port_b_address_width = 11,
-		ram_block3a_10.port_b_data_out_clear = "none",
-		ram_block3a_10.port_b_data_out_clock = "none",
-		ram_block3a_10.port_b_data_width = 1,
-		ram_block3a_10.port_b_first_address = 0,
-		ram_block3a_10.port_b_first_bit_number = 10,
-		ram_block3a_10.port_b_last_address = 2047,
-		ram_block3a_10.port_b_logical_ram_depth = 2048,
-		ram_block3a_10.port_b_logical_ram_width = 16,
-		ram_block3a_10.port_b_read_enable_write_enable_clock = "clock1",
-		ram_block3a_10.ram_block_type = "auto",
-		ram_block3a_10.lpm_type = "cyclone_ram_block";
-	cyclone_ram_block   ram_block3a_11
-	( 
-	.clk0(clock0),
-	.clk1(clock1),
-	.ena0(wren_a),
-	.ena1(clocken1),
-	.portaaddr({address_a_wire[10:0]}),
-	.portadatain({data_a[11]}),
-	.portadataout(),
-	.portawe(1'b1),
-	.portbaddr({address_b_wire[10:0]}),
-	.portbdataout(wire_ram_block3a_11portbdataout[0:0]),
-	.portbrewe(1'b1)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.clr0(1'b0),
-	.clr1(1'b0),
-	.portabyteenamasks(1'b1),
-	.portbbyteenamasks(1'b1),
-	.portbdatain(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		ram_block3a_11.connectivity_checking = "OFF",
-		ram_block3a_11.logical_ram_name = "ALTSYNCRAM",
-		ram_block3a_11.mixed_port_feed_through_mode = "dont_care",
-		ram_block3a_11.operation_mode = "dual_port",
-		ram_block3a_11.port_a_address_width = 11,
-		ram_block3a_11.port_a_data_width = 1,
-		ram_block3a_11.port_a_first_address = 0,
-		ram_block3a_11.port_a_first_bit_number = 11,
-		ram_block3a_11.port_a_last_address = 2047,
-		ram_block3a_11.port_a_logical_ram_depth = 2048,
-		ram_block3a_11.port_a_logical_ram_width = 16,
-		ram_block3a_11.port_b_address_clear = "none",
-		ram_block3a_11.port_b_address_clock = "clock1",
-		ram_block3a_11.port_b_address_width = 11,
-		ram_block3a_11.port_b_data_out_clear = "none",
-		ram_block3a_11.port_b_data_out_clock = "none",
-		ram_block3a_11.port_b_data_width = 1,
-		ram_block3a_11.port_b_first_address = 0,
-		ram_block3a_11.port_b_first_bit_number = 11,
-		ram_block3a_11.port_b_last_address = 2047,
-		ram_block3a_11.port_b_logical_ram_depth = 2048,
-		ram_block3a_11.port_b_logical_ram_width = 16,
-		ram_block3a_11.port_b_read_enable_write_enable_clock = "clock1",
-		ram_block3a_11.ram_block_type = "auto",
-		ram_block3a_11.lpm_type = "cyclone_ram_block";
-	cyclone_ram_block   ram_block3a_12
-	( 
-	.clk0(clock0),
-	.clk1(clock1),
-	.ena0(wren_a),
-	.ena1(clocken1),
-	.portaaddr({address_a_wire[10:0]}),
-	.portadatain({data_a[12]}),
-	.portadataout(),
-	.portawe(1'b1),
-	.portbaddr({address_b_wire[10:0]}),
-	.portbdataout(wire_ram_block3a_12portbdataout[0:0]),
-	.portbrewe(1'b1)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.clr0(1'b0),
-	.clr1(1'b0),
-	.portabyteenamasks(1'b1),
-	.portbbyteenamasks(1'b1),
-	.portbdatain(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		ram_block3a_12.connectivity_checking = "OFF",
-		ram_block3a_12.logical_ram_name = "ALTSYNCRAM",
-		ram_block3a_12.mixed_port_feed_through_mode = "dont_care",
-		ram_block3a_12.operation_mode = "dual_port",
-		ram_block3a_12.port_a_address_width = 11,
-		ram_block3a_12.port_a_data_width = 1,
-		ram_block3a_12.port_a_first_address = 0,
-		ram_block3a_12.port_a_first_bit_number = 12,
-		ram_block3a_12.port_a_last_address = 2047,
-		ram_block3a_12.port_a_logical_ram_depth = 2048,
-		ram_block3a_12.port_a_logical_ram_width = 16,
-		ram_block3a_12.port_b_address_clear = "none",
-		ram_block3a_12.port_b_address_clock = "clock1",
-		ram_block3a_12.port_b_address_width = 11,
-		ram_block3a_12.port_b_data_out_clear = "none",
-		ram_block3a_12.port_b_data_out_clock = "none",
-		ram_block3a_12.port_b_data_width = 1,
-		ram_block3a_12.port_b_first_address = 0,
-		ram_block3a_12.port_b_first_bit_number = 12,
-		ram_block3a_12.port_b_last_address = 2047,
-		ram_block3a_12.port_b_logical_ram_depth = 2048,
-		ram_block3a_12.port_b_logical_ram_width = 16,
-		ram_block3a_12.port_b_read_enable_write_enable_clock = "clock1",
-		ram_block3a_12.ram_block_type = "auto",
-		ram_block3a_12.lpm_type = "cyclone_ram_block";
-	cyclone_ram_block   ram_block3a_13
-	( 
-	.clk0(clock0),
-	.clk1(clock1),
-	.ena0(wren_a),
-	.ena1(clocken1),
-	.portaaddr({address_a_wire[10:0]}),
-	.portadatain({data_a[13]}),
-	.portadataout(),
-	.portawe(1'b1),
-	.portbaddr({address_b_wire[10:0]}),
-	.portbdataout(wire_ram_block3a_13portbdataout[0:0]),
-	.portbrewe(1'b1)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.clr0(1'b0),
-	.clr1(1'b0),
-	.portabyteenamasks(1'b1),
-	.portbbyteenamasks(1'b1),
-	.portbdatain(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		ram_block3a_13.connectivity_checking = "OFF",
-		ram_block3a_13.logical_ram_name = "ALTSYNCRAM",
-		ram_block3a_13.mixed_port_feed_through_mode = "dont_care",
-		ram_block3a_13.operation_mode = "dual_port",
-		ram_block3a_13.port_a_address_width = 11,
-		ram_block3a_13.port_a_data_width = 1,
-		ram_block3a_13.port_a_first_address = 0,
-		ram_block3a_13.port_a_first_bit_number = 13,
-		ram_block3a_13.port_a_last_address = 2047,
-		ram_block3a_13.port_a_logical_ram_depth = 2048,
-		ram_block3a_13.port_a_logical_ram_width = 16,
-		ram_block3a_13.port_b_address_clear = "none",
-		ram_block3a_13.port_b_address_clock = "clock1",
-		ram_block3a_13.port_b_address_width = 11,
-		ram_block3a_13.port_b_data_out_clear = "none",
-		ram_block3a_13.port_b_data_out_clock = "none",
-		ram_block3a_13.port_b_data_width = 1,
-		ram_block3a_13.port_b_first_address = 0,
-		ram_block3a_13.port_b_first_bit_number = 13,
-		ram_block3a_13.port_b_last_address = 2047,
-		ram_block3a_13.port_b_logical_ram_depth = 2048,
-		ram_block3a_13.port_b_logical_ram_width = 16,
-		ram_block3a_13.port_b_read_enable_write_enable_clock = "clock1",
-		ram_block3a_13.ram_block_type = "auto",
-		ram_block3a_13.lpm_type = "cyclone_ram_block";
-	cyclone_ram_block   ram_block3a_14
-	( 
-	.clk0(clock0),
-	.clk1(clock1),
-	.ena0(wren_a),
-	.ena1(clocken1),
-	.portaaddr({address_a_wire[10:0]}),
-	.portadatain({data_a[14]}),
-	.portadataout(),
-	.portawe(1'b1),
-	.portbaddr({address_b_wire[10:0]}),
-	.portbdataout(wire_ram_block3a_14portbdataout[0:0]),
-	.portbrewe(1'b1)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.clr0(1'b0),
-	.clr1(1'b0),
-	.portabyteenamasks(1'b1),
-	.portbbyteenamasks(1'b1),
-	.portbdatain(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		ram_block3a_14.connectivity_checking = "OFF",
-		ram_block3a_14.logical_ram_name = "ALTSYNCRAM",
-		ram_block3a_14.mixed_port_feed_through_mode = "dont_care",
-		ram_block3a_14.operation_mode = "dual_port",
-		ram_block3a_14.port_a_address_width = 11,
-		ram_block3a_14.port_a_data_width = 1,
-		ram_block3a_14.port_a_first_address = 0,
-		ram_block3a_14.port_a_first_bit_number = 14,
-		ram_block3a_14.port_a_last_address = 2047,
-		ram_block3a_14.port_a_logical_ram_depth = 2048,
-		ram_block3a_14.port_a_logical_ram_width = 16,
-		ram_block3a_14.port_b_address_clear = "none",
-		ram_block3a_14.port_b_address_clock = "clock1",
-		ram_block3a_14.port_b_address_width = 11,
-		ram_block3a_14.port_b_data_out_clear = "none",
-		ram_block3a_14.port_b_data_out_clock = "none",
-		ram_block3a_14.port_b_data_width = 1,
-		ram_block3a_14.port_b_first_address = 0,
-		ram_block3a_14.port_b_first_bit_number = 14,
-		ram_block3a_14.port_b_last_address = 2047,
-		ram_block3a_14.port_b_logical_ram_depth = 2048,
-		ram_block3a_14.port_b_logical_ram_width = 16,
-		ram_block3a_14.port_b_read_enable_write_enable_clock = "clock1",
-		ram_block3a_14.ram_block_type = "auto",
-		ram_block3a_14.lpm_type = "cyclone_ram_block";
-	cyclone_ram_block   ram_block3a_15
-	( 
-	.clk0(clock0),
-	.clk1(clock1),
-	.ena0(wren_a),
-	.ena1(clocken1),
-	.portaaddr({address_a_wire[10:0]}),
-	.portadatain({data_a[15]}),
-	.portadataout(),
-	.portawe(1'b1),
-	.portbaddr({address_b_wire[10:0]}),
-	.portbdataout(wire_ram_block3a_15portbdataout[0:0]),
-	.portbrewe(1'b1)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.clr0(1'b0),
-	.clr1(1'b0),
-	.portabyteenamasks(1'b1),
-	.portbbyteenamasks(1'b1),
-	.portbdatain(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		ram_block3a_15.connectivity_checking = "OFF",
-		ram_block3a_15.logical_ram_name = "ALTSYNCRAM",
-		ram_block3a_15.mixed_port_feed_through_mode = "dont_care",
-		ram_block3a_15.operation_mode = "dual_port",
-		ram_block3a_15.port_a_address_width = 11,
-		ram_block3a_15.port_a_data_width = 1,
-		ram_block3a_15.port_a_first_address = 0,
-		ram_block3a_15.port_a_first_bit_number = 15,
-		ram_block3a_15.port_a_last_address = 2047,
-		ram_block3a_15.port_a_logical_ram_depth = 2048,
-		ram_block3a_15.port_a_logical_ram_width = 16,
-		ram_block3a_15.port_b_address_clear = "none",
-		ram_block3a_15.port_b_address_clock = "clock1",
-		ram_block3a_15.port_b_address_width = 11,
-		ram_block3a_15.port_b_data_out_clear = "none",
-		ram_block3a_15.port_b_data_out_clock = "none",
-		ram_block3a_15.port_b_data_width = 1,
-		ram_block3a_15.port_b_first_address = 0,
-		ram_block3a_15.port_b_first_bit_number = 15,
-		ram_block3a_15.port_b_last_address = 2047,
-		ram_block3a_15.port_b_logical_ram_depth = 2048,
-		ram_block3a_15.port_b_logical_ram_width = 16,
-		ram_block3a_15.port_b_read_enable_write_enable_clock = "clock1",
-		ram_block3a_15.ram_block_type = "auto",
-		ram_block3a_15.lpm_type = "cyclone_ram_block";
-	assign
-		address_a_wire = address_a,
-		address_b_wire = address_b,
-		q_b = {wire_ram_block3a_15portbdataout[0], wire_ram_block3a_14portbdataout[0], wire_ram_block3a_13portbdataout[0], wire_ram_block3a_12portbdataout[0], wire_ram_block3a_11portbdataout[0], wire_ram_block3a_10portbdataout[0], wire_ram_block3a_9portbdataout[0], wire_ram_block3a_8portbdataout[0], wire_ram_block3a_7portbdataout[0], wire_ram_block3a_6portbdataout[0], wire_ram_block3a_5portbdataout[0], wire_ram_block3a_4portbdataout[0], wire_ram_block3a_3portbdataout[0], wire_ram_block3a_2portbdataout[0], wire_ram_block3a_1portbdataout[0], wire_ram_block3a_0portbdataout[0]};
-endmodule //fifo_2k_altsyncram_6pl
-
-
-//dffpipe DELAY=1 WIDTH=11 clock clrn d q
-//VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END
-
-//synthesis_resources = lut 11 
-//synopsys translate_off
-`timescale 1 ps / 1 ps
-//synopsys translate_on
-module  fifo_2k_dffpipe_ab3
-	( 
-	clock,
-	clrn,
-	d,
-	q) /* synthesis synthesis_clearbox=1 */
-		/* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */;
-	input   clock;
-	input   clrn;
-	input   [10:0]  d;
-	output   [10:0]  q;
-
-	wire	[10:0]	wire_dffe4a_D;
-	reg	[10:0]	dffe4a;
-	wire ena;
-	wire prn;
-	wire sclr;
-
-	// synopsys translate_off
-	initial
-		dffe4a[0:0] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe4a[0:0] <= 1'b1;
-		else if (clrn == 1'b0) dffe4a[0:0] <= 1'b0;
-		else if  (ena == 1'b1)   dffe4a[0:0] <= wire_dffe4a_D[0:0];
-	// synopsys translate_off
-	initial
-		dffe4a[1:1] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe4a[1:1] <= 1'b1;
-		else if (clrn == 1'b0) dffe4a[1:1] <= 1'b0;
-		else if  (ena == 1'b1)   dffe4a[1:1] <= wire_dffe4a_D[1:1];
-	// synopsys translate_off
-	initial
-		dffe4a[2:2] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe4a[2:2] <= 1'b1;
-		else if (clrn == 1'b0) dffe4a[2:2] <= 1'b0;
-		else if  (ena == 1'b1)   dffe4a[2:2] <= wire_dffe4a_D[2:2];
-	// synopsys translate_off
-	initial
-		dffe4a[3:3] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe4a[3:3] <= 1'b1;
-		else if (clrn == 1'b0) dffe4a[3:3] <= 1'b0;
-		else if  (ena == 1'b1)   dffe4a[3:3] <= wire_dffe4a_D[3:3];
-	// synopsys translate_off
-	initial
-		dffe4a[4:4] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe4a[4:4] <= 1'b1;
-		else if (clrn == 1'b0) dffe4a[4:4] <= 1'b0;
-		else if  (ena == 1'b1)   dffe4a[4:4] <= wire_dffe4a_D[4:4];
-	// synopsys translate_off
-	initial
-		dffe4a[5:5] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe4a[5:5] <= 1'b1;
-		else if (clrn == 1'b0) dffe4a[5:5] <= 1'b0;
-		else if  (ena == 1'b1)   dffe4a[5:5] <= wire_dffe4a_D[5:5];
-	// synopsys translate_off
-	initial
-		dffe4a[6:6] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe4a[6:6] <= 1'b1;
-		else if (clrn == 1'b0) dffe4a[6:6] <= 1'b0;
-		else if  (ena == 1'b1)   dffe4a[6:6] <= wire_dffe4a_D[6:6];
-	// synopsys translate_off
-	initial
-		dffe4a[7:7] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe4a[7:7] <= 1'b1;
-		else if (clrn == 1'b0) dffe4a[7:7] <= 1'b0;
-		else if  (ena == 1'b1)   dffe4a[7:7] <= wire_dffe4a_D[7:7];
-	// synopsys translate_off
-	initial
-		dffe4a[8:8] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe4a[8:8] <= 1'b1;
-		else if (clrn == 1'b0) dffe4a[8:8] <= 1'b0;
-		else if  (ena == 1'b1)   dffe4a[8:8] <= wire_dffe4a_D[8:8];
-	// synopsys translate_off
-	initial
-		dffe4a[9:9] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe4a[9:9] <= 1'b1;
-		else if (clrn == 1'b0) dffe4a[9:9] <= 1'b0;
-		else if  (ena == 1'b1)   dffe4a[9:9] <= wire_dffe4a_D[9:9];
-	// synopsys translate_off
-	initial
-		dffe4a[10:10] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe4a[10:10] <= 1'b1;
-		else if (clrn == 1'b0) dffe4a[10:10] <= 1'b0;
-		else if  (ena == 1'b1)   dffe4a[10:10] <= wire_dffe4a_D[10:10];
-	assign
-		wire_dffe4a_D = (d & {11{(~ sclr)}});
-	assign
-		ena = 1'b1,
-		prn = 1'b1,
-		q = dffe4a,
-		sclr = 1'b0;
-endmodule //fifo_2k_dffpipe_ab3
-
-
-//dffpipe WIDTH=11 clock clrn d q
-//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END
-
-
-//dffpipe WIDTH=11 clock clrn d q
-//VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END
-
-//synthesis_resources = lut 11 
-//synopsys translate_off
-`timescale 1 ps / 1 ps
-//synopsys translate_on
-module  fifo_2k_dffpipe_dm2
-	( 
-	clock,
-	clrn,
-	d,
-	q) /* synthesis synthesis_clearbox=1 */
-		/* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */;
-	input   clock;
-	input   clrn;
-	input   [10:0]  d;
-	output   [10:0]  q;
-
-	wire	[10:0]	wire_dffe6a_D;
-	reg	[10:0]	dffe6a;
-	wire ena;
-	wire prn;
-	wire sclr;
-
-	// synopsys translate_off
-	initial
-		dffe6a[0:0] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe6a[0:0] <= 1'b1;
-		else if (clrn == 1'b0) dffe6a[0:0] <= 1'b0;
-		else if  (ena == 1'b1)   dffe6a[0:0] <= wire_dffe6a_D[0:0];
-	// synopsys translate_off
-	initial
-		dffe6a[1:1] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe6a[1:1] <= 1'b1;
-		else if (clrn == 1'b0) dffe6a[1:1] <= 1'b0;
-		else if  (ena == 1'b1)   dffe6a[1:1] <= wire_dffe6a_D[1:1];
-	// synopsys translate_off
-	initial
-		dffe6a[2:2] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe6a[2:2] <= 1'b1;
-		else if (clrn == 1'b0) dffe6a[2:2] <= 1'b0;
-		else if  (ena == 1'b1)   dffe6a[2:2] <= wire_dffe6a_D[2:2];
-	// synopsys translate_off
-	initial
-		dffe6a[3:3] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe6a[3:3] <= 1'b1;
-		else if (clrn == 1'b0) dffe6a[3:3] <= 1'b0;
-		else if  (ena == 1'b1)   dffe6a[3:3] <= wire_dffe6a_D[3:3];
-	// synopsys translate_off
-	initial
-		dffe6a[4:4] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe6a[4:4] <= 1'b1;
-		else if (clrn == 1'b0) dffe6a[4:4] <= 1'b0;
-		else if  (ena == 1'b1)   dffe6a[4:4] <= wire_dffe6a_D[4:4];
-	// synopsys translate_off
-	initial
-		dffe6a[5:5] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe6a[5:5] <= 1'b1;
-		else if (clrn == 1'b0) dffe6a[5:5] <= 1'b0;
-		else if  (ena == 1'b1)   dffe6a[5:5] <= wire_dffe6a_D[5:5];
-	// synopsys translate_off
-	initial
-		dffe6a[6:6] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe6a[6:6] <= 1'b1;
-		else if (clrn == 1'b0) dffe6a[6:6] <= 1'b0;
-		else if  (ena == 1'b1)   dffe6a[6:6] <= wire_dffe6a_D[6:6];
-	// synopsys translate_off
-	initial
-		dffe6a[7:7] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe6a[7:7] <= 1'b1;
-		else if (clrn == 1'b0) dffe6a[7:7] <= 1'b0;
-		else if  (ena == 1'b1)   dffe6a[7:7] <= wire_dffe6a_D[7:7];
-	// synopsys translate_off
-	initial
-		dffe6a[8:8] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe6a[8:8] <= 1'b1;
-		else if (clrn == 1'b0) dffe6a[8:8] <= 1'b0;
-		else if  (ena == 1'b1)   dffe6a[8:8] <= wire_dffe6a_D[8:8];
-	// synopsys translate_off
-	initial
-		dffe6a[9:9] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe6a[9:9] <= 1'b1;
-		else if (clrn == 1'b0) dffe6a[9:9] <= 1'b0;
-		else if  (ena == 1'b1)   dffe6a[9:9] <= wire_dffe6a_D[9:9];
-	// synopsys translate_off
-	initial
-		dffe6a[10:10] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe6a[10:10] <= 1'b1;
-		else if (clrn == 1'b0) dffe6a[10:10] <= 1'b0;
-		else if  (ena == 1'b1)   dffe6a[10:10] <= wire_dffe6a_D[10:10];
-	assign
-		wire_dffe6a_D = (d & {11{(~ sclr)}});
-	assign
-		ena = 1'b1,
-		prn = 1'b1,
-		q = dffe6a,
-		sclr = 1'b0;
-endmodule //fifo_2k_dffpipe_dm2
-
-//synthesis_resources = lut 11 
-//synopsys translate_off
-`timescale 1 ps / 1 ps
-//synopsys translate_on
-module  fifo_2k_alt_synch_pipe_dm2
-	( 
-	clock,
-	clrn,
-	d,
-	q) /* synthesis synthesis_clearbox=1 */
-		/* synthesis ALTERA_ATTRIBUTE="X_ON_VIOLATION_OPTION=OFF" */;
-	input   clock;
-	input   clrn;
-	input   [10:0]  d;
-	output   [10:0]  q;
-
-	wire  [10:0]   wire_dffpipe5_q;
-
-	fifo_2k_dffpipe_dm2   dffpipe5
-	( 
-	.clock(clock),
-	.clrn(clrn),
-	.d(d),
-	.q(wire_dffpipe5_q));
-	assign
-		q = wire_dffpipe5_q;
-endmodule //fifo_2k_alt_synch_pipe_dm2
-
-
-//lpm_add_sub DEVICE_FAMILY="Cyclone" LPM_DIRECTION="SUB" LPM_WIDTH=11 dataa datab result
-//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END
-
-//synthesis_resources = lut 11 
-//synopsys translate_off
-`timescale 1 ps / 1 ps
-//synopsys translate_on
-module  fifo_2k_add_sub_a18
-	( 
-	dataa,
-	datab,
-	result) /* synthesis synthesis_clearbox=1 */;
-	input   [10:0]  dataa;
-	input   [10:0]  datab;
-	output   [10:0]  result;
-
-	wire  [10:0]   wire_add_sub_cella_combout;
-	wire  [0:0]   wire_add_sub_cella_0cout;
-	wire  [0:0]   wire_add_sub_cella_1cout;
-	wire  [0:0]   wire_add_sub_cella_2cout;
-	wire  [0:0]   wire_add_sub_cella_3cout;
-	wire  [0:0]   wire_add_sub_cella_4cout;
-	wire  [0:0]   wire_add_sub_cella_5cout;
-	wire  [0:0]   wire_add_sub_cella_6cout;
-	wire  [0:0]   wire_add_sub_cella_7cout;
-	wire  [0:0]   wire_add_sub_cella_8cout;
-	wire  [0:0]   wire_add_sub_cella_9cout;
-	wire  [10:0]   wire_add_sub_cella_dataa;
-	wire  [10:0]   wire_add_sub_cella_datab;
-
-	cyclone_lcell   add_sub_cella_0
-	( 
-	.cin(1'b1),
-	.combout(wire_add_sub_cella_combout[0:0]),
-	.cout(wire_add_sub_cella_0cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[0:0]),
-	.datab(wire_add_sub_cella_datab[0:0]),
-	.regout()
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aclr(1'b0),
-	.aload(1'b0),
-	.clk(1'b1),
-	.datac(1'b1),
-	.datad(1'b1),
-	.ena(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sclr(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		add_sub_cella_0.cin_used = "true",
-		add_sub_cella_0.lut_mask = "69b2",
-		add_sub_cella_0.operation_mode = "arithmetic",
-		add_sub_cella_0.sum_lutc_input = "cin",
-		add_sub_cella_0.lpm_type = "cyclone_lcell";
-	cyclone_lcell   add_sub_cella_1
-	( 
-	.cin(wire_add_sub_cella_0cout[0:0]),
-	.combout(wire_add_sub_cella_combout[1:1]),
-	.cout(wire_add_sub_cella_1cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[1:1]),
-	.datab(wire_add_sub_cella_datab[1:1]),
-	.regout()
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aclr(1'b0),
-	.aload(1'b0),
-	.clk(1'b1),
-	.datac(1'b1),
-	.datad(1'b1),
-	.ena(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sclr(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		add_sub_cella_1.cin_used = "true",
-		add_sub_cella_1.lut_mask = "69b2",
-		add_sub_cella_1.operation_mode = "arithmetic",
-		add_sub_cella_1.sum_lutc_input = "cin",
-		add_sub_cella_1.lpm_type = "cyclone_lcell";
-	cyclone_lcell   add_sub_cella_2
-	( 
-	.cin(wire_add_sub_cella_1cout[0:0]),
-	.combout(wire_add_sub_cella_combout[2:2]),
-	.cout(wire_add_sub_cella_2cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[2:2]),
-	.datab(wire_add_sub_cella_datab[2:2]),
-	.regout()
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aclr(1'b0),
-	.aload(1'b0),
-	.clk(1'b1),
-	.datac(1'b1),
-	.datad(1'b1),
-	.ena(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sclr(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		add_sub_cella_2.cin_used = "true",
-		add_sub_cella_2.lut_mask = "69b2",
-		add_sub_cella_2.operation_mode = "arithmetic",
-		add_sub_cella_2.sum_lutc_input = "cin",
-		add_sub_cella_2.lpm_type = "cyclone_lcell";
-	cyclone_lcell   add_sub_cella_3
-	( 
-	.cin(wire_add_sub_cella_2cout[0:0]),
-	.combout(wire_add_sub_cella_combout[3:3]),
-	.cout(wire_add_sub_cella_3cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[3:3]),
-	.datab(wire_add_sub_cella_datab[3:3]),
-	.regout()
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aclr(1'b0),
-	.aload(1'b0),
-	.clk(1'b1),
-	.datac(1'b1),
-	.datad(1'b1),
-	.ena(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sclr(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		add_sub_cella_3.cin_used = "true",
-		add_sub_cella_3.lut_mask = "69b2",
-		add_sub_cella_3.operation_mode = "arithmetic",
-		add_sub_cella_3.sum_lutc_input = "cin",
-		add_sub_cella_3.lpm_type = "cyclone_lcell";
-	cyclone_lcell   add_sub_cella_4
-	( 
-	.cin(wire_add_sub_cella_3cout[0:0]),
-	.combout(wire_add_sub_cella_combout[4:4]),
-	.cout(wire_add_sub_cella_4cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[4:4]),
-	.datab(wire_add_sub_cella_datab[4:4]),
-	.regout()
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aclr(1'b0),
-	.aload(1'b0),
-	.clk(1'b1),
-	.datac(1'b1),
-	.datad(1'b1),
-	.ena(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sclr(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		add_sub_cella_4.cin_used = "true",
-		add_sub_cella_4.lut_mask = "69b2",
-		add_sub_cella_4.operation_mode = "arithmetic",
-		add_sub_cella_4.sum_lutc_input = "cin",
-		add_sub_cella_4.lpm_type = "cyclone_lcell";
-	cyclone_lcell   add_sub_cella_5
-	( 
-	.cin(wire_add_sub_cella_4cout[0:0]),
-	.combout(wire_add_sub_cella_combout[5:5]),
-	.cout(wire_add_sub_cella_5cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[5:5]),
-	.datab(wire_add_sub_cella_datab[5:5]),
-	.regout()
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aclr(1'b0),
-	.aload(1'b0),
-	.clk(1'b1),
-	.datac(1'b1),
-	.datad(1'b1),
-	.ena(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sclr(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		add_sub_cella_5.cin_used = "true",
-		add_sub_cella_5.lut_mask = "69b2",
-		add_sub_cella_5.operation_mode = "arithmetic",
-		add_sub_cella_5.sum_lutc_input = "cin",
-		add_sub_cella_5.lpm_type = "cyclone_lcell";
-	cyclone_lcell   add_sub_cella_6
-	( 
-	.cin(wire_add_sub_cella_5cout[0:0]),
-	.combout(wire_add_sub_cella_combout[6:6]),
-	.cout(wire_add_sub_cella_6cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[6:6]),
-	.datab(wire_add_sub_cella_datab[6:6]),
-	.regout()
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aclr(1'b0),
-	.aload(1'b0),
-	.clk(1'b1),
-	.datac(1'b1),
-	.datad(1'b1),
-	.ena(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sclr(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		add_sub_cella_6.cin_used = "true",
-		add_sub_cella_6.lut_mask = "69b2",
-		add_sub_cella_6.operation_mode = "arithmetic",
-		add_sub_cella_6.sum_lutc_input = "cin",
-		add_sub_cella_6.lpm_type = "cyclone_lcell";
-	cyclone_lcell   add_sub_cella_7
-	( 
-	.cin(wire_add_sub_cella_6cout[0:0]),
-	.combout(wire_add_sub_cella_combout[7:7]),
-	.cout(wire_add_sub_cella_7cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[7:7]),
-	.datab(wire_add_sub_cella_datab[7:7]),
-	.regout()
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aclr(1'b0),
-	.aload(1'b0),
-	.clk(1'b1),
-	.datac(1'b1),
-	.datad(1'b1),
-	.ena(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sclr(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		add_sub_cella_7.cin_used = "true",
-		add_sub_cella_7.lut_mask = "69b2",
-		add_sub_cella_7.operation_mode = "arithmetic",
-		add_sub_cella_7.sum_lutc_input = "cin",
-		add_sub_cella_7.lpm_type = "cyclone_lcell";
-	cyclone_lcell   add_sub_cella_8
-	( 
-	.cin(wire_add_sub_cella_7cout[0:0]),
-	.combout(wire_add_sub_cella_combout[8:8]),
-	.cout(wire_add_sub_cella_8cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[8:8]),
-	.datab(wire_add_sub_cella_datab[8:8]),
-	.regout()
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aclr(1'b0),
-	.aload(1'b0),
-	.clk(1'b1),
-	.datac(1'b1),
-	.datad(1'b1),
-	.ena(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sclr(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		add_sub_cella_8.cin_used = "true",
-		add_sub_cella_8.lut_mask = "69b2",
-		add_sub_cella_8.operation_mode = "arithmetic",
-		add_sub_cella_8.sum_lutc_input = "cin",
-		add_sub_cella_8.lpm_type = "cyclone_lcell";
-	cyclone_lcell   add_sub_cella_9
-	( 
-	.cin(wire_add_sub_cella_8cout[0:0]),
-	.combout(wire_add_sub_cella_combout[9:9]),
-	.cout(wire_add_sub_cella_9cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[9:9]),
-	.datab(wire_add_sub_cella_datab[9:9]),
-	.regout()
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aclr(1'b0),
-	.aload(1'b0),
-	.clk(1'b1),
-	.datac(1'b1),
-	.datad(1'b1),
-	.ena(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sclr(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		add_sub_cella_9.cin_used = "true",
-		add_sub_cella_9.lut_mask = "69b2",
-		add_sub_cella_9.operation_mode = "arithmetic",
-		add_sub_cella_9.sum_lutc_input = "cin",
-		add_sub_cella_9.lpm_type = "cyclone_lcell";
-	cyclone_lcell   add_sub_cella_10
-	( 
-	.cin(wire_add_sub_cella_9cout[0:0]),
-	.combout(wire_add_sub_cella_combout[10:10]),
-	.cout(),
-	.dataa(wire_add_sub_cella_dataa[10:10]),
-	.datab(wire_add_sub_cella_datab[10:10]),
-	.regout()
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aclr(1'b0),
-	.aload(1'b0),
-	.clk(1'b1),
-	.datac(1'b1),
-	.datad(1'b1),
-	.ena(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sclr(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		add_sub_cella_10.cin_used = "true",
-		add_sub_cella_10.lut_mask = "6969",
-		add_sub_cella_10.operation_mode = "normal",
-		add_sub_cella_10.sum_lutc_input = "cin",
-		add_sub_cella_10.lpm_type = "cyclone_lcell";
-	assign
-		wire_add_sub_cella_dataa = dataa,
-		wire_add_sub_cella_datab = datab;
-	assign
-		result = wire_add_sub_cella_combout;
-endmodule //fifo_2k_add_sub_a18
-
-
-//lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=11 aeb dataa datab
-//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END
-
-
-//lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=11 aeb dataa datab
-//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END
-
-//synthesis_resources = lut 97 M4K 8 
-//synopsys translate_off
-`timescale 1 ps / 1 ps
-//synopsys translate_on
-module  fifo_2k_dcfifo_0cq
-	( 
-	aclr,
-	data,
-	q,
-	rdclk,
-	rdempty,
-	rdreq,
-	rdusedw,
-	wrclk,
-	wrfull,
-	wrreq,
-	wrusedw) /* synthesis synthesis_clearbox=1 */
-		/* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF;{ -from \"rdptr_g|power_modified_counter_values\" -to \"ws_dgrp|dffpipe5|dffe6a\" }CUT=ON;{ -from \"delayed_wrptr_g\" -to \"rs_dgwp|dffpipe5|dffe6a\" }CUT=ON" */;
-	input   aclr;
-	input   [15:0]  data;
-	output   [15:0]  q;
-	input   rdclk;
-	output   rdempty;
-	input   rdreq;
-	output   [10:0]  rdusedw;
-	input   wrclk;
-	output   wrfull;
-	input   wrreq;
-	output   [10:0]  wrusedw;
-
-	wire  [10:0]   wire_rdptr_g_gray2bin_bin;
-	wire  [10:0]   wire_rs_dgwp_gray2bin_bin;
-	wire  [10:0]   wire_wrptr_g_gray2bin_bin;
-	wire  [10:0]   wire_ws_dgrp_gray2bin_bin;
-	wire  [10:0]   wire_rdptr_g_q;
-	wire  [10:0]   wire_rdptr_g1p_q;
-	wire  [10:0]   wire_wrptr_g1p_q;
-	wire  [15:0]   wire_fifo_ram_q_b;
-	reg	[10:0]	delayed_wrptr_g;
-	reg	[10:0]	wrptr_g;
-	wire  [10:0]   wire_rs_brp_q;
-	wire  [10:0]   wire_rs_bwp_q;
-	wire  [10:0]   wire_rs_dgwp_q;
-	wire  [10:0]   wire_ws_brp_q;
-	wire  [10:0]   wire_ws_bwp_q;
-	wire  [10:0]   wire_ws_dgrp_q;
-	wire  [10:0]   wire_rdusedw_sub_result;
-	wire  [10:0]   wire_wrusedw_sub_result;
-	reg	wire_rdempty_eq_comp_aeb_int;
-	wire	wire_rdempty_eq_comp_aeb;
-	wire	[10:0]	wire_rdempty_eq_comp_dataa;
-	wire	[10:0]	wire_rdempty_eq_comp_datab;
-	reg	wire_wrfull_eq_comp_aeb_int;
-	wire	wire_wrfull_eq_comp_aeb;
-	wire	[10:0]	wire_wrfull_eq_comp_dataa;
-	wire	[10:0]	wire_wrfull_eq_comp_datab;
-	wire  int_rdempty;
-	wire  int_wrfull;
-	wire  valid_rdreq;
-	wire  valid_wrreq;
-
-	fifo_2k_a_gray2bin_8m4   rdptr_g_gray2bin
-	( 
-	.bin(wire_rdptr_g_gray2bin_bin),
-	.gray(wire_rdptr_g_q));
-	fifo_2k_a_gray2bin_8m4   rs_dgwp_gray2bin
-	( 
-	.bin(wire_rs_dgwp_gray2bin_bin),
-	.gray(wire_rs_dgwp_q));
-	fifo_2k_a_gray2bin_8m4   wrptr_g_gray2bin
-	( 
-	.bin(wire_wrptr_g_gray2bin_bin),
-	.gray(wrptr_g));
-	fifo_2k_a_gray2bin_8m4   ws_dgrp_gray2bin
-	( 
-	.bin(wire_ws_dgrp_gray2bin_bin),
-	.gray(wire_ws_dgrp_q));
-	fifo_2k_a_graycounter_726   rdptr_g
-	( 
-	.aclr(aclr),
-	.clock(rdclk),
-	.cnt_en(valid_rdreq),
-	.q(wire_rdptr_g_q));
-	fifo_2k_a_graycounter_2r6   rdptr_g1p
-	( 
-	.aclr(aclr),
-	.clock(rdclk),
-	.cnt_en(valid_rdreq),
-	.q(wire_rdptr_g1p_q));
-	fifo_2k_a_graycounter_2r6   wrptr_g1p
-	( 
-	.aclr(aclr),
-	.clock(wrclk),
-	.cnt_en(valid_wrreq),
-	.q(wire_wrptr_g1p_q));
-	fifo_2k_altsyncram_6pl   fifo_ram
-	( 
-	.address_a(wrptr_g),
-	.address_b(((wire_rdptr_g_q & {11{int_rdempty}}) | (wire_rdptr_g1p_q & {11{(~ int_rdempty)}}))),
-	.clock0(wrclk),
-	.clock1(rdclk),
-	.clocken1((valid_rdreq | int_rdempty)),
-	.data_a(data),
-	.q_b(wire_fifo_ram_q_b),
-	.wren_a(valid_wrreq));
-	// synopsys translate_off
-	initial
-		delayed_wrptr_g = 0;
-	// synopsys translate_on
-	always @ ( posedge wrclk or  posedge aclr)
-		if (aclr == 1'b1) delayed_wrptr_g <= 11'b0;
-		else  delayed_wrptr_g <= wrptr_g;
-	// synopsys translate_off
-	initial
-		wrptr_g = 0;
-	// synopsys translate_on
-	always @ ( posedge wrclk or  posedge aclr)
-		if (aclr == 1'b1) wrptr_g <= 11'b0;
-		else if  (valid_wrreq == 1'b1)   wrptr_g <= wire_wrptr_g1p_q;
-	fifo_2k_dffpipe_ab3   rs_brp
-	( 
-	.clock(rdclk),
-	.clrn((~ aclr)),
-	.d(wire_rdptr_g_gray2bin_bin),
-	.q(wire_rs_brp_q));
-	fifo_2k_dffpipe_ab3   rs_bwp
-	( 
-	.clock(rdclk),
-	.clrn((~ aclr)),
-	.d(wire_rs_dgwp_gray2bin_bin),
-	.q(wire_rs_bwp_q));
-	fifo_2k_alt_synch_pipe_dm2   rs_dgwp
-	( 
-	.clock(rdclk),
-	.clrn((~ aclr)),
-	.d(delayed_wrptr_g),
-	.q(wire_rs_dgwp_q));
-	fifo_2k_dffpipe_ab3   ws_brp
-	( 
-	.clock(wrclk),
-	.clrn((~ aclr)),
-	.d(wire_ws_dgrp_gray2bin_bin),
-	.q(wire_ws_brp_q));
-	fifo_2k_dffpipe_ab3   ws_bwp
-	( 
-	.clock(wrclk),
-	.clrn((~ aclr)),
-	.d(wire_wrptr_g_gray2bin_bin),
-	.q(wire_ws_bwp_q));
-	fifo_2k_alt_synch_pipe_dm2   ws_dgrp
-	( 
-	.clock(wrclk),
-	.clrn((~ aclr)),
-	.d(wire_rdptr_g_q),
-	.q(wire_ws_dgrp_q));
-	fifo_2k_add_sub_a18   rdusedw_sub
-	( 
-	.dataa(wire_rs_bwp_q),
-	.datab(wire_rs_brp_q),
-	.result(wire_rdusedw_sub_result));
-	fifo_2k_add_sub_a18   wrusedw_sub
-	( 
-	.dataa(wire_ws_bwp_q),
-	.datab(wire_ws_brp_q),
-	.result(wire_wrusedw_sub_result));
-	always @(wire_rdempty_eq_comp_dataa or wire_rdempty_eq_comp_datab)
-		if (wire_rdempty_eq_comp_dataa == wire_rdempty_eq_comp_datab) 
-			begin
-				wire_rdempty_eq_comp_aeb_int = 1'b1;
-			end
-		else
-			begin
-				wire_rdempty_eq_comp_aeb_int = 1'b0;
-			end
-	assign
-		wire_rdempty_eq_comp_aeb = wire_rdempty_eq_comp_aeb_int;
-	assign
-		wire_rdempty_eq_comp_dataa = wire_rs_dgwp_q,
-		wire_rdempty_eq_comp_datab = wire_rdptr_g_q;
-	always @(wire_wrfull_eq_comp_dataa or wire_wrfull_eq_comp_datab)
-		if (wire_wrfull_eq_comp_dataa == wire_wrfull_eq_comp_datab) 
-			begin
-				wire_wrfull_eq_comp_aeb_int = 1'b1;
-			end
-		else
-			begin
-				wire_wrfull_eq_comp_aeb_int = 1'b0;
-			end
-	assign
-		wire_wrfull_eq_comp_aeb = wire_wrfull_eq_comp_aeb_int;
-	assign
-		wire_wrfull_eq_comp_dataa = wire_ws_dgrp_q,
-		wire_wrfull_eq_comp_datab = wire_wrptr_g1p_q;
-	assign
-		int_rdempty = wire_rdempty_eq_comp_aeb,
-		int_wrfull = wire_wrfull_eq_comp_aeb,
-		q = wire_fifo_ram_q_b,
-		rdempty = int_rdempty,
-		rdusedw = wire_rdusedw_sub_result,
-		valid_rdreq = rdreq,
-		valid_wrreq = wrreq,
-		wrfull = int_wrfull,
-		wrusedw = wire_wrusedw_sub_result;
-endmodule //fifo_2k_dcfifo_0cq
-//VALID FILE
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module fifo_2k (
-	data,
-	wrreq,
-	rdreq,
-	rdclk,
-	wrclk,
-	aclr,
-	q,
-	rdempty,
-	rdusedw,
-	wrfull,
-	wrusedw)/* synthesis synthesis_clearbox = 1 */;
-
-	input	[15:0]  data;
-	input	  wrreq;
-	input	  rdreq;
-	input	  rdclk;
-	input	  wrclk;
-	input	  aclr;
-	output	[15:0]  q;
-	output	  rdempty;
-	output	[10:0]  rdusedw;
-	output	  wrfull;
-	output	[10:0]  wrusedw;
-
-	wire  sub_wire0;
-	wire [10:0] sub_wire1;
-	wire  sub_wire2;
-	wire [15:0] sub_wire3;
-	wire [10:0] sub_wire4;
-	wire  rdempty = sub_wire0;
-	wire [10:0] wrusedw = sub_wire1[10:0];
-	wire  wrfull = sub_wire2;
-	wire [15:0] q = sub_wire3[15:0];
-	wire [10:0] rdusedw = sub_wire4[10:0];
-
-	fifo_2k_dcfifo_0cq	fifo_2k_dcfifo_0cq_component (
-				.wrclk (wrclk),
-				.rdreq (rdreq),
-				.aclr (aclr),
-				.rdclk (rdclk),
-				.wrreq (wrreq),
-				.data (data),
-				.rdempty (sub_wire0),
-				.wrusedw (sub_wire1),
-				.wrfull (sub_wire2),
-				.q (sub_wire3),
-				.rdusedw (sub_wire4));
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: Width NUMERIC "16"
-// Retrieval info: PRIVATE: Depth NUMERIC "2048"
-// Retrieval info: PRIVATE: Clock NUMERIC "4"
-// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-// Retrieval info: PRIVATE: Full NUMERIC "1"
-// Retrieval info: PRIVATE: Empty NUMERIC "1"
-// Retrieval info: PRIVATE: UsedW NUMERIC "1"
-// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-// Retrieval info: PRIVATE: rsFull NUMERIC "0"
-// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
-// Retrieval info: PRIVATE: wsFull NUMERIC "1"
-// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
-// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
-// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
-// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-// Retrieval info: PRIVATE: Optimize NUMERIC "2"
-// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
-// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
-// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"
-// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
-// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
-// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
-// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
-// Retrieval info: CONSTANT: USE_EAB STRING "ON"
-// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
-// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
-// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
-// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
-// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
-// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
-// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
-// Retrieval info: USED_PORT: rdusedw 0 0 11 0 OUTPUT NODEFVAL rdusedw[10..0]
-// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
-// Retrieval info: USED_PORT: wrusedw 0 0 11 0 OUTPUT NODEFVAL wrusedw[10..0]
-// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
-// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
-// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
-// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
-// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
-// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
-// Retrieval info: CONNECT: rdusedw 0 0 11 0 @rdusedw 0 0 11 0
-// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
-// Retrieval info: CONNECT: wrusedw 0 0 11 0 @wrusedw 0 0 11 0
-// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_bb.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_waveforms.html TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_wave*.jpg FALSE
diff --git a/fpga/usrp1/megacells/fifo_2k_bb.v b/fpga/usrp1/megacells/fifo_2k_bb.v
deleted file mode 100644
index 3fcc2a496..000000000
--- a/fpga/usrp1/megacells/fifo_2k_bb.v
+++ /dev/null
@@ -1,131 +0,0 @@
-// megafunction wizard: %FIFO%VBB%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: dcfifo 
-
-// ============================================================
-// File Name: fifo_2k.v
-// Megafunction Name(s):
-// 			dcfifo
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition
-// ************************************************************
-
-//Copyright (C) 1991-2005 Altera Corporation
-//Your use of Altera Corporation's design tools, logic functions 
-//and other software and tools, and its AMPP partner logic       
-//functions, and any output files any of the foregoing           
-//(including device programming or simulation files), and any    
-//associated documentation or information are expressly subject  
-//to the terms and conditions of the Altera Program License      
-//Subscription Agreement, Altera MegaCore Function License       
-//Agreement, or other applicable license agreement, including,   
-//without limitation, that your use is for the sole purpose of   
-//programming logic devices manufactured by Altera and sold by   
-//Altera or its authorized distributors.  Please refer to the    
-//applicable agreement for further details.
-
-module fifo_2k (
-	data,
-	wrreq,
-	rdreq,
-	rdclk,
-	wrclk,
-	aclr,
-	q,
-	rdempty,
-	rdusedw,
-	wrfull,
-	wrusedw)/* synthesis synthesis_clearbox = 1 */;
-
-	input	[15:0]  data;
-	input	  wrreq;
-	input	  rdreq;
-	input	  rdclk;
-	input	  wrclk;
-	input	  aclr;
-	output	[15:0]  q;
-	output	  rdempty;
-	output	[10:0]  rdusedw;
-	output	  wrfull;
-	output	[10:0]  wrusedw;
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: Width NUMERIC "16"
-// Retrieval info: PRIVATE: Depth NUMERIC "2048"
-// Retrieval info: PRIVATE: Clock NUMERIC "4"
-// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-// Retrieval info: PRIVATE: Full NUMERIC "1"
-// Retrieval info: PRIVATE: Empty NUMERIC "1"
-// Retrieval info: PRIVATE: UsedW NUMERIC "1"
-// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-// Retrieval info: PRIVATE: rsFull NUMERIC "0"
-// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
-// Retrieval info: PRIVATE: wsFull NUMERIC "1"
-// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
-// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
-// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
-// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-// Retrieval info: PRIVATE: Optimize NUMERIC "2"
-// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
-// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
-// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"
-// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
-// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
-// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
-// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
-// Retrieval info: CONSTANT: USE_EAB STRING "ON"
-// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
-// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
-// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
-// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
-// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
-// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
-// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
-// Retrieval info: USED_PORT: rdusedw 0 0 11 0 OUTPUT NODEFVAL rdusedw[10..0]
-// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
-// Retrieval info: USED_PORT: wrusedw 0 0 11 0 OUTPUT NODEFVAL wrusedw[10..0]
-// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
-// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
-// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
-// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
-// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
-// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
-// Retrieval info: CONNECT: rdusedw 0 0 11 0 @rdusedw 0 0 11 0
-// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
-// Retrieval info: CONNECT: wrusedw 0 0 11 0 @wrusedw 0 0 11 0
-// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_bb.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_waveforms.html TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_wave*.jpg FALSE
diff --git a/fpga/usrp1/megacells/fifo_4k.v b/fpga/usrp1/megacells/fifo_4k.v
deleted file mode 100644
index a5ab46677..000000000
--- a/fpga/usrp1/megacells/fifo_4k.v
+++ /dev/null
@@ -1,3495 +0,0 @@
-// megafunction wizard: %FIFO%CBX%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: dcfifo 
-
-// ============================================================
-// File Name: fifo_4k.v
-// Megafunction Name(s):
-// 			dcfifo
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition
-// ************************************************************
-
-
-//Copyright (C) 1991-2005 Altera Corporation
-//Your use of Altera Corporation's design tools, logic functions 
-//and other software and tools, and its AMPP partner logic       
-//functions, and any output files any of the foregoing           
-//(including device programming or simulation files), and any    
-//associated documentation or information are expressly subject  
-//to the terms and conditions of the Altera Program License      
-//Subscription Agreement, Altera MegaCore Function License       
-//Agreement, or other applicable license agreement, including,   
-//without limitation, that your use is for the sole purpose of   
-//programming logic devices manufactured by Altera and sold by   
-//Altera or its authorized distributors.  Please refer to the    
-//applicable agreement for further details.
-
-
-//dcfifo ADD_RAM_OUTPUT_REGISTER="OFF" CLOCKS_ARE_SYNCHRONIZED="FALSE" DEVICE_FAMILY="Cyclone" LPM_NUMWORDS=4096 LPM_SHOWAHEAD="ON" LPM_WIDTH=16 LPM_WIDTHU=12 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" USE_EAB="ON" aclr data q rdclk rdempty rdreq rdusedw wrclk wrfull wrreq wrusedw
-//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END
-
-
-//a_gray2bin device_family="Cyclone" WIDTH=12 bin gray
-//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_mgl 2005:05:19:13:51:58:SJ  VERSION_END
-
-//synthesis_resources = 
-//synopsys translate_off
-`timescale 1 ps / 1 ps
-//synopsys translate_on
-module  fifo_4k_a_gray2bin_9m4
-	( 
-	bin,
-	gray) /* synthesis synthesis_clearbox=1 */;
-	output   [11:0]  bin;
-	input   [11:0]  gray;
-
-	wire  xor0;
-	wire  xor1;
-	wire  xor10;
-	wire  xor2;
-	wire  xor3;
-	wire  xor4;
-	wire  xor5;
-	wire  xor6;
-	wire  xor7;
-	wire  xor8;
-	wire  xor9;
-
-	assign
-		bin = {gray[11], xor10, xor9, xor8, xor7, xor6, xor5, xor4, xor3, xor2, xor1, xor0},
-		xor0 = (gray[0] ^ xor1),
-		xor1 = (gray[1] ^ xor2),
-		xor10 = (gray[11] ^ gray[10]),
-		xor2 = (gray[2] ^ xor3),
-		xor3 = (gray[3] ^ xor4),
-		xor4 = (gray[4] ^ xor5),
-		xor5 = (gray[5] ^ xor6),
-		xor6 = (gray[6] ^ xor7),
-		xor7 = (gray[7] ^ xor8),
-		xor8 = (gray[8] ^ xor9),
-		xor9 = (gray[9] ^ xor10);
-endmodule //fifo_4k_a_gray2bin_9m4
-
-
-//a_graycounter DEVICE_FAMILY="Cyclone" WIDTH=12 aclr clock cnt_en q
-//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END
-
-//synthesis_resources = lut 13 
-//synopsys translate_off
-`timescale 1 ps / 1 ps
-//synopsys translate_on
-module  fifo_4k_a_graycounter_826
-	( 
-	aclr,
-	clock,
-	cnt_en,
-	q) /* synthesis synthesis_clearbox=1 */;
-	input   aclr;
-	input   clock;
-	input   cnt_en;
-	output   [11:0]  q;
-
-	wire  [0:0]   wire_countera_0cout;
-	wire  [0:0]   wire_countera_1cout;
-	wire  [0:0]   wire_countera_2cout;
-	wire  [0:0]   wire_countera_3cout;
-	wire  [0:0]   wire_countera_4cout;
-	wire  [0:0]   wire_countera_5cout;
-	wire  [0:0]   wire_countera_6cout;
-	wire  [0:0]   wire_countera_7cout;
-	wire  [0:0]   wire_countera_8cout;
-	wire  [0:0]   wire_countera_9cout;
-	wire  [0:0]   wire_countera_10cout;
-	wire  [11:0]   wire_countera_regout;
-	wire  wire_parity_cout;
-	wire  wire_parity_regout;
-	wire  [11:0]  power_modified_counter_values;
-	wire sclr;
-	wire updown;
-
-	cyclone_lcell   countera_0
-	( 
-	.aclr(aclr),
-	.cin(wire_parity_cout),
-	.clk(clock),
-	.combout(),
-	.cout(wire_countera_0cout[0:0]),
-	.dataa(cnt_en),
-	.datab(wire_countera_regout[0:0]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[0:0]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_0.cin_used = "true",
-		countera_0.lut_mask = "c6a0",
-		countera_0.operation_mode = "arithmetic",
-		countera_0.sum_lutc_input = "cin",
-		countera_0.synch_mode = "on",
-		countera_0.lpm_type = "cyclone_lcell";
-	cyclone_lcell   countera_1
-	( 
-	.aclr(aclr),
-	.cin(wire_countera_0cout[0:0]),
-	.clk(clock),
-	.combout(),
-	.cout(wire_countera_1cout[0:0]),
-	.dataa(power_modified_counter_values[0]),
-	.datab(power_modified_counter_values[1]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[1:1]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_1.cin_used = "true",
-		countera_1.lut_mask = "6c50",
-		countera_1.operation_mode = "arithmetic",
-		countera_1.sum_lutc_input = "cin",
-		countera_1.synch_mode = "on",
-		countera_1.lpm_type = "cyclone_lcell";
-	cyclone_lcell   countera_2
-	( 
-	.aclr(aclr),
-	.cin(wire_countera_1cout[0:0]),
-	.clk(clock),
-	.combout(),
-	.cout(wire_countera_2cout[0:0]),
-	.dataa(power_modified_counter_values[1]),
-	.datab(power_modified_counter_values[2]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[2:2]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_2.cin_used = "true",
-		countera_2.lut_mask = "6c50",
-		countera_2.operation_mode = "arithmetic",
-		countera_2.sum_lutc_input = "cin",
-		countera_2.synch_mode = "on",
-		countera_2.lpm_type = "cyclone_lcell";
-	cyclone_lcell   countera_3
-	( 
-	.aclr(aclr),
-	.cin(wire_countera_2cout[0:0]),
-	.clk(clock),
-	.combout(),
-	.cout(wire_countera_3cout[0:0]),
-	.dataa(power_modified_counter_values[2]),
-	.datab(power_modified_counter_values[3]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[3:3]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_3.cin_used = "true",
-		countera_3.lut_mask = "6c50",
-		countera_3.operation_mode = "arithmetic",
-		countera_3.sum_lutc_input = "cin",
-		countera_3.synch_mode = "on",
-		countera_3.lpm_type = "cyclone_lcell";
-	cyclone_lcell   countera_4
-	( 
-	.aclr(aclr),
-	.cin(wire_countera_3cout[0:0]),
-	.clk(clock),
-	.combout(),
-	.cout(wire_countera_4cout[0:0]),
-	.dataa(power_modified_counter_values[3]),
-	.datab(power_modified_counter_values[4]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[4:4]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_4.cin_used = "true",
-		countera_4.lut_mask = "6c50",
-		countera_4.operation_mode = "arithmetic",
-		countera_4.sum_lutc_input = "cin",
-		countera_4.synch_mode = "on",
-		countera_4.lpm_type = "cyclone_lcell";
-	cyclone_lcell   countera_5
-	( 
-	.aclr(aclr),
-	.cin(wire_countera_4cout[0:0]),
-	.clk(clock),
-	.combout(),
-	.cout(wire_countera_5cout[0:0]),
-	.dataa(power_modified_counter_values[4]),
-	.datab(power_modified_counter_values[5]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[5:5]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_5.cin_used = "true",
-		countera_5.lut_mask = "6c50",
-		countera_5.operation_mode = "arithmetic",
-		countera_5.sum_lutc_input = "cin",
-		countera_5.synch_mode = "on",
-		countera_5.lpm_type = "cyclone_lcell";
-	cyclone_lcell   countera_6
-	( 
-	.aclr(aclr),
-	.cin(wire_countera_5cout[0:0]),
-	.clk(clock),
-	.combout(),
-	.cout(wire_countera_6cout[0:0]),
-	.dataa(power_modified_counter_values[5]),
-	.datab(power_modified_counter_values[6]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[6:6]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_6.cin_used = "true",
-		countera_6.lut_mask = "6c50",
-		countera_6.operation_mode = "arithmetic",
-		countera_6.sum_lutc_input = "cin",
-		countera_6.synch_mode = "on",
-		countera_6.lpm_type = "cyclone_lcell";
-	cyclone_lcell   countera_7
-	( 
-	.aclr(aclr),
-	.cin(wire_countera_6cout[0:0]),
-	.clk(clock),
-	.combout(),
-	.cout(wire_countera_7cout[0:0]),
-	.dataa(power_modified_counter_values[6]),
-	.datab(power_modified_counter_values[7]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[7:7]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_7.cin_used = "true",
-		countera_7.lut_mask = "6c50",
-		countera_7.operation_mode = "arithmetic",
-		countera_7.sum_lutc_input = "cin",
-		countera_7.synch_mode = "on",
-		countera_7.lpm_type = "cyclone_lcell";
-	cyclone_lcell   countera_8
-	( 
-	.aclr(aclr),
-	.cin(wire_countera_7cout[0:0]),
-	.clk(clock),
-	.combout(),
-	.cout(wire_countera_8cout[0:0]),
-	.dataa(power_modified_counter_values[7]),
-	.datab(power_modified_counter_values[8]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[8:8]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_8.cin_used = "true",
-		countera_8.lut_mask = "6c50",
-		countera_8.operation_mode = "arithmetic",
-		countera_8.sum_lutc_input = "cin",
-		countera_8.synch_mode = "on",
-		countera_8.lpm_type = "cyclone_lcell";
-	cyclone_lcell   countera_9
-	( 
-	.aclr(aclr),
-	.cin(wire_countera_8cout[0:0]),
-	.clk(clock),
-	.combout(),
-	.cout(wire_countera_9cout[0:0]),
-	.dataa(power_modified_counter_values[8]),
-	.datab(power_modified_counter_values[9]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[9:9]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_9.cin_used = "true",
-		countera_9.lut_mask = "6c50",
-		countera_9.operation_mode = "arithmetic",
-		countera_9.sum_lutc_input = "cin",
-		countera_9.synch_mode = "on",
-		countera_9.lpm_type = "cyclone_lcell";
-	cyclone_lcell   countera_10
-	( 
-	.aclr(aclr),
-	.cin(wire_countera_9cout[0:0]),
-	.clk(clock),
-	.combout(),
-	.cout(wire_countera_10cout[0:0]),
-	.dataa(power_modified_counter_values[9]),
-	.datab(power_modified_counter_values[10]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[10:10]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_10.cin_used = "true",
-		countera_10.lut_mask = "6c50",
-		countera_10.operation_mode = "arithmetic",
-		countera_10.sum_lutc_input = "cin",
-		countera_10.synch_mode = "on",
-		countera_10.lpm_type = "cyclone_lcell";
-	cyclone_lcell   countera_11
-	( 
-	.aclr(aclr),
-	.cin(wire_countera_10cout[0:0]),
-	.clk(clock),
-	.combout(),
-	.cout(),
-	.dataa(power_modified_counter_values[11]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[11:11]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datab(1'b1),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_11.cin_used = "true",
-		countera_11.lut_mask = "5a5a",
-		countera_11.operation_mode = "normal",
-		countera_11.sum_lutc_input = "cin",
-		countera_11.synch_mode = "on",
-		countera_11.lpm_type = "cyclone_lcell";
-	cyclone_lcell   parity
-	( 
-	.aclr(aclr),
-	.cin(updown),
-	.clk(clock),
-	.combout(),
-	.cout(wire_parity_cout),
-	.dataa(cnt_en),
-	.datab(wire_parity_regout),
-	.ena(1'b1),
-	.regout(wire_parity_regout),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		parity.cin_used = "true",
-		parity.lut_mask = "6682",
-		parity.operation_mode = "arithmetic",
-		parity.synch_mode = "on",
-		parity.lpm_type = "cyclone_lcell";
-	assign
-		power_modified_counter_values = {wire_countera_regout[11:0]},
-		q = power_modified_counter_values,
-		sclr = 1'b0,
-		updown = 1'b1;
-endmodule //fifo_4k_a_graycounter_826
-
-
-//a_graycounter DEVICE_FAMILY="Cyclone" PVALUE=1 WIDTH=12 aclr clock cnt_en q
-//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END
-
-//synthesis_resources = lut 13 
-//synopsys translate_off
-`timescale 1 ps / 1 ps
-//synopsys translate_on
-module  fifo_4k_a_graycounter_3r6
-	( 
-	aclr,
-	clock,
-	cnt_en,
-	q) /* synthesis synthesis_clearbox=1 */;
-	input   aclr;
-	input   clock;
-	input   cnt_en;
-	output   [11:0]  q;
-
-	wire  [0:0]   wire_countera_0cout;
-	wire  [0:0]   wire_countera_1cout;
-	wire  [0:0]   wire_countera_2cout;
-	wire  [0:0]   wire_countera_3cout;
-	wire  [0:0]   wire_countera_4cout;
-	wire  [0:0]   wire_countera_5cout;
-	wire  [0:0]   wire_countera_6cout;
-	wire  [0:0]   wire_countera_7cout;
-	wire  [0:0]   wire_countera_8cout;
-	wire  [0:0]   wire_countera_9cout;
-	wire  [0:0]   wire_countera_10cout;
-	wire  [11:0]   wire_countera_regout;
-	wire  wire_parity_cout;
-	wire  wire_parity_regout;
-	wire  [11:0]  power_modified_counter_values;
-	wire sclr;
-	wire updown;
-
-	cyclone_lcell   countera_0
-	( 
-	.aclr(aclr),
-	.cin(wire_parity_cout),
-	.clk(clock),
-	.combout(),
-	.cout(wire_countera_0cout[0:0]),
-	.dataa(cnt_en),
-	.datab(wire_countera_regout[0:0]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[0:0]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_0.cin_used = "true",
-		countera_0.lut_mask = "c6a0",
-		countera_0.operation_mode = "arithmetic",
-		countera_0.sum_lutc_input = "cin",
-		countera_0.synch_mode = "on",
-		countera_0.lpm_type = "cyclone_lcell";
-	cyclone_lcell   countera_1
-	( 
-	.aclr(aclr),
-	.cin(wire_countera_0cout[0:0]),
-	.clk(clock),
-	.combout(),
-	.cout(wire_countera_1cout[0:0]),
-	.dataa(power_modified_counter_values[0]),
-	.datab(power_modified_counter_values[1]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[1:1]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_1.cin_used = "true",
-		countera_1.lut_mask = "6c50",
-		countera_1.operation_mode = "arithmetic",
-		countera_1.sum_lutc_input = "cin",
-		countera_1.synch_mode = "on",
-		countera_1.lpm_type = "cyclone_lcell";
-	cyclone_lcell   countera_2
-	( 
-	.aclr(aclr),
-	.cin(wire_countera_1cout[0:0]),
-	.clk(clock),
-	.combout(),
-	.cout(wire_countera_2cout[0:0]),
-	.dataa(power_modified_counter_values[1]),
-	.datab(power_modified_counter_values[2]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[2:2]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_2.cin_used = "true",
-		countera_2.lut_mask = "6c50",
-		countera_2.operation_mode = "arithmetic",
-		countera_2.sum_lutc_input = "cin",
-		countera_2.synch_mode = "on",
-		countera_2.lpm_type = "cyclone_lcell";
-	cyclone_lcell   countera_3
-	( 
-	.aclr(aclr),
-	.cin(wire_countera_2cout[0:0]),
-	.clk(clock),
-	.combout(),
-	.cout(wire_countera_3cout[0:0]),
-	.dataa(power_modified_counter_values[2]),
-	.datab(power_modified_counter_values[3]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[3:3]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_3.cin_used = "true",
-		countera_3.lut_mask = "6c50",
-		countera_3.operation_mode = "arithmetic",
-		countera_3.sum_lutc_input = "cin",
-		countera_3.synch_mode = "on",
-		countera_3.lpm_type = "cyclone_lcell";
-	cyclone_lcell   countera_4
-	( 
-	.aclr(aclr),
-	.cin(wire_countera_3cout[0:0]),
-	.clk(clock),
-	.combout(),
-	.cout(wire_countera_4cout[0:0]),
-	.dataa(power_modified_counter_values[3]),
-	.datab(power_modified_counter_values[4]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[4:4]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_4.cin_used = "true",
-		countera_4.lut_mask = "6c50",
-		countera_4.operation_mode = "arithmetic",
-		countera_4.sum_lutc_input = "cin",
-		countera_4.synch_mode = "on",
-		countera_4.lpm_type = "cyclone_lcell";
-	cyclone_lcell   countera_5
-	( 
-	.aclr(aclr),
-	.cin(wire_countera_4cout[0:0]),
-	.clk(clock),
-	.combout(),
-	.cout(wire_countera_5cout[0:0]),
-	.dataa(power_modified_counter_values[4]),
-	.datab(power_modified_counter_values[5]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[5:5]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_5.cin_used = "true",
-		countera_5.lut_mask = "6c50",
-		countera_5.operation_mode = "arithmetic",
-		countera_5.sum_lutc_input = "cin",
-		countera_5.synch_mode = "on",
-		countera_5.lpm_type = "cyclone_lcell";
-	cyclone_lcell   countera_6
-	( 
-	.aclr(aclr),
-	.cin(wire_countera_5cout[0:0]),
-	.clk(clock),
-	.combout(),
-	.cout(wire_countera_6cout[0:0]),
-	.dataa(power_modified_counter_values[5]),
-	.datab(power_modified_counter_values[6]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[6:6]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_6.cin_used = "true",
-		countera_6.lut_mask = "6c50",
-		countera_6.operation_mode = "arithmetic",
-		countera_6.sum_lutc_input = "cin",
-		countera_6.synch_mode = "on",
-		countera_6.lpm_type = "cyclone_lcell";
-	cyclone_lcell   countera_7
-	( 
-	.aclr(aclr),
-	.cin(wire_countera_6cout[0:0]),
-	.clk(clock),
-	.combout(),
-	.cout(wire_countera_7cout[0:0]),
-	.dataa(power_modified_counter_values[6]),
-	.datab(power_modified_counter_values[7]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[7:7]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_7.cin_used = "true",
-		countera_7.lut_mask = "6c50",
-		countera_7.operation_mode = "arithmetic",
-		countera_7.sum_lutc_input = "cin",
-		countera_7.synch_mode = "on",
-		countera_7.lpm_type = "cyclone_lcell";
-	cyclone_lcell   countera_8
-	( 
-	.aclr(aclr),
-	.cin(wire_countera_7cout[0:0]),
-	.clk(clock),
-	.combout(),
-	.cout(wire_countera_8cout[0:0]),
-	.dataa(power_modified_counter_values[7]),
-	.datab(power_modified_counter_values[8]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[8:8]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_8.cin_used = "true",
-		countera_8.lut_mask = "6c50",
-		countera_8.operation_mode = "arithmetic",
-		countera_8.sum_lutc_input = "cin",
-		countera_8.synch_mode = "on",
-		countera_8.lpm_type = "cyclone_lcell";
-	cyclone_lcell   countera_9
-	( 
-	.aclr(aclr),
-	.cin(wire_countera_8cout[0:0]),
-	.clk(clock),
-	.combout(),
-	.cout(wire_countera_9cout[0:0]),
-	.dataa(power_modified_counter_values[8]),
-	.datab(power_modified_counter_values[9]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[9:9]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_9.cin_used = "true",
-		countera_9.lut_mask = "6c50",
-		countera_9.operation_mode = "arithmetic",
-		countera_9.sum_lutc_input = "cin",
-		countera_9.synch_mode = "on",
-		countera_9.lpm_type = "cyclone_lcell";
-	cyclone_lcell   countera_10
-	( 
-	.aclr(aclr),
-	.cin(wire_countera_9cout[0:0]),
-	.clk(clock),
-	.combout(),
-	.cout(wire_countera_10cout[0:0]),
-	.dataa(power_modified_counter_values[9]),
-	.datab(power_modified_counter_values[10]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[10:10]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_10.cin_used = "true",
-		countera_10.lut_mask = "6c50",
-		countera_10.operation_mode = "arithmetic",
-		countera_10.sum_lutc_input = "cin",
-		countera_10.synch_mode = "on",
-		countera_10.lpm_type = "cyclone_lcell";
-	cyclone_lcell   countera_11
-	( 
-	.aclr(aclr),
-	.cin(wire_countera_10cout[0:0]),
-	.clk(clock),
-	.combout(),
-	.cout(),
-	.dataa(power_modified_counter_values[11]),
-	.ena(1'b1),
-	.regout(wire_countera_regout[11:11]),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datab(1'b1),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		countera_11.cin_used = "true",
-		countera_11.lut_mask = "5a5a",
-		countera_11.operation_mode = "normal",
-		countera_11.sum_lutc_input = "cin",
-		countera_11.synch_mode = "on",
-		countera_11.lpm_type = "cyclone_lcell";
-	cyclone_lcell   parity
-	( 
-	.aclr(aclr),
-	.cin(updown),
-	.clk(clock),
-	.combout(),
-	.cout(wire_parity_cout),
-	.dataa(cnt_en),
-	.datab((~ wire_parity_regout)),
-	.ena(1'b1),
-	.regout(wire_parity_regout),
-	.sclr(sclr)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aload(1'b0),
-	.datac(1'b1),
-	.datad(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		parity.cin_used = "true",
-		parity.lut_mask = "9982",
-		parity.operation_mode = "arithmetic",
-		parity.synch_mode = "on",
-		parity.lpm_type = "cyclone_lcell";
-	assign
-		power_modified_counter_values = {wire_countera_regout[11:1], (~ wire_countera_regout[0])},
-		q = power_modified_counter_values,
-		sclr = 1'b0,
-		updown = 1'b1;
-endmodule //fifo_4k_a_graycounter_3r6
-
-
-//altsyncram ADDRESS_REG_B="CLOCK1" DEVICE_FAMILY="Cyclone" OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" WIDTH_A=16 WIDTH_B=16 WIDTH_BYTEENA_A=1 WIDTHAD_A=12 WIDTHAD_B=12 address_a address_b clock0 clock1 clocken1 data_a q_b wren_a
-//VERSION_BEGIN 5.0 cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END
-
-//synthesis_resources = M4K 16 
-//synopsys translate_off
-`timescale 1 ps / 1 ps
-//synopsys translate_on
-module  fifo_4k_altsyncram_8pl
-	( 
-	address_a,
-	address_b,
-	clock0,
-	clock1,
-	clocken1,
-	data_a,
-	q_b,
-	wren_a) /* synthesis synthesis_clearbox=1 */;
-	input   [11:0]  address_a;
-	input   [11:0]  address_b;
-	input   clock0;
-	input   clock1;
-	input   clocken1;
-	input   [15:0]  data_a;
-	output   [15:0]  q_b;
-	input   wren_a;
-
-	wire  [0:0]   wire_ram_block3a_0portbdataout;
-	wire  [0:0]   wire_ram_block3a_1portbdataout;
-	wire  [0:0]   wire_ram_block3a_2portbdataout;
-	wire  [0:0]   wire_ram_block3a_3portbdataout;
-	wire  [0:0]   wire_ram_block3a_4portbdataout;
-	wire  [0:0]   wire_ram_block3a_5portbdataout;
-	wire  [0:0]   wire_ram_block3a_6portbdataout;
-	wire  [0:0]   wire_ram_block3a_7portbdataout;
-	wire  [0:0]   wire_ram_block3a_8portbdataout;
-	wire  [0:0]   wire_ram_block3a_9portbdataout;
-	wire  [0:0]   wire_ram_block3a_10portbdataout;
-	wire  [0:0]   wire_ram_block3a_11portbdataout;
-	wire  [0:0]   wire_ram_block3a_12portbdataout;
-	wire  [0:0]   wire_ram_block3a_13portbdataout;
-	wire  [0:0]   wire_ram_block3a_14portbdataout;
-	wire  [0:0]   wire_ram_block3a_15portbdataout;
-	wire  [11:0]  address_a_wire;
-	wire  [11:0]  address_b_wire;
-
-	cyclone_ram_block   ram_block3a_0
-	( 
-	.clk0(clock0),
-	.clk1(clock1),
-	.ena0(wren_a),
-	.ena1(clocken1),
-	.portaaddr({address_a_wire[11:0]}),
-	.portadatain({data_a[0]}),
-	.portadataout(),
-	.portawe(1'b1),
-	.portbaddr({address_b_wire[11:0]}),
-	.portbdataout(wire_ram_block3a_0portbdataout[0:0]),
-	.portbrewe(1'b1)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.clr0(1'b0),
-	.clr1(1'b0),
-	.portabyteenamasks(1'b1),
-	.portbbyteenamasks(1'b1),
-	.portbdatain(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		ram_block3a_0.connectivity_checking = "OFF",
-		ram_block3a_0.logical_ram_name = "ALTSYNCRAM",
-		ram_block3a_0.mixed_port_feed_through_mode = "dont_care",
-		ram_block3a_0.operation_mode = "dual_port",
-		ram_block3a_0.port_a_address_width = 12,
-		ram_block3a_0.port_a_data_width = 1,
-		ram_block3a_0.port_a_first_address = 0,
-		ram_block3a_0.port_a_first_bit_number = 0,
-		ram_block3a_0.port_a_last_address = 4095,
-		ram_block3a_0.port_a_logical_ram_depth = 4096,
-		ram_block3a_0.port_a_logical_ram_width = 16,
-		ram_block3a_0.port_b_address_clear = "none",
-		ram_block3a_0.port_b_address_clock = "clock1",
-		ram_block3a_0.port_b_address_width = 12,
-		ram_block3a_0.port_b_data_out_clear = "none",
-		ram_block3a_0.port_b_data_out_clock = "none",
-		ram_block3a_0.port_b_data_width = 1,
-		ram_block3a_0.port_b_first_address = 0,
-		ram_block3a_0.port_b_first_bit_number = 0,
-		ram_block3a_0.port_b_last_address = 4095,
-		ram_block3a_0.port_b_logical_ram_depth = 4096,
-		ram_block3a_0.port_b_logical_ram_width = 16,
-		ram_block3a_0.port_b_read_enable_write_enable_clock = "clock1",
-		ram_block3a_0.ram_block_type = "auto",
-		ram_block3a_0.lpm_type = "cyclone_ram_block";
-	cyclone_ram_block   ram_block3a_1
-	( 
-	.clk0(clock0),
-	.clk1(clock1),
-	.ena0(wren_a),
-	.ena1(clocken1),
-	.portaaddr({address_a_wire[11:0]}),
-	.portadatain({data_a[1]}),
-	.portadataout(),
-	.portawe(1'b1),
-	.portbaddr({address_b_wire[11:0]}),
-	.portbdataout(wire_ram_block3a_1portbdataout[0:0]),
-	.portbrewe(1'b1)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.clr0(1'b0),
-	.clr1(1'b0),
-	.portabyteenamasks(1'b1),
-	.portbbyteenamasks(1'b1),
-	.portbdatain(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		ram_block3a_1.connectivity_checking = "OFF",
-		ram_block3a_1.logical_ram_name = "ALTSYNCRAM",
-		ram_block3a_1.mixed_port_feed_through_mode = "dont_care",
-		ram_block3a_1.operation_mode = "dual_port",
-		ram_block3a_1.port_a_address_width = 12,
-		ram_block3a_1.port_a_data_width = 1,
-		ram_block3a_1.port_a_first_address = 0,
-		ram_block3a_1.port_a_first_bit_number = 1,
-		ram_block3a_1.port_a_last_address = 4095,
-		ram_block3a_1.port_a_logical_ram_depth = 4096,
-		ram_block3a_1.port_a_logical_ram_width = 16,
-		ram_block3a_1.port_b_address_clear = "none",
-		ram_block3a_1.port_b_address_clock = "clock1",
-		ram_block3a_1.port_b_address_width = 12,
-		ram_block3a_1.port_b_data_out_clear = "none",
-		ram_block3a_1.port_b_data_out_clock = "none",
-		ram_block3a_1.port_b_data_width = 1,
-		ram_block3a_1.port_b_first_address = 0,
-		ram_block3a_1.port_b_first_bit_number = 1,
-		ram_block3a_1.port_b_last_address = 4095,
-		ram_block3a_1.port_b_logical_ram_depth = 4096,
-		ram_block3a_1.port_b_logical_ram_width = 16,
-		ram_block3a_1.port_b_read_enable_write_enable_clock = "clock1",
-		ram_block3a_1.ram_block_type = "auto",
-		ram_block3a_1.lpm_type = "cyclone_ram_block";
-	cyclone_ram_block   ram_block3a_2
-	( 
-	.clk0(clock0),
-	.clk1(clock1),
-	.ena0(wren_a),
-	.ena1(clocken1),
-	.portaaddr({address_a_wire[11:0]}),
-	.portadatain({data_a[2]}),
-	.portadataout(),
-	.portawe(1'b1),
-	.portbaddr({address_b_wire[11:0]}),
-	.portbdataout(wire_ram_block3a_2portbdataout[0:0]),
-	.portbrewe(1'b1)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.clr0(1'b0),
-	.clr1(1'b0),
-	.portabyteenamasks(1'b1),
-	.portbbyteenamasks(1'b1),
-	.portbdatain(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		ram_block3a_2.connectivity_checking = "OFF",
-		ram_block3a_2.logical_ram_name = "ALTSYNCRAM",
-		ram_block3a_2.mixed_port_feed_through_mode = "dont_care",
-		ram_block3a_2.operation_mode = "dual_port",
-		ram_block3a_2.port_a_address_width = 12,
-		ram_block3a_2.port_a_data_width = 1,
-		ram_block3a_2.port_a_first_address = 0,
-		ram_block3a_2.port_a_first_bit_number = 2,
-		ram_block3a_2.port_a_last_address = 4095,
-		ram_block3a_2.port_a_logical_ram_depth = 4096,
-		ram_block3a_2.port_a_logical_ram_width = 16,
-		ram_block3a_2.port_b_address_clear = "none",
-		ram_block3a_2.port_b_address_clock = "clock1",
-		ram_block3a_2.port_b_address_width = 12,
-		ram_block3a_2.port_b_data_out_clear = "none",
-		ram_block3a_2.port_b_data_out_clock = "none",
-		ram_block3a_2.port_b_data_width = 1,
-		ram_block3a_2.port_b_first_address = 0,
-		ram_block3a_2.port_b_first_bit_number = 2,
-		ram_block3a_2.port_b_last_address = 4095,
-		ram_block3a_2.port_b_logical_ram_depth = 4096,
-		ram_block3a_2.port_b_logical_ram_width = 16,
-		ram_block3a_2.port_b_read_enable_write_enable_clock = "clock1",
-		ram_block3a_2.ram_block_type = "auto",
-		ram_block3a_2.lpm_type = "cyclone_ram_block";
-	cyclone_ram_block   ram_block3a_3
-	( 
-	.clk0(clock0),
-	.clk1(clock1),
-	.ena0(wren_a),
-	.ena1(clocken1),
-	.portaaddr({address_a_wire[11:0]}),
-	.portadatain({data_a[3]}),
-	.portadataout(),
-	.portawe(1'b1),
-	.portbaddr({address_b_wire[11:0]}),
-	.portbdataout(wire_ram_block3a_3portbdataout[0:0]),
-	.portbrewe(1'b1)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.clr0(1'b0),
-	.clr1(1'b0),
-	.portabyteenamasks(1'b1),
-	.portbbyteenamasks(1'b1),
-	.portbdatain(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		ram_block3a_3.connectivity_checking = "OFF",
-		ram_block3a_3.logical_ram_name = "ALTSYNCRAM",
-		ram_block3a_3.mixed_port_feed_through_mode = "dont_care",
-		ram_block3a_3.operation_mode = "dual_port",
-		ram_block3a_3.port_a_address_width = 12,
-		ram_block3a_3.port_a_data_width = 1,
-		ram_block3a_3.port_a_first_address = 0,
-		ram_block3a_3.port_a_first_bit_number = 3,
-		ram_block3a_3.port_a_last_address = 4095,
-		ram_block3a_3.port_a_logical_ram_depth = 4096,
-		ram_block3a_3.port_a_logical_ram_width = 16,
-		ram_block3a_3.port_b_address_clear = "none",
-		ram_block3a_3.port_b_address_clock = "clock1",
-		ram_block3a_3.port_b_address_width = 12,
-		ram_block3a_3.port_b_data_out_clear = "none",
-		ram_block3a_3.port_b_data_out_clock = "none",
-		ram_block3a_3.port_b_data_width = 1,
-		ram_block3a_3.port_b_first_address = 0,
-		ram_block3a_3.port_b_first_bit_number = 3,
-		ram_block3a_3.port_b_last_address = 4095,
-		ram_block3a_3.port_b_logical_ram_depth = 4096,
-		ram_block3a_3.port_b_logical_ram_width = 16,
-		ram_block3a_3.port_b_read_enable_write_enable_clock = "clock1",
-		ram_block3a_3.ram_block_type = "auto",
-		ram_block3a_3.lpm_type = "cyclone_ram_block";
-	cyclone_ram_block   ram_block3a_4
-	( 
-	.clk0(clock0),
-	.clk1(clock1),
-	.ena0(wren_a),
-	.ena1(clocken1),
-	.portaaddr({address_a_wire[11:0]}),
-	.portadatain({data_a[4]}),
-	.portadataout(),
-	.portawe(1'b1),
-	.portbaddr({address_b_wire[11:0]}),
-	.portbdataout(wire_ram_block3a_4portbdataout[0:0]),
-	.portbrewe(1'b1)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.clr0(1'b0),
-	.clr1(1'b0),
-	.portabyteenamasks(1'b1),
-	.portbbyteenamasks(1'b1),
-	.portbdatain(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		ram_block3a_4.connectivity_checking = "OFF",
-		ram_block3a_4.logical_ram_name = "ALTSYNCRAM",
-		ram_block3a_4.mixed_port_feed_through_mode = "dont_care",
-		ram_block3a_4.operation_mode = "dual_port",
-		ram_block3a_4.port_a_address_width = 12,
-		ram_block3a_4.port_a_data_width = 1,
-		ram_block3a_4.port_a_first_address = 0,
-		ram_block3a_4.port_a_first_bit_number = 4,
-		ram_block3a_4.port_a_last_address = 4095,
-		ram_block3a_4.port_a_logical_ram_depth = 4096,
-		ram_block3a_4.port_a_logical_ram_width = 16,
-		ram_block3a_4.port_b_address_clear = "none",
-		ram_block3a_4.port_b_address_clock = "clock1",
-		ram_block3a_4.port_b_address_width = 12,
-		ram_block3a_4.port_b_data_out_clear = "none",
-		ram_block3a_4.port_b_data_out_clock = "none",
-		ram_block3a_4.port_b_data_width = 1,
-		ram_block3a_4.port_b_first_address = 0,
-		ram_block3a_4.port_b_first_bit_number = 4,
-		ram_block3a_4.port_b_last_address = 4095,
-		ram_block3a_4.port_b_logical_ram_depth = 4096,
-		ram_block3a_4.port_b_logical_ram_width = 16,
-		ram_block3a_4.port_b_read_enable_write_enable_clock = "clock1",
-		ram_block3a_4.ram_block_type = "auto",
-		ram_block3a_4.lpm_type = "cyclone_ram_block";
-	cyclone_ram_block   ram_block3a_5
-	( 
-	.clk0(clock0),
-	.clk1(clock1),
-	.ena0(wren_a),
-	.ena1(clocken1),
-	.portaaddr({address_a_wire[11:0]}),
-	.portadatain({data_a[5]}),
-	.portadataout(),
-	.portawe(1'b1),
-	.portbaddr({address_b_wire[11:0]}),
-	.portbdataout(wire_ram_block3a_5portbdataout[0:0]),
-	.portbrewe(1'b1)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.clr0(1'b0),
-	.clr1(1'b0),
-	.portabyteenamasks(1'b1),
-	.portbbyteenamasks(1'b1),
-	.portbdatain(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		ram_block3a_5.connectivity_checking = "OFF",
-		ram_block3a_5.logical_ram_name = "ALTSYNCRAM",
-		ram_block3a_5.mixed_port_feed_through_mode = "dont_care",
-		ram_block3a_5.operation_mode = "dual_port",
-		ram_block3a_5.port_a_address_width = 12,
-		ram_block3a_5.port_a_data_width = 1,
-		ram_block3a_5.port_a_first_address = 0,
-		ram_block3a_5.port_a_first_bit_number = 5,
-		ram_block3a_5.port_a_last_address = 4095,
-		ram_block3a_5.port_a_logical_ram_depth = 4096,
-		ram_block3a_5.port_a_logical_ram_width = 16,
-		ram_block3a_5.port_b_address_clear = "none",
-		ram_block3a_5.port_b_address_clock = "clock1",
-		ram_block3a_5.port_b_address_width = 12,
-		ram_block3a_5.port_b_data_out_clear = "none",
-		ram_block3a_5.port_b_data_out_clock = "none",
-		ram_block3a_5.port_b_data_width = 1,
-		ram_block3a_5.port_b_first_address = 0,
-		ram_block3a_5.port_b_first_bit_number = 5,
-		ram_block3a_5.port_b_last_address = 4095,
-		ram_block3a_5.port_b_logical_ram_depth = 4096,
-		ram_block3a_5.port_b_logical_ram_width = 16,
-		ram_block3a_5.port_b_read_enable_write_enable_clock = "clock1",
-		ram_block3a_5.ram_block_type = "auto",
-		ram_block3a_5.lpm_type = "cyclone_ram_block";
-	cyclone_ram_block   ram_block3a_6
-	( 
-	.clk0(clock0),
-	.clk1(clock1),
-	.ena0(wren_a),
-	.ena1(clocken1),
-	.portaaddr({address_a_wire[11:0]}),
-	.portadatain({data_a[6]}),
-	.portadataout(),
-	.portawe(1'b1),
-	.portbaddr({address_b_wire[11:0]}),
-	.portbdataout(wire_ram_block3a_6portbdataout[0:0]),
-	.portbrewe(1'b1)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.clr0(1'b0),
-	.clr1(1'b0),
-	.portabyteenamasks(1'b1),
-	.portbbyteenamasks(1'b1),
-	.portbdatain(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		ram_block3a_6.connectivity_checking = "OFF",
-		ram_block3a_6.logical_ram_name = "ALTSYNCRAM",
-		ram_block3a_6.mixed_port_feed_through_mode = "dont_care",
-		ram_block3a_6.operation_mode = "dual_port",
-		ram_block3a_6.port_a_address_width = 12,
-		ram_block3a_6.port_a_data_width = 1,
-		ram_block3a_6.port_a_first_address = 0,
-		ram_block3a_6.port_a_first_bit_number = 6,
-		ram_block3a_6.port_a_last_address = 4095,
-		ram_block3a_6.port_a_logical_ram_depth = 4096,
-		ram_block3a_6.port_a_logical_ram_width = 16,
-		ram_block3a_6.port_b_address_clear = "none",
-		ram_block3a_6.port_b_address_clock = "clock1",
-		ram_block3a_6.port_b_address_width = 12,
-		ram_block3a_6.port_b_data_out_clear = "none",
-		ram_block3a_6.port_b_data_out_clock = "none",
-		ram_block3a_6.port_b_data_width = 1,
-		ram_block3a_6.port_b_first_address = 0,
-		ram_block3a_6.port_b_first_bit_number = 6,
-		ram_block3a_6.port_b_last_address = 4095,
-		ram_block3a_6.port_b_logical_ram_depth = 4096,
-		ram_block3a_6.port_b_logical_ram_width = 16,
-		ram_block3a_6.port_b_read_enable_write_enable_clock = "clock1",
-		ram_block3a_6.ram_block_type = "auto",
-		ram_block3a_6.lpm_type = "cyclone_ram_block";
-	cyclone_ram_block   ram_block3a_7
-	( 
-	.clk0(clock0),
-	.clk1(clock1),
-	.ena0(wren_a),
-	.ena1(clocken1),
-	.portaaddr({address_a_wire[11:0]}),
-	.portadatain({data_a[7]}),
-	.portadataout(),
-	.portawe(1'b1),
-	.portbaddr({address_b_wire[11:0]}),
-	.portbdataout(wire_ram_block3a_7portbdataout[0:0]),
-	.portbrewe(1'b1)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.clr0(1'b0),
-	.clr1(1'b0),
-	.portabyteenamasks(1'b1),
-	.portbbyteenamasks(1'b1),
-	.portbdatain(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		ram_block3a_7.connectivity_checking = "OFF",
-		ram_block3a_7.logical_ram_name = "ALTSYNCRAM",
-		ram_block3a_7.mixed_port_feed_through_mode = "dont_care",
-		ram_block3a_7.operation_mode = "dual_port",
-		ram_block3a_7.port_a_address_width = 12,
-		ram_block3a_7.port_a_data_width = 1,
-		ram_block3a_7.port_a_first_address = 0,
-		ram_block3a_7.port_a_first_bit_number = 7,
-		ram_block3a_7.port_a_last_address = 4095,
-		ram_block3a_7.port_a_logical_ram_depth = 4096,
-		ram_block3a_7.port_a_logical_ram_width = 16,
-		ram_block3a_7.port_b_address_clear = "none",
-		ram_block3a_7.port_b_address_clock = "clock1",
-		ram_block3a_7.port_b_address_width = 12,
-		ram_block3a_7.port_b_data_out_clear = "none",
-		ram_block3a_7.port_b_data_out_clock = "none",
-		ram_block3a_7.port_b_data_width = 1,
-		ram_block3a_7.port_b_first_address = 0,
-		ram_block3a_7.port_b_first_bit_number = 7,
-		ram_block3a_7.port_b_last_address = 4095,
-		ram_block3a_7.port_b_logical_ram_depth = 4096,
-		ram_block3a_7.port_b_logical_ram_width = 16,
-		ram_block3a_7.port_b_read_enable_write_enable_clock = "clock1",
-		ram_block3a_7.ram_block_type = "auto",
-		ram_block3a_7.lpm_type = "cyclone_ram_block";
-	cyclone_ram_block   ram_block3a_8
-	( 
-	.clk0(clock0),
-	.clk1(clock1),
-	.ena0(wren_a),
-	.ena1(clocken1),
-	.portaaddr({address_a_wire[11:0]}),
-	.portadatain({data_a[8]}),
-	.portadataout(),
-	.portawe(1'b1),
-	.portbaddr({address_b_wire[11:0]}),
-	.portbdataout(wire_ram_block3a_8portbdataout[0:0]),
-	.portbrewe(1'b1)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.clr0(1'b0),
-	.clr1(1'b0),
-	.portabyteenamasks(1'b1),
-	.portbbyteenamasks(1'b1),
-	.portbdatain(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		ram_block3a_8.connectivity_checking = "OFF",
-		ram_block3a_8.logical_ram_name = "ALTSYNCRAM",
-		ram_block3a_8.mixed_port_feed_through_mode = "dont_care",
-		ram_block3a_8.operation_mode = "dual_port",
-		ram_block3a_8.port_a_address_width = 12,
-		ram_block3a_8.port_a_data_width = 1,
-		ram_block3a_8.port_a_first_address = 0,
-		ram_block3a_8.port_a_first_bit_number = 8,
-		ram_block3a_8.port_a_last_address = 4095,
-		ram_block3a_8.port_a_logical_ram_depth = 4096,
-		ram_block3a_8.port_a_logical_ram_width = 16,
-		ram_block3a_8.port_b_address_clear = "none",
-		ram_block3a_8.port_b_address_clock = "clock1",
-		ram_block3a_8.port_b_address_width = 12,
-		ram_block3a_8.port_b_data_out_clear = "none",
-		ram_block3a_8.port_b_data_out_clock = "none",
-		ram_block3a_8.port_b_data_width = 1,
-		ram_block3a_8.port_b_first_address = 0,
-		ram_block3a_8.port_b_first_bit_number = 8,
-		ram_block3a_8.port_b_last_address = 4095,
-		ram_block3a_8.port_b_logical_ram_depth = 4096,
-		ram_block3a_8.port_b_logical_ram_width = 16,
-		ram_block3a_8.port_b_read_enable_write_enable_clock = "clock1",
-		ram_block3a_8.ram_block_type = "auto",
-		ram_block3a_8.lpm_type = "cyclone_ram_block";
-	cyclone_ram_block   ram_block3a_9
-	( 
-	.clk0(clock0),
-	.clk1(clock1),
-	.ena0(wren_a),
-	.ena1(clocken1),
-	.portaaddr({address_a_wire[11:0]}),
-	.portadatain({data_a[9]}),
-	.portadataout(),
-	.portawe(1'b1),
-	.portbaddr({address_b_wire[11:0]}),
-	.portbdataout(wire_ram_block3a_9portbdataout[0:0]),
-	.portbrewe(1'b1)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.clr0(1'b0),
-	.clr1(1'b0),
-	.portabyteenamasks(1'b1),
-	.portbbyteenamasks(1'b1),
-	.portbdatain(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		ram_block3a_9.connectivity_checking = "OFF",
-		ram_block3a_9.logical_ram_name = "ALTSYNCRAM",
-		ram_block3a_9.mixed_port_feed_through_mode = "dont_care",
-		ram_block3a_9.operation_mode = "dual_port",
-		ram_block3a_9.port_a_address_width = 12,
-		ram_block3a_9.port_a_data_width = 1,
-		ram_block3a_9.port_a_first_address = 0,
-		ram_block3a_9.port_a_first_bit_number = 9,
-		ram_block3a_9.port_a_last_address = 4095,
-		ram_block3a_9.port_a_logical_ram_depth = 4096,
-		ram_block3a_9.port_a_logical_ram_width = 16,
-		ram_block3a_9.port_b_address_clear = "none",
-		ram_block3a_9.port_b_address_clock = "clock1",
-		ram_block3a_9.port_b_address_width = 12,
-		ram_block3a_9.port_b_data_out_clear = "none",
-		ram_block3a_9.port_b_data_out_clock = "none",
-		ram_block3a_9.port_b_data_width = 1,
-		ram_block3a_9.port_b_first_address = 0,
-		ram_block3a_9.port_b_first_bit_number = 9,
-		ram_block3a_9.port_b_last_address = 4095,
-		ram_block3a_9.port_b_logical_ram_depth = 4096,
-		ram_block3a_9.port_b_logical_ram_width = 16,
-		ram_block3a_9.port_b_read_enable_write_enable_clock = "clock1",
-		ram_block3a_9.ram_block_type = "auto",
-		ram_block3a_9.lpm_type = "cyclone_ram_block";
-	cyclone_ram_block   ram_block3a_10
-	( 
-	.clk0(clock0),
-	.clk1(clock1),
-	.ena0(wren_a),
-	.ena1(clocken1),
-	.portaaddr({address_a_wire[11:0]}),
-	.portadatain({data_a[10]}),
-	.portadataout(),
-	.portawe(1'b1),
-	.portbaddr({address_b_wire[11:0]}),
-	.portbdataout(wire_ram_block3a_10portbdataout[0:0]),
-	.portbrewe(1'b1)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.clr0(1'b0),
-	.clr1(1'b0),
-	.portabyteenamasks(1'b1),
-	.portbbyteenamasks(1'b1),
-	.portbdatain(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		ram_block3a_10.connectivity_checking = "OFF",
-		ram_block3a_10.logical_ram_name = "ALTSYNCRAM",
-		ram_block3a_10.mixed_port_feed_through_mode = "dont_care",
-		ram_block3a_10.operation_mode = "dual_port",
-		ram_block3a_10.port_a_address_width = 12,
-		ram_block3a_10.port_a_data_width = 1,
-		ram_block3a_10.port_a_first_address = 0,
-		ram_block3a_10.port_a_first_bit_number = 10,
-		ram_block3a_10.port_a_last_address = 4095,
-		ram_block3a_10.port_a_logical_ram_depth = 4096,
-		ram_block3a_10.port_a_logical_ram_width = 16,
-		ram_block3a_10.port_b_address_clear = "none",
-		ram_block3a_10.port_b_address_clock = "clock1",
-		ram_block3a_10.port_b_address_width = 12,
-		ram_block3a_10.port_b_data_out_clear = "none",
-		ram_block3a_10.port_b_data_out_clock = "none",
-		ram_block3a_10.port_b_data_width = 1,
-		ram_block3a_10.port_b_first_address = 0,
-		ram_block3a_10.port_b_first_bit_number = 10,
-		ram_block3a_10.port_b_last_address = 4095,
-		ram_block3a_10.port_b_logical_ram_depth = 4096,
-		ram_block3a_10.port_b_logical_ram_width = 16,
-		ram_block3a_10.port_b_read_enable_write_enable_clock = "clock1",
-		ram_block3a_10.ram_block_type = "auto",
-		ram_block3a_10.lpm_type = "cyclone_ram_block";
-	cyclone_ram_block   ram_block3a_11
-	( 
-	.clk0(clock0),
-	.clk1(clock1),
-	.ena0(wren_a),
-	.ena1(clocken1),
-	.portaaddr({address_a_wire[11:0]}),
-	.portadatain({data_a[11]}),
-	.portadataout(),
-	.portawe(1'b1),
-	.portbaddr({address_b_wire[11:0]}),
-	.portbdataout(wire_ram_block3a_11portbdataout[0:0]),
-	.portbrewe(1'b1)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.clr0(1'b0),
-	.clr1(1'b0),
-	.portabyteenamasks(1'b1),
-	.portbbyteenamasks(1'b1),
-	.portbdatain(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		ram_block3a_11.connectivity_checking = "OFF",
-		ram_block3a_11.logical_ram_name = "ALTSYNCRAM",
-		ram_block3a_11.mixed_port_feed_through_mode = "dont_care",
-		ram_block3a_11.operation_mode = "dual_port",
-		ram_block3a_11.port_a_address_width = 12,
-		ram_block3a_11.port_a_data_width = 1,
-		ram_block3a_11.port_a_first_address = 0,
-		ram_block3a_11.port_a_first_bit_number = 11,
-		ram_block3a_11.port_a_last_address = 4095,
-		ram_block3a_11.port_a_logical_ram_depth = 4096,
-		ram_block3a_11.port_a_logical_ram_width = 16,
-		ram_block3a_11.port_b_address_clear = "none",
-		ram_block3a_11.port_b_address_clock = "clock1",
-		ram_block3a_11.port_b_address_width = 12,
-		ram_block3a_11.port_b_data_out_clear = "none",
-		ram_block3a_11.port_b_data_out_clock = "none",
-		ram_block3a_11.port_b_data_width = 1,
-		ram_block3a_11.port_b_first_address = 0,
-		ram_block3a_11.port_b_first_bit_number = 11,
-		ram_block3a_11.port_b_last_address = 4095,
-		ram_block3a_11.port_b_logical_ram_depth = 4096,
-		ram_block3a_11.port_b_logical_ram_width = 16,
-		ram_block3a_11.port_b_read_enable_write_enable_clock = "clock1",
-		ram_block3a_11.ram_block_type = "auto",
-		ram_block3a_11.lpm_type = "cyclone_ram_block";
-	cyclone_ram_block   ram_block3a_12
-	( 
-	.clk0(clock0),
-	.clk1(clock1),
-	.ena0(wren_a),
-	.ena1(clocken1),
-	.portaaddr({address_a_wire[11:0]}),
-	.portadatain({data_a[12]}),
-	.portadataout(),
-	.portawe(1'b1),
-	.portbaddr({address_b_wire[11:0]}),
-	.portbdataout(wire_ram_block3a_12portbdataout[0:0]),
-	.portbrewe(1'b1)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.clr0(1'b0),
-	.clr1(1'b0),
-	.portabyteenamasks(1'b1),
-	.portbbyteenamasks(1'b1),
-	.portbdatain(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		ram_block3a_12.connectivity_checking = "OFF",
-		ram_block3a_12.logical_ram_name = "ALTSYNCRAM",
-		ram_block3a_12.mixed_port_feed_through_mode = "dont_care",
-		ram_block3a_12.operation_mode = "dual_port",
-		ram_block3a_12.port_a_address_width = 12,
-		ram_block3a_12.port_a_data_width = 1,
-		ram_block3a_12.port_a_first_address = 0,
-		ram_block3a_12.port_a_first_bit_number = 12,
-		ram_block3a_12.port_a_last_address = 4095,
-		ram_block3a_12.port_a_logical_ram_depth = 4096,
-		ram_block3a_12.port_a_logical_ram_width = 16,
-		ram_block3a_12.port_b_address_clear = "none",
-		ram_block3a_12.port_b_address_clock = "clock1",
-		ram_block3a_12.port_b_address_width = 12,
-		ram_block3a_12.port_b_data_out_clear = "none",
-		ram_block3a_12.port_b_data_out_clock = "none",
-		ram_block3a_12.port_b_data_width = 1,
-		ram_block3a_12.port_b_first_address = 0,
-		ram_block3a_12.port_b_first_bit_number = 12,
-		ram_block3a_12.port_b_last_address = 4095,
-		ram_block3a_12.port_b_logical_ram_depth = 4096,
-		ram_block3a_12.port_b_logical_ram_width = 16,
-		ram_block3a_12.port_b_read_enable_write_enable_clock = "clock1",
-		ram_block3a_12.ram_block_type = "auto",
-		ram_block3a_12.lpm_type = "cyclone_ram_block";
-	cyclone_ram_block   ram_block3a_13
-	( 
-	.clk0(clock0),
-	.clk1(clock1),
-	.ena0(wren_a),
-	.ena1(clocken1),
-	.portaaddr({address_a_wire[11:0]}),
-	.portadatain({data_a[13]}),
-	.portadataout(),
-	.portawe(1'b1),
-	.portbaddr({address_b_wire[11:0]}),
-	.portbdataout(wire_ram_block3a_13portbdataout[0:0]),
-	.portbrewe(1'b1)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.clr0(1'b0),
-	.clr1(1'b0),
-	.portabyteenamasks(1'b1),
-	.portbbyteenamasks(1'b1),
-	.portbdatain(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		ram_block3a_13.connectivity_checking = "OFF",
-		ram_block3a_13.logical_ram_name = "ALTSYNCRAM",
-		ram_block3a_13.mixed_port_feed_through_mode = "dont_care",
-		ram_block3a_13.operation_mode = "dual_port",
-		ram_block3a_13.port_a_address_width = 12,
-		ram_block3a_13.port_a_data_width = 1,
-		ram_block3a_13.port_a_first_address = 0,
-		ram_block3a_13.port_a_first_bit_number = 13,
-		ram_block3a_13.port_a_last_address = 4095,
-		ram_block3a_13.port_a_logical_ram_depth = 4096,
-		ram_block3a_13.port_a_logical_ram_width = 16,
-		ram_block3a_13.port_b_address_clear = "none",
-		ram_block3a_13.port_b_address_clock = "clock1",
-		ram_block3a_13.port_b_address_width = 12,
-		ram_block3a_13.port_b_data_out_clear = "none",
-		ram_block3a_13.port_b_data_out_clock = "none",
-		ram_block3a_13.port_b_data_width = 1,
-		ram_block3a_13.port_b_first_address = 0,
-		ram_block3a_13.port_b_first_bit_number = 13,
-		ram_block3a_13.port_b_last_address = 4095,
-		ram_block3a_13.port_b_logical_ram_depth = 4096,
-		ram_block3a_13.port_b_logical_ram_width = 16,
-		ram_block3a_13.port_b_read_enable_write_enable_clock = "clock1",
-		ram_block3a_13.ram_block_type = "auto",
-		ram_block3a_13.lpm_type = "cyclone_ram_block";
-	cyclone_ram_block   ram_block3a_14
-	( 
-	.clk0(clock0),
-	.clk1(clock1),
-	.ena0(wren_a),
-	.ena1(clocken1),
-	.portaaddr({address_a_wire[11:0]}),
-	.portadatain({data_a[14]}),
-	.portadataout(),
-	.portawe(1'b1),
-	.portbaddr({address_b_wire[11:0]}),
-	.portbdataout(wire_ram_block3a_14portbdataout[0:0]),
-	.portbrewe(1'b1)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.clr0(1'b0),
-	.clr1(1'b0),
-	.portabyteenamasks(1'b1),
-	.portbbyteenamasks(1'b1),
-	.portbdatain(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		ram_block3a_14.connectivity_checking = "OFF",
-		ram_block3a_14.logical_ram_name = "ALTSYNCRAM",
-		ram_block3a_14.mixed_port_feed_through_mode = "dont_care",
-		ram_block3a_14.operation_mode = "dual_port",
-		ram_block3a_14.port_a_address_width = 12,
-		ram_block3a_14.port_a_data_width = 1,
-		ram_block3a_14.port_a_first_address = 0,
-		ram_block3a_14.port_a_first_bit_number = 14,
-		ram_block3a_14.port_a_last_address = 4095,
-		ram_block3a_14.port_a_logical_ram_depth = 4096,
-		ram_block3a_14.port_a_logical_ram_width = 16,
-		ram_block3a_14.port_b_address_clear = "none",
-		ram_block3a_14.port_b_address_clock = "clock1",
-		ram_block3a_14.port_b_address_width = 12,
-		ram_block3a_14.port_b_data_out_clear = "none",
-		ram_block3a_14.port_b_data_out_clock = "none",
-		ram_block3a_14.port_b_data_width = 1,
-		ram_block3a_14.port_b_first_address = 0,
-		ram_block3a_14.port_b_first_bit_number = 14,
-		ram_block3a_14.port_b_last_address = 4095,
-		ram_block3a_14.port_b_logical_ram_depth = 4096,
-		ram_block3a_14.port_b_logical_ram_width = 16,
-		ram_block3a_14.port_b_read_enable_write_enable_clock = "clock1",
-		ram_block3a_14.ram_block_type = "auto",
-		ram_block3a_14.lpm_type = "cyclone_ram_block";
-	cyclone_ram_block   ram_block3a_15
-	( 
-	.clk0(clock0),
-	.clk1(clock1),
-	.ena0(wren_a),
-	.ena1(clocken1),
-	.portaaddr({address_a_wire[11:0]}),
-	.portadatain({data_a[15]}),
-	.portadataout(),
-	.portawe(1'b1),
-	.portbaddr({address_b_wire[11:0]}),
-	.portbdataout(wire_ram_block3a_15portbdataout[0:0]),
-	.portbrewe(1'b1)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.clr0(1'b0),
-	.clr1(1'b0),
-	.portabyteenamasks(1'b1),
-	.portbbyteenamasks(1'b1),
-	.portbdatain(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		ram_block3a_15.connectivity_checking = "OFF",
-		ram_block3a_15.logical_ram_name = "ALTSYNCRAM",
-		ram_block3a_15.mixed_port_feed_through_mode = "dont_care",
-		ram_block3a_15.operation_mode = "dual_port",
-		ram_block3a_15.port_a_address_width = 12,
-		ram_block3a_15.port_a_data_width = 1,
-		ram_block3a_15.port_a_first_address = 0,
-		ram_block3a_15.port_a_first_bit_number = 15,
-		ram_block3a_15.port_a_last_address = 4095,
-		ram_block3a_15.port_a_logical_ram_depth = 4096,
-		ram_block3a_15.port_a_logical_ram_width = 16,
-		ram_block3a_15.port_b_address_clear = "none",
-		ram_block3a_15.port_b_address_clock = "clock1",
-		ram_block3a_15.port_b_address_width = 12,
-		ram_block3a_15.port_b_data_out_clear = "none",
-		ram_block3a_15.port_b_data_out_clock = "none",
-		ram_block3a_15.port_b_data_width = 1,
-		ram_block3a_15.port_b_first_address = 0,
-		ram_block3a_15.port_b_first_bit_number = 15,
-		ram_block3a_15.port_b_last_address = 4095,
-		ram_block3a_15.port_b_logical_ram_depth = 4096,
-		ram_block3a_15.port_b_logical_ram_width = 16,
-		ram_block3a_15.port_b_read_enable_write_enable_clock = "clock1",
-		ram_block3a_15.ram_block_type = "auto",
-		ram_block3a_15.lpm_type = "cyclone_ram_block";
-	assign
-		address_a_wire = address_a,
-		address_b_wire = address_b,
-		q_b = {wire_ram_block3a_15portbdataout[0], wire_ram_block3a_14portbdataout[0], wire_ram_block3a_13portbdataout[0], wire_ram_block3a_12portbdataout[0], wire_ram_block3a_11portbdataout[0], wire_ram_block3a_10portbdataout[0], wire_ram_block3a_9portbdataout[0], wire_ram_block3a_8portbdataout[0], wire_ram_block3a_7portbdataout[0], wire_ram_block3a_6portbdataout[0], wire_ram_block3a_5portbdataout[0], wire_ram_block3a_4portbdataout[0], wire_ram_block3a_3portbdataout[0], wire_ram_block3a_2portbdataout[0], wire_ram_block3a_1portbdataout[0], wire_ram_block3a_0portbdataout[0]};
-endmodule //fifo_4k_altsyncram_8pl
-
-
-//dffpipe DELAY=1 WIDTH=12 clock clrn d q
-//VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END
-
-//synthesis_resources = lut 12 
-//synopsys translate_off
-`timescale 1 ps / 1 ps
-//synopsys translate_on
-module  fifo_4k_dffpipe_bb3
-	( 
-	clock,
-	clrn,
-	d,
-	q) /* synthesis synthesis_clearbox=1 */
-		/* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */;
-	input   clock;
-	input   clrn;
-	input   [11:0]  d;
-	output   [11:0]  q;
-
-	wire	[11:0]	wire_dffe4a_D;
-	reg	[11:0]	dffe4a;
-	wire ena;
-	wire prn;
-	wire sclr;
-
-	// synopsys translate_off
-	initial
-		dffe4a[0:0] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe4a[0:0] <= 1'b1;
-		else if (clrn == 1'b0) dffe4a[0:0] <= 1'b0;
-		else if  (ena == 1'b1)   dffe4a[0:0] <= wire_dffe4a_D[0:0];
-	// synopsys translate_off
-	initial
-		dffe4a[1:1] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe4a[1:1] <= 1'b1;
-		else if (clrn == 1'b0) dffe4a[1:1] <= 1'b0;
-		else if  (ena == 1'b1)   dffe4a[1:1] <= wire_dffe4a_D[1:1];
-	// synopsys translate_off
-	initial
-		dffe4a[2:2] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe4a[2:2] <= 1'b1;
-		else if (clrn == 1'b0) dffe4a[2:2] <= 1'b0;
-		else if  (ena == 1'b1)   dffe4a[2:2] <= wire_dffe4a_D[2:2];
-	// synopsys translate_off
-	initial
-		dffe4a[3:3] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe4a[3:3] <= 1'b1;
-		else if (clrn == 1'b0) dffe4a[3:3] <= 1'b0;
-		else if  (ena == 1'b1)   dffe4a[3:3] <= wire_dffe4a_D[3:3];
-	// synopsys translate_off
-	initial
-		dffe4a[4:4] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe4a[4:4] <= 1'b1;
-		else if (clrn == 1'b0) dffe4a[4:4] <= 1'b0;
-		else if  (ena == 1'b1)   dffe4a[4:4] <= wire_dffe4a_D[4:4];
-	// synopsys translate_off
-	initial
-		dffe4a[5:5] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe4a[5:5] <= 1'b1;
-		else if (clrn == 1'b0) dffe4a[5:5] <= 1'b0;
-		else if  (ena == 1'b1)   dffe4a[5:5] <= wire_dffe4a_D[5:5];
-	// synopsys translate_off
-	initial
-		dffe4a[6:6] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe4a[6:6] <= 1'b1;
-		else if (clrn == 1'b0) dffe4a[6:6] <= 1'b0;
-		else if  (ena == 1'b1)   dffe4a[6:6] <= wire_dffe4a_D[6:6];
-	// synopsys translate_off
-	initial
-		dffe4a[7:7] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe4a[7:7] <= 1'b1;
-		else if (clrn == 1'b0) dffe4a[7:7] <= 1'b0;
-		else if  (ena == 1'b1)   dffe4a[7:7] <= wire_dffe4a_D[7:7];
-	// synopsys translate_off
-	initial
-		dffe4a[8:8] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe4a[8:8] <= 1'b1;
-		else if (clrn == 1'b0) dffe4a[8:8] <= 1'b0;
-		else if  (ena == 1'b1)   dffe4a[8:8] <= wire_dffe4a_D[8:8];
-	// synopsys translate_off
-	initial
-		dffe4a[9:9] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe4a[9:9] <= 1'b1;
-		else if (clrn == 1'b0) dffe4a[9:9] <= 1'b0;
-		else if  (ena == 1'b1)   dffe4a[9:9] <= wire_dffe4a_D[9:9];
-	// synopsys translate_off
-	initial
-		dffe4a[10:10] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe4a[10:10] <= 1'b1;
-		else if (clrn == 1'b0) dffe4a[10:10] <= 1'b0;
-		else if  (ena == 1'b1)   dffe4a[10:10] <= wire_dffe4a_D[10:10];
-	// synopsys translate_off
-	initial
-		dffe4a[11:11] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe4a[11:11] <= 1'b1;
-		else if (clrn == 1'b0) dffe4a[11:11] <= 1'b0;
-		else if  (ena == 1'b1)   dffe4a[11:11] <= wire_dffe4a_D[11:11];
-	assign
-		wire_dffe4a_D = (d & {12{(~ sclr)}});
-	assign
-		ena = 1'b1,
-		prn = 1'b1,
-		q = dffe4a,
-		sclr = 1'b0;
-endmodule //fifo_4k_dffpipe_bb3
-
-
-//dffpipe WIDTH=12 clock clrn d q
-//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END
-
-
-//dffpipe WIDTH=12 clock clrn d q
-//VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END
-
-//synthesis_resources = lut 12 
-//synopsys translate_off
-`timescale 1 ps / 1 ps
-//synopsys translate_on
-module  fifo_4k_dffpipe_em2
-	( 
-	clock,
-	clrn,
-	d,
-	q) /* synthesis synthesis_clearbox=1 */
-		/* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */;
-	input   clock;
-	input   clrn;
-	input   [11:0]  d;
-	output   [11:0]  q;
-
-	wire	[11:0]	wire_dffe6a_D;
-	reg	[11:0]	dffe6a;
-	wire ena;
-	wire prn;
-	wire sclr;
-
-	// synopsys translate_off
-	initial
-		dffe6a[0:0] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe6a[0:0] <= 1'b1;
-		else if (clrn == 1'b0) dffe6a[0:0] <= 1'b0;
-		else if  (ena == 1'b1)   dffe6a[0:0] <= wire_dffe6a_D[0:0];
-	// synopsys translate_off
-	initial
-		dffe6a[1:1] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe6a[1:1] <= 1'b1;
-		else if (clrn == 1'b0) dffe6a[1:1] <= 1'b0;
-		else if  (ena == 1'b1)   dffe6a[1:1] <= wire_dffe6a_D[1:1];
-	// synopsys translate_off
-	initial
-		dffe6a[2:2] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe6a[2:2] <= 1'b1;
-		else if (clrn == 1'b0) dffe6a[2:2] <= 1'b0;
-		else if  (ena == 1'b1)   dffe6a[2:2] <= wire_dffe6a_D[2:2];
-	// synopsys translate_off
-	initial
-		dffe6a[3:3] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe6a[3:3] <= 1'b1;
-		else if (clrn == 1'b0) dffe6a[3:3] <= 1'b0;
-		else if  (ena == 1'b1)   dffe6a[3:3] <= wire_dffe6a_D[3:3];
-	// synopsys translate_off
-	initial
-		dffe6a[4:4] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe6a[4:4] <= 1'b1;
-		else if (clrn == 1'b0) dffe6a[4:4] <= 1'b0;
-		else if  (ena == 1'b1)   dffe6a[4:4] <= wire_dffe6a_D[4:4];
-	// synopsys translate_off
-	initial
-		dffe6a[5:5] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe6a[5:5] <= 1'b1;
-		else if (clrn == 1'b0) dffe6a[5:5] <= 1'b0;
-		else if  (ena == 1'b1)   dffe6a[5:5] <= wire_dffe6a_D[5:5];
-	// synopsys translate_off
-	initial
-		dffe6a[6:6] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe6a[6:6] <= 1'b1;
-		else if (clrn == 1'b0) dffe6a[6:6] <= 1'b0;
-		else if  (ena == 1'b1)   dffe6a[6:6] <= wire_dffe6a_D[6:6];
-	// synopsys translate_off
-	initial
-		dffe6a[7:7] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe6a[7:7] <= 1'b1;
-		else if (clrn == 1'b0) dffe6a[7:7] <= 1'b0;
-		else if  (ena == 1'b1)   dffe6a[7:7] <= wire_dffe6a_D[7:7];
-	// synopsys translate_off
-	initial
-		dffe6a[8:8] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe6a[8:8] <= 1'b1;
-		else if (clrn == 1'b0) dffe6a[8:8] <= 1'b0;
-		else if  (ena == 1'b1)   dffe6a[8:8] <= wire_dffe6a_D[8:8];
-	// synopsys translate_off
-	initial
-		dffe6a[9:9] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe6a[9:9] <= 1'b1;
-		else if (clrn == 1'b0) dffe6a[9:9] <= 1'b0;
-		else if  (ena == 1'b1)   dffe6a[9:9] <= wire_dffe6a_D[9:9];
-	// synopsys translate_off
-	initial
-		dffe6a[10:10] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe6a[10:10] <= 1'b1;
-		else if (clrn == 1'b0) dffe6a[10:10] <= 1'b0;
-		else if  (ena == 1'b1)   dffe6a[10:10] <= wire_dffe6a_D[10:10];
-	// synopsys translate_off
-	initial
-		dffe6a[11:11] = 0;
-	// synopsys translate_on
-	always @ ( posedge clock or  negedge prn or  negedge clrn)
-		if (prn == 1'b0) dffe6a[11:11] <= 1'b1;
-		else if (clrn == 1'b0) dffe6a[11:11] <= 1'b0;
-		else if  (ena == 1'b1)   dffe6a[11:11] <= wire_dffe6a_D[11:11];
-	assign
-		wire_dffe6a_D = (d & {12{(~ sclr)}});
-	assign
-		ena = 1'b1,
-		prn = 1'b1,
-		q = dffe6a,
-		sclr = 1'b0;
-endmodule //fifo_4k_dffpipe_em2
-
-//synthesis_resources = lut 12 
-//synopsys translate_off
-`timescale 1 ps / 1 ps
-//synopsys translate_on
-module  fifo_4k_alt_synch_pipe_em2
-	( 
-	clock,
-	clrn,
-	d,
-	q) /* synthesis synthesis_clearbox=1 */
-		/* synthesis ALTERA_ATTRIBUTE="X_ON_VIOLATION_OPTION=OFF" */;
-	input   clock;
-	input   clrn;
-	input   [11:0]  d;
-	output   [11:0]  q;
-
-	wire  [11:0]   wire_dffpipe5_q;
-
-	fifo_4k_dffpipe_em2   dffpipe5
-	( 
-	.clock(clock),
-	.clrn(clrn),
-	.d(d),
-	.q(wire_dffpipe5_q));
-	assign
-		q = wire_dffpipe5_q;
-endmodule //fifo_4k_alt_synch_pipe_em2
-
-
-//lpm_add_sub DEVICE_FAMILY="Cyclone" LPM_DIRECTION="SUB" LPM_WIDTH=12 dataa datab result
-//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END
-
-//synthesis_resources = lut 12 
-//synopsys translate_off
-`timescale 1 ps / 1 ps
-//synopsys translate_on
-module  fifo_4k_add_sub_b18
-	( 
-	dataa,
-	datab,
-	result) /* synthesis synthesis_clearbox=1 */;
-	input   [11:0]  dataa;
-	input   [11:0]  datab;
-	output   [11:0]  result;
-
-	wire  [11:0]   wire_add_sub_cella_combout;
-	wire  [0:0]   wire_add_sub_cella_0cout;
-	wire  [0:0]   wire_add_sub_cella_1cout;
-	wire  [0:0]   wire_add_sub_cella_2cout;
-	wire  [0:0]   wire_add_sub_cella_3cout;
-	wire  [0:0]   wire_add_sub_cella_4cout;
-	wire  [0:0]   wire_add_sub_cella_5cout;
-	wire  [0:0]   wire_add_sub_cella_6cout;
-	wire  [0:0]   wire_add_sub_cella_7cout;
-	wire  [0:0]   wire_add_sub_cella_8cout;
-	wire  [0:0]   wire_add_sub_cella_9cout;
-	wire  [0:0]   wire_add_sub_cella_10cout;
-	wire  [11:0]   wire_add_sub_cella_dataa;
-	wire  [11:0]   wire_add_sub_cella_datab;
-
-	cyclone_lcell   add_sub_cella_0
-	( 
-	.cin(1'b1),
-	.combout(wire_add_sub_cella_combout[0:0]),
-	.cout(wire_add_sub_cella_0cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[0:0]),
-	.datab(wire_add_sub_cella_datab[0:0]),
-	.regout()
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aclr(1'b0),
-	.aload(1'b0),
-	.clk(1'b1),
-	.datac(1'b1),
-	.datad(1'b1),
-	.ena(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sclr(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		add_sub_cella_0.cin_used = "true",
-		add_sub_cella_0.lut_mask = "69b2",
-		add_sub_cella_0.operation_mode = "arithmetic",
-		add_sub_cella_0.sum_lutc_input = "cin",
-		add_sub_cella_0.lpm_type = "cyclone_lcell";
-	cyclone_lcell   add_sub_cella_1
-	( 
-	.cin(wire_add_sub_cella_0cout[0:0]),
-	.combout(wire_add_sub_cella_combout[1:1]),
-	.cout(wire_add_sub_cella_1cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[1:1]),
-	.datab(wire_add_sub_cella_datab[1:1]),
-	.regout()
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aclr(1'b0),
-	.aload(1'b0),
-	.clk(1'b1),
-	.datac(1'b1),
-	.datad(1'b1),
-	.ena(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sclr(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		add_sub_cella_1.cin_used = "true",
-		add_sub_cella_1.lut_mask = "69b2",
-		add_sub_cella_1.operation_mode = "arithmetic",
-		add_sub_cella_1.sum_lutc_input = "cin",
-		add_sub_cella_1.lpm_type = "cyclone_lcell";
-	cyclone_lcell   add_sub_cella_2
-	( 
-	.cin(wire_add_sub_cella_1cout[0:0]),
-	.combout(wire_add_sub_cella_combout[2:2]),
-	.cout(wire_add_sub_cella_2cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[2:2]),
-	.datab(wire_add_sub_cella_datab[2:2]),
-	.regout()
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aclr(1'b0),
-	.aload(1'b0),
-	.clk(1'b1),
-	.datac(1'b1),
-	.datad(1'b1),
-	.ena(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sclr(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		add_sub_cella_2.cin_used = "true",
-		add_sub_cella_2.lut_mask = "69b2",
-		add_sub_cella_2.operation_mode = "arithmetic",
-		add_sub_cella_2.sum_lutc_input = "cin",
-		add_sub_cella_2.lpm_type = "cyclone_lcell";
-	cyclone_lcell   add_sub_cella_3
-	( 
-	.cin(wire_add_sub_cella_2cout[0:0]),
-	.combout(wire_add_sub_cella_combout[3:3]),
-	.cout(wire_add_sub_cella_3cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[3:3]),
-	.datab(wire_add_sub_cella_datab[3:3]),
-	.regout()
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aclr(1'b0),
-	.aload(1'b0),
-	.clk(1'b1),
-	.datac(1'b1),
-	.datad(1'b1),
-	.ena(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sclr(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		add_sub_cella_3.cin_used = "true",
-		add_sub_cella_3.lut_mask = "69b2",
-		add_sub_cella_3.operation_mode = "arithmetic",
-		add_sub_cella_3.sum_lutc_input = "cin",
-		add_sub_cella_3.lpm_type = "cyclone_lcell";
-	cyclone_lcell   add_sub_cella_4
-	( 
-	.cin(wire_add_sub_cella_3cout[0:0]),
-	.combout(wire_add_sub_cella_combout[4:4]),
-	.cout(wire_add_sub_cella_4cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[4:4]),
-	.datab(wire_add_sub_cella_datab[4:4]),
-	.regout()
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aclr(1'b0),
-	.aload(1'b0),
-	.clk(1'b1),
-	.datac(1'b1),
-	.datad(1'b1),
-	.ena(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sclr(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		add_sub_cella_4.cin_used = "true",
-		add_sub_cella_4.lut_mask = "69b2",
-		add_sub_cella_4.operation_mode = "arithmetic",
-		add_sub_cella_4.sum_lutc_input = "cin",
-		add_sub_cella_4.lpm_type = "cyclone_lcell";
-	cyclone_lcell   add_sub_cella_5
-	( 
-	.cin(wire_add_sub_cella_4cout[0:0]),
-	.combout(wire_add_sub_cella_combout[5:5]),
-	.cout(wire_add_sub_cella_5cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[5:5]),
-	.datab(wire_add_sub_cella_datab[5:5]),
-	.regout()
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aclr(1'b0),
-	.aload(1'b0),
-	.clk(1'b1),
-	.datac(1'b1),
-	.datad(1'b1),
-	.ena(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sclr(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		add_sub_cella_5.cin_used = "true",
-		add_sub_cella_5.lut_mask = "69b2",
-		add_sub_cella_5.operation_mode = "arithmetic",
-		add_sub_cella_5.sum_lutc_input = "cin",
-		add_sub_cella_5.lpm_type = "cyclone_lcell";
-	cyclone_lcell   add_sub_cella_6
-	( 
-	.cin(wire_add_sub_cella_5cout[0:0]),
-	.combout(wire_add_sub_cella_combout[6:6]),
-	.cout(wire_add_sub_cella_6cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[6:6]),
-	.datab(wire_add_sub_cella_datab[6:6]),
-	.regout()
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aclr(1'b0),
-	.aload(1'b0),
-	.clk(1'b1),
-	.datac(1'b1),
-	.datad(1'b1),
-	.ena(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sclr(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		add_sub_cella_6.cin_used = "true",
-		add_sub_cella_6.lut_mask = "69b2",
-		add_sub_cella_6.operation_mode = "arithmetic",
-		add_sub_cella_6.sum_lutc_input = "cin",
-		add_sub_cella_6.lpm_type = "cyclone_lcell";
-	cyclone_lcell   add_sub_cella_7
-	( 
-	.cin(wire_add_sub_cella_6cout[0:0]),
-	.combout(wire_add_sub_cella_combout[7:7]),
-	.cout(wire_add_sub_cella_7cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[7:7]),
-	.datab(wire_add_sub_cella_datab[7:7]),
-	.regout()
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aclr(1'b0),
-	.aload(1'b0),
-	.clk(1'b1),
-	.datac(1'b1),
-	.datad(1'b1),
-	.ena(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sclr(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		add_sub_cella_7.cin_used = "true",
-		add_sub_cella_7.lut_mask = "69b2",
-		add_sub_cella_7.operation_mode = "arithmetic",
-		add_sub_cella_7.sum_lutc_input = "cin",
-		add_sub_cella_7.lpm_type = "cyclone_lcell";
-	cyclone_lcell   add_sub_cella_8
-	( 
-	.cin(wire_add_sub_cella_7cout[0:0]),
-	.combout(wire_add_sub_cella_combout[8:8]),
-	.cout(wire_add_sub_cella_8cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[8:8]),
-	.datab(wire_add_sub_cella_datab[8:8]),
-	.regout()
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aclr(1'b0),
-	.aload(1'b0),
-	.clk(1'b1),
-	.datac(1'b1),
-	.datad(1'b1),
-	.ena(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sclr(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		add_sub_cella_8.cin_used = "true",
-		add_sub_cella_8.lut_mask = "69b2",
-		add_sub_cella_8.operation_mode = "arithmetic",
-		add_sub_cella_8.sum_lutc_input = "cin",
-		add_sub_cella_8.lpm_type = "cyclone_lcell";
-	cyclone_lcell   add_sub_cella_9
-	( 
-	.cin(wire_add_sub_cella_8cout[0:0]),
-	.combout(wire_add_sub_cella_combout[9:9]),
-	.cout(wire_add_sub_cella_9cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[9:9]),
-	.datab(wire_add_sub_cella_datab[9:9]),
-	.regout()
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aclr(1'b0),
-	.aload(1'b0),
-	.clk(1'b1),
-	.datac(1'b1),
-	.datad(1'b1),
-	.ena(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sclr(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		add_sub_cella_9.cin_used = "true",
-		add_sub_cella_9.lut_mask = "69b2",
-		add_sub_cella_9.operation_mode = "arithmetic",
-		add_sub_cella_9.sum_lutc_input = "cin",
-		add_sub_cella_9.lpm_type = "cyclone_lcell";
-	cyclone_lcell   add_sub_cella_10
-	( 
-	.cin(wire_add_sub_cella_9cout[0:0]),
-	.combout(wire_add_sub_cella_combout[10:10]),
-	.cout(wire_add_sub_cella_10cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[10:10]),
-	.datab(wire_add_sub_cella_datab[10:10]),
-	.regout()
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aclr(1'b0),
-	.aload(1'b0),
-	.clk(1'b1),
-	.datac(1'b1),
-	.datad(1'b1),
-	.ena(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sclr(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		add_sub_cella_10.cin_used = "true",
-		add_sub_cella_10.lut_mask = "69b2",
-		add_sub_cella_10.operation_mode = "arithmetic",
-		add_sub_cella_10.sum_lutc_input = "cin",
-		add_sub_cella_10.lpm_type = "cyclone_lcell";
-	cyclone_lcell   add_sub_cella_11
-	( 
-	.cin(wire_add_sub_cella_10cout[0:0]),
-	.combout(wire_add_sub_cella_combout[11:11]),
-	.cout(),
-	.dataa(wire_add_sub_cella_dataa[11:11]),
-	.datab(wire_add_sub_cella_datab[11:11]),
-	.regout()
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_off
-	`endif
-	,
-	.aclr(1'b0),
-	.aload(1'b0),
-	.clk(1'b1),
-	.datac(1'b1),
-	.datad(1'b1),
-	.ena(1'b1),
-	.inverta(1'b0),
-	.regcascin(1'b0),
-	.sclr(1'b0),
-	.sload(1'b0)
-	`ifdef FORMAL_VERIFICATION
-	`else
-	// synopsys translate_on
-	`endif
-	// synopsys translate_off
-	,
-	.cin0(),
-	.cin1(),
-	.cout0(),
-	.cout1(),
-	.devclrn(),
-	.devpor()
-	// synopsys translate_on
-	);
-	defparam
-		add_sub_cella_11.cin_used = "true",
-		add_sub_cella_11.lut_mask = "6969",
-		add_sub_cella_11.operation_mode = "normal",
-		add_sub_cella_11.sum_lutc_input = "cin",
-		add_sub_cella_11.lpm_type = "cyclone_lcell";
-	assign
-		wire_add_sub_cella_dataa = dataa,
-		wire_add_sub_cella_datab = datab;
-	assign
-		result = wire_add_sub_cella_combout;
-endmodule //fifo_4k_add_sub_b18
-
-
-//lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=12 aeb dataa datab
-//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END
-
-
-//lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=12 aeb dataa datab
-//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END
-
-//synthesis_resources = lut 104 M4K 16 
-//synopsys translate_off
-`timescale 1 ps / 1 ps
-//synopsys translate_on
-module  fifo_4k_dcfifo_6cq
-	( 
-	aclr,
-	data,
-	q,
-	rdclk,
-	rdempty,
-	rdreq,
-	rdusedw,
-	wrclk,
-	wrfull,
-	wrreq,
-	wrusedw) /* synthesis synthesis_clearbox=1 */
-		/* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF;{ -from \"rdptr_g|power_modified_counter_values\" -to \"ws_dgrp|dffpipe5|dffe6a\" }CUT=ON;{ -from \"delayed_wrptr_g\" -to \"rs_dgwp|dffpipe5|dffe6a\" }CUT=ON" */;
-	input   aclr;
-	input   [15:0]  data;
-	output   [15:0]  q;
-	input   rdclk;
-	output   rdempty;
-	input   rdreq;
-	output   [11:0]  rdusedw;
-	input   wrclk;
-	output   wrfull;
-	input   wrreq;
-	output   [11:0]  wrusedw;
-
-	wire  [11:0]   wire_rdptr_g_gray2bin_bin;
-	wire  [11:0]   wire_rs_dgwp_gray2bin_bin;
-	wire  [11:0]   wire_wrptr_g_gray2bin_bin;
-	wire  [11:0]   wire_ws_dgrp_gray2bin_bin;
-	wire  [11:0]   wire_rdptr_g_q;
-	wire  [11:0]   wire_rdptr_g1p_q;
-	wire  [11:0]   wire_wrptr_g1p_q;
-	wire  [15:0]   wire_fifo_ram_q_b;
-	reg	[11:0]	delayed_wrptr_g;
-	reg	[11:0]	wrptr_g;
-	wire  [11:0]   wire_rs_brp_q;
-	wire  [11:0]   wire_rs_bwp_q;
-	wire  [11:0]   wire_rs_dgwp_q;
-	wire  [11:0]   wire_ws_brp_q;
-	wire  [11:0]   wire_ws_bwp_q;
-	wire  [11:0]   wire_ws_dgrp_q;
-	wire  [11:0]   wire_rdusedw_sub_result;
-	wire  [11:0]   wire_wrusedw_sub_result;
-	reg	wire_rdempty_eq_comp_aeb_int;
-	wire	wire_rdempty_eq_comp_aeb;
-	wire	[11:0]	wire_rdempty_eq_comp_dataa;
-	wire	[11:0]	wire_rdempty_eq_comp_datab;
-	reg	wire_wrfull_eq_comp_aeb_int;
-	wire	wire_wrfull_eq_comp_aeb;
-	wire	[11:0]	wire_wrfull_eq_comp_dataa;
-	wire	[11:0]	wire_wrfull_eq_comp_datab;
-	wire  int_rdempty;
-	wire  int_wrfull;
-	wire  valid_rdreq;
-	wire  valid_wrreq;
-
-	fifo_4k_a_gray2bin_9m4   rdptr_g_gray2bin
-	( 
-	.bin(wire_rdptr_g_gray2bin_bin),
-	.gray(wire_rdptr_g_q));
-	fifo_4k_a_gray2bin_9m4   rs_dgwp_gray2bin
-	( 
-	.bin(wire_rs_dgwp_gray2bin_bin),
-	.gray(wire_rs_dgwp_q));
-	fifo_4k_a_gray2bin_9m4   wrptr_g_gray2bin
-	( 
-	.bin(wire_wrptr_g_gray2bin_bin),
-	.gray(wrptr_g));
-	fifo_4k_a_gray2bin_9m4   ws_dgrp_gray2bin
-	( 
-	.bin(wire_ws_dgrp_gray2bin_bin),
-	.gray(wire_ws_dgrp_q));
-	fifo_4k_a_graycounter_826   rdptr_g
-	( 
-	.aclr(aclr),
-	.clock(rdclk),
-	.cnt_en(valid_rdreq),
-	.q(wire_rdptr_g_q));
-	fifo_4k_a_graycounter_3r6   rdptr_g1p
-	( 
-	.aclr(aclr),
-	.clock(rdclk),
-	.cnt_en(valid_rdreq),
-	.q(wire_rdptr_g1p_q));
-	fifo_4k_a_graycounter_3r6   wrptr_g1p
-	( 
-	.aclr(aclr),
-	.clock(wrclk),
-	.cnt_en(valid_wrreq),
-	.q(wire_wrptr_g1p_q));
-	fifo_4k_altsyncram_8pl   fifo_ram
-	( 
-	.address_a(wrptr_g),
-	.address_b(((wire_rdptr_g_q & {12{int_rdempty}}) | (wire_rdptr_g1p_q & {12{(~ int_rdempty)}}))),
-	.clock0(wrclk),
-	.clock1(rdclk),
-	.clocken1((valid_rdreq | int_rdempty)),
-	.data_a(data),
-	.q_b(wire_fifo_ram_q_b),
-	.wren_a(valid_wrreq));
-	// synopsys translate_off
-	initial
-		delayed_wrptr_g = 0;
-	// synopsys translate_on
-	always @ ( posedge wrclk or  posedge aclr)
-		if (aclr == 1'b1) delayed_wrptr_g <= 12'b0;
-		else  delayed_wrptr_g <= wrptr_g;
-	// synopsys translate_off
-	initial
-		wrptr_g = 0;
-	// synopsys translate_on
-	always @ ( posedge wrclk or  posedge aclr)
-		if (aclr == 1'b1) wrptr_g <= 12'b0;
-		else if  (valid_wrreq == 1'b1)   wrptr_g <= wire_wrptr_g1p_q;
-	fifo_4k_dffpipe_bb3   rs_brp
-	( 
-	.clock(rdclk),
-	.clrn((~ aclr)),
-	.d(wire_rdptr_g_gray2bin_bin),
-	.q(wire_rs_brp_q));
-	fifo_4k_dffpipe_bb3   rs_bwp
-	( 
-	.clock(rdclk),
-	.clrn((~ aclr)),
-	.d(wire_rs_dgwp_gray2bin_bin),
-	.q(wire_rs_bwp_q));
-	fifo_4k_alt_synch_pipe_em2   rs_dgwp
-	( 
-	.clock(rdclk),
-	.clrn((~ aclr)),
-	.d(delayed_wrptr_g),
-	.q(wire_rs_dgwp_q));
-	fifo_4k_dffpipe_bb3   ws_brp
-	( 
-	.clock(wrclk),
-	.clrn((~ aclr)),
-	.d(wire_ws_dgrp_gray2bin_bin),
-	.q(wire_ws_brp_q));
-	fifo_4k_dffpipe_bb3   ws_bwp
-	( 
-	.clock(wrclk),
-	.clrn((~ aclr)),
-	.d(wire_wrptr_g_gray2bin_bin),
-	.q(wire_ws_bwp_q));
-	fifo_4k_alt_synch_pipe_em2   ws_dgrp
-	( 
-	.clock(wrclk),
-	.clrn((~ aclr)),
-	.d(wire_rdptr_g_q),
-	.q(wire_ws_dgrp_q));
-	fifo_4k_add_sub_b18   rdusedw_sub
-	( 
-	.dataa(wire_rs_bwp_q),
-	.datab(wire_rs_brp_q),
-	.result(wire_rdusedw_sub_result));
-	fifo_4k_add_sub_b18   wrusedw_sub
-	( 
-	.dataa(wire_ws_bwp_q),
-	.datab(wire_ws_brp_q),
-	.result(wire_wrusedw_sub_result));
-	always @(wire_rdempty_eq_comp_dataa or wire_rdempty_eq_comp_datab)
-		if (wire_rdempty_eq_comp_dataa == wire_rdempty_eq_comp_datab) 
-			begin
-				wire_rdempty_eq_comp_aeb_int = 1'b1;
-			end
-		else
-			begin
-				wire_rdempty_eq_comp_aeb_int = 1'b0;
-			end
-	assign
-		wire_rdempty_eq_comp_aeb = wire_rdempty_eq_comp_aeb_int;
-	assign
-		wire_rdempty_eq_comp_dataa = wire_rs_dgwp_q,
-		wire_rdempty_eq_comp_datab = wire_rdptr_g_q;
-	always @(wire_wrfull_eq_comp_dataa or wire_wrfull_eq_comp_datab)
-		if (wire_wrfull_eq_comp_dataa == wire_wrfull_eq_comp_datab) 
-			begin
-				wire_wrfull_eq_comp_aeb_int = 1'b1;
-			end
-		else
-			begin
-				wire_wrfull_eq_comp_aeb_int = 1'b0;
-			end
-	assign
-		wire_wrfull_eq_comp_aeb = wire_wrfull_eq_comp_aeb_int;
-	assign
-		wire_wrfull_eq_comp_dataa = wire_ws_dgrp_q,
-		wire_wrfull_eq_comp_datab = wire_wrptr_g1p_q;
-	assign
-		int_rdempty = wire_rdempty_eq_comp_aeb,
-		int_wrfull = wire_wrfull_eq_comp_aeb,
-		q = wire_fifo_ram_q_b,
-		rdempty = int_rdempty,
-		rdusedw = wire_rdusedw_sub_result,
-		valid_rdreq = rdreq,
-		valid_wrreq = wrreq,
-		wrfull = int_wrfull,
-		wrusedw = wire_wrusedw_sub_result;
-endmodule //fifo_4k_dcfifo_6cq
-//VALID FILE
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module fifo_4k (
-	data,
-	wrreq,
-	rdreq,
-	rdclk,
-	wrclk,
-	aclr,
-	q,
-	rdempty,
-	rdusedw,
-	wrfull,
-	wrusedw)/* synthesis synthesis_clearbox = 1 */;
-
-	input	[15:0]  data;
-	input	  wrreq;
-	input	  rdreq;
-	input	  rdclk;
-	input	  wrclk;
-	input	  aclr;
-	output	[15:0]  q;
-	output	  rdempty;
-	output	[11:0]  rdusedw;
-	output	  wrfull;
-	output	[11:0]  wrusedw;
-
-	wire  sub_wire0;
-	wire [11:0] sub_wire1;
-	wire  sub_wire2;
-	wire [15:0] sub_wire3;
-	wire [11:0] sub_wire4;
-	wire  rdempty = sub_wire0;
-	wire [11:0] wrusedw = sub_wire1[11:0];
-	wire  wrfull = sub_wire2;
-	wire [15:0] q = sub_wire3[15:0];
-	wire [11:0] rdusedw = sub_wire4[11:0];
-
-	fifo_4k_dcfifo_6cq	fifo_4k_dcfifo_6cq_component (
-				.wrclk (wrclk),
-				.rdreq (rdreq),
-				.aclr (aclr),
-				.rdclk (rdclk),
-				.wrreq (wrreq),
-				.data (data),
-				.rdempty (sub_wire0),
-				.wrusedw (sub_wire1),
-				.wrfull (sub_wire2),
-				.q (sub_wire3),
-				.rdusedw (sub_wire4));
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: Width NUMERIC "16"
-// Retrieval info: PRIVATE: Depth NUMERIC "4096"
-// Retrieval info: PRIVATE: Clock NUMERIC "4"
-// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-// Retrieval info: PRIVATE: Full NUMERIC "1"
-// Retrieval info: PRIVATE: Empty NUMERIC "1"
-// Retrieval info: PRIVATE: UsedW NUMERIC "1"
-// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-// Retrieval info: PRIVATE: rsFull NUMERIC "0"
-// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
-// Retrieval info: PRIVATE: wsFull NUMERIC "1"
-// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
-// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
-// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
-// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-// Retrieval info: PRIVATE: Optimize NUMERIC "2"
-// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
-// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
-// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
-// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
-// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
-// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
-// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
-// Retrieval info: CONSTANT: USE_EAB STRING "ON"
-// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
-// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
-// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
-// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
-// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
-// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
-// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
-// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]
-// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
-// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]
-// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
-// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
-// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
-// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
-// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
-// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
-// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0
-// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
-// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0
-// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_bb.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_waveforms.html TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_wave*.jpg FALSE
diff --git a/fpga/usrp1/megacells/fifo_4k_18.v b/fpga/usrp1/megacells/fifo_4k_18.v
deleted file mode 100755
index ad76121bb..000000000
--- a/fpga/usrp1/megacells/fifo_4k_18.v
+++ /dev/null
@@ -1,186 +0,0 @@
-// megafunction wizard: %FIFO%

-// GENERATION: STANDARD

-// VERSION: WM1.0

-// MODULE: dcfifo 

-

-// ============================================================

-// File Name: fifo_4k_18.v

-// Megafunction Name(s):

-// 			dcfifo

-//

-// Simulation Library Files(s):

-// 			altera_mf

-// ============================================================

-// ************************************************************

-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!

-//

-// 7.1 Build 178 06/25/2007 SP 1 SJ Web Edition

-// ************************************************************

-

-

-//Copyright (C) 1991-2007 Altera Corporation

-//Your use of Altera Corporation's design tools, logic functions 

-//and other software and tools, and its AMPP partner logic 

-//functions, and any output files from any of the foregoing 

-//(including device programming or simulation files), and any 

-//associated documentation or information are expressly subject 

-//to the terms and conditions of the Altera Program License 

-//Subscription Agreement, Altera MegaCore Function License 

-//Agreement, or other applicable license agreement, including, 

-//without limitation, that your use is for the sole purpose of 

-//programming logic devices manufactured by Altera and sold by 

-//Altera or its authorized distributors.  Please refer to the 

-//applicable agreement for further details.

-

-

-// synopsys translate_off

-`timescale 1 ps / 1 ps

-// synopsys translate_on

-module fifo_4k_18 (

-	aclr,

-	data,

-	rdclk,

-	rdreq,

-	wrclk,

-	wrreq,

-	q,

-	rdempty,

-	rdusedw,

-	wrfull,

-	wrusedw);

-

-	input	  aclr;

-	input	[17:0]  data;

-	input	  rdclk;

-	input	  rdreq;

-	input	  wrclk;

-	input	  wrreq;

-	output	[17:0]  q;

-	output	  rdempty;

-	output	[11:0]  rdusedw;

-	output	  wrfull;

-	output	[11:0]  wrusedw;

-

-	wire  sub_wire0;

-	wire [11:0] sub_wire1;

-	wire  sub_wire2;

-	wire [17:0] sub_wire3;

-	wire [11:0] sub_wire4;

-	wire  rdempty = sub_wire0;

-	wire [11:0] wrusedw = sub_wire1[11:0];

-	wire  wrfull = sub_wire2;

-	wire [17:0] q = sub_wire3[17:0];

-	wire [11:0] rdusedw = sub_wire4[11:0];

-

-	dcfifo	dcfifo_component (

-				.wrclk (wrclk),

-				.rdreq (rdreq),

-				.aclr (aclr),

-				.rdclk (rdclk),

-				.wrreq (wrreq),

-				.data (data),

-				.rdempty (sub_wire0),

-				.wrusedw (sub_wire1),

-				.wrfull (sub_wire2),

-				.q (sub_wire3),

-				.rdusedw (sub_wire4)

-				// synopsys translate_off

-				,

-				.rdfull (),

-				.wrempty ()

-				// synopsys translate_on

-				);

-	defparam

-		dcfifo_component.add_ram_output_register = "OFF",

-		dcfifo_component.clocks_are_synchronized = "FALSE",

-		dcfifo_component.intended_device_family = "Cyclone",

-		dcfifo_component.lpm_numwords = 4096,

-		dcfifo_component.lpm_showahead = "ON",

-		dcfifo_component.lpm_type = "dcfifo",

-		dcfifo_component.lpm_width = 18,

-		dcfifo_component.lpm_widthu = 12,

-		dcfifo_component.overflow_checking = "OFF",

-		dcfifo_component.underflow_checking = "OFF",

-		dcfifo_component.use_eab = "ON";

-

-

-endmodule

-

-// ============================================================

-// CNX file retrieval info

-// ============================================================

-// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"

-// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"

-// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"

-// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"

-// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"

-// Retrieval info: PRIVATE: Clock NUMERIC "4"

-// Retrieval info: PRIVATE: Depth NUMERIC "4096"

-// Retrieval info: PRIVATE: Empty NUMERIC "1"

-// Retrieval info: PRIVATE: Full NUMERIC "1"

-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"

-// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"

-// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"

-// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"

-// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"

-// Retrieval info: PRIVATE: Optimize NUMERIC "2"

-// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"

-// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"

-// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"

-// Retrieval info: PRIVATE: UsedW NUMERIC "1"

-// Retrieval info: PRIVATE: Width NUMERIC "18"

-// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"

-// Retrieval info: PRIVATE: diff_widths NUMERIC "0"

-// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"

-// Retrieval info: PRIVATE: output_width NUMERIC "18"

-// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"

-// Retrieval info: PRIVATE: rsFull NUMERIC "0"

-// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"

-// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"

-// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"

-// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"

-// Retrieval info: PRIVATE: wsFull NUMERIC "1"

-// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"

-// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"

-// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"

-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"

-// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"

-// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"

-// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"

-// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "18"

-// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"

-// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"

-// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"

-// Retrieval info: CONSTANT: USE_EAB STRING "ON"

-// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr

-// Retrieval info: USED_PORT: data 0 0 18 0 INPUT NODEFVAL data[17..0]

-// Retrieval info: USED_PORT: q 0 0 18 0 OUTPUT NODEFVAL q[17..0]

-// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk

-// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty

-// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq

-// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]

-// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk

-// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull

-// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq

-// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]

-// Retrieval info: CONNECT: @data 0 0 18 0 data 0 0 18 0

-// Retrieval info: CONNECT: q 0 0 18 0 @q 0 0 18 0

-// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0

-// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0

-// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0

-// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0

-// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0

-// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0

-// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0

-// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0

-// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0

-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all

-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.v TRUE

-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.inc FALSE

-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.cmp FALSE

-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.bsf FALSE

-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_inst.v FALSE

-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_bb.v FALSE

-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_waveforms.html FALSE

-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_wave*.jpg FALSE

-// Retrieval info: LIB_FILE: altera_mf

diff --git a/fpga/usrp1/megacells/fifo_4k_bb.v b/fpga/usrp1/megacells/fifo_4k_bb.v
deleted file mode 100644
index fc4ca9797..000000000
--- a/fpga/usrp1/megacells/fifo_4k_bb.v
+++ /dev/null
@@ -1,131 +0,0 @@
-// megafunction wizard: %FIFO%VBB%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: dcfifo 
-
-// ============================================================
-// File Name: fifo_4k.v
-// Megafunction Name(s):
-// 			dcfifo
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition
-// ************************************************************
-
-//Copyright (C) 1991-2005 Altera Corporation
-//Your use of Altera Corporation's design tools, logic functions 
-//and other software and tools, and its AMPP partner logic       
-//functions, and any output files any of the foregoing           
-//(including device programming or simulation files), and any    
-//associated documentation or information are expressly subject  
-//to the terms and conditions of the Altera Program License      
-//Subscription Agreement, Altera MegaCore Function License       
-//Agreement, or other applicable license agreement, including,   
-//without limitation, that your use is for the sole purpose of   
-//programming logic devices manufactured by Altera and sold by   
-//Altera or its authorized distributors.  Please refer to the    
-//applicable agreement for further details.
-
-module fifo_4k (
-	data,
-	wrreq,
-	rdreq,
-	rdclk,
-	wrclk,
-	aclr,
-	q,
-	rdempty,
-	rdusedw,
-	wrfull,
-	wrusedw)/* synthesis synthesis_clearbox = 1 */;
-
-	input	[15:0]  data;
-	input	  wrreq;
-	input	  rdreq;
-	input	  rdclk;
-	input	  wrclk;
-	input	  aclr;
-	output	[15:0]  q;
-	output	  rdempty;
-	output	[11:0]  rdusedw;
-	output	  wrfull;
-	output	[11:0]  wrusedw;
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: Width NUMERIC "16"
-// Retrieval info: PRIVATE: Depth NUMERIC "4096"
-// Retrieval info: PRIVATE: Clock NUMERIC "4"
-// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-// Retrieval info: PRIVATE: Full NUMERIC "1"
-// Retrieval info: PRIVATE: Empty NUMERIC "1"
-// Retrieval info: PRIVATE: UsedW NUMERIC "1"
-// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-// Retrieval info: PRIVATE: rsFull NUMERIC "0"
-// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
-// Retrieval info: PRIVATE: wsFull NUMERIC "1"
-// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
-// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
-// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
-// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-// Retrieval info: PRIVATE: Optimize NUMERIC "2"
-// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
-// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
-// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
-// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
-// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
-// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
-// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
-// Retrieval info: CONSTANT: USE_EAB STRING "ON"
-// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
-// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
-// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
-// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
-// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
-// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
-// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
-// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]
-// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
-// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]
-// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
-// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
-// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
-// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
-// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
-// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
-// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0
-// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
-// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0
-// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_bb.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_waveforms.html TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_wave*.jpg FALSE
diff --git a/fpga/usrp1/megacells/fifo_4kx16_dc.bsf b/fpga/usrp1/megacells/fifo_4kx16_dc.bsf
deleted file mode 100755
index b80add8de..000000000
--- a/fpga/usrp1/megacells/fifo_4kx16_dc.bsf
+++ /dev/null
@@ -1,117 +0,0 @@
-/*

-WARNING: Do NOT edit the input and output ports in this file in a text

-editor if you plan to continue editing the block that represents it in

-the Block Editor! File corruption is VERY likely to occur.

-*/

-/*

-Copyright (C) 1991-2006 Altera Corporation

-Your use of Altera Corporation's design tools, logic functions 

-and other software and tools, and its AMPP partner logic 

-functions, and any output files any of the foregoing 

-(including device programming or simulation files), and any 

-associated documentation or information are expressly subject 

-to the terms and conditions of the Altera Program License 

-Subscription Agreement, Altera MegaCore Function License 

-Agreement, or other applicable license agreement, including, 

-without limitation, that your use is for the sole purpose of 

-programming logic devices manufactured by Altera and sold by 

-Altera or its authorized distributors.  Please refer to the 

-applicable agreement for further details.

-*/

-(header "symbol" (version "1.1"))

-(symbol

-	(rect 0 0 160 184)

-	(text "fifo_4kx16_dc" (rect 41 1 134 17)(font "Arial" (font_size 10)))

-	(text "inst" (rect 8 168 25 180)(font "Arial" ))

-	(port

-		(pt 0 32)

-		(input)

-		(text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))

-		(text "data[15..0]" (rect 20 26 71 39)(font "Arial" (font_size 8)))

-		(line (pt 0 32)(pt 16 32)(line_width 3))

-	)

-	(port

-		(pt 0 56)

-		(input)

-		(text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8)))

-		(text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8)))

-		(line (pt 0 56)(pt 16 56)(line_width 1))

-	)

-	(port

-		(pt 0 72)

-		(input)

-		(text "wrclk" (rect 0 0 31 14)(font "Arial" (font_size 8)))

-		(text "wrclk" (rect 26 66 48 79)(font "Arial" (font_size 8)))

-		(line (pt 0 72)(pt 16 72)(line_width 1))

-	)

-	(port

-		(pt 0 104)

-		(input)

-		(text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8)))

-		(text "rdreq" (rect 20 98 44 111)(font "Arial" (font_size 8)))

-		(line (pt 0 104)(pt 16 104)(line_width 1))

-	)

-	(port

-		(pt 0 120)

-		(input)

-		(text "rdclk" (rect 0 0 27 14)(font "Arial" (font_size 8)))

-		(text "rdclk" (rect 26 114 47 127)(font "Arial" (font_size 8)))

-		(line (pt 0 120)(pt 16 120)(line_width 1))

-	)

-	(port

-		(pt 0 160)

-		(input)

-		(text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8)))

-		(text "aclr" (rect 20 154 37 167)(font "Arial" (font_size 8)))

-		(line (pt 0 160)(pt 16 160)(line_width 1))

-	)

-	(port

-		(pt 160 40)

-		(output)

-		(text "wrfull" (rect 0 0 33 14)(font "Arial" (font_size 8)))

-		(text "wrfull" (rect 113 34 138 47)(font "Arial" (font_size 8)))

-		(line (pt 160 40)(pt 144 40)(line_width 1))

-	)

-	(port

-		(pt 160 72)

-		(output)

-		(text "wrusedw[11..0]" (rect 0 0 92 14)(font "Arial" (font_size 8)))

-		(text "wrusedw[11..0]" (rect 63 66 132 79)(font "Arial" (font_size 8)))

-		(line (pt 160 72)(pt 144 72)(line_width 3))

-	)

-	(port

-		(pt 160 96)

-		(output)

-		(text "q[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))

-		(text "q[15..0]" (rect 105 90 141 103)(font "Arial" (font_size 8)))

-		(line (pt 160 96)(pt 144 96)(line_width 3))

-	)

-	(port

-		(pt 160 120)

-		(output)

-		(text "rdempty" (rect 0 0 46 14)(font "Arial" (font_size 8)))

-		(text "rdempty" (rect 102 114 140 127)(font "Arial" (font_size 8)))

-		(line (pt 160 120)(pt 144 120)(line_width 1))

-	)

-	(port

-		(pt 160 136)

-		(output)

-		(text "rdusedw[11..0]" (rect 0 0 87 14)(font "Arial" (font_size 8)))

-		(text "rdusedw[11..0]" (rect 67 130 135 143)(font "Arial" (font_size 8)))

-		(line (pt 160 136)(pt 144 136)(line_width 3))

-	)

-	(drawing

-		(text "(ack)" (rect 51 99 72 111)(font "Arial" ))

-		(text "16 bits x 4096 words" (rect 58 156 144 168)(font "Arial" ))

-		(line (pt 16 16)(pt 144 16)(line_width 1))

-		(line (pt 144 16)(pt 144 168)(line_width 1))

-		(line (pt 144 168)(pt 16 168)(line_width 1))

-		(line (pt 16 168)(pt 16 16)(line_width 1))

-		(line (pt 16 84)(pt 144 84)(line_width 1))

-		(line (pt 16 148)(pt 144 148)(line_width 1))

-		(line (pt 16 66)(pt 22 72)(line_width 1))

-		(line (pt 22 72)(pt 16 78)(line_width 1))

-		(line (pt 16 114)(pt 22 120)(line_width 1))

-		(line (pt 22 120)(pt 16 126)(line_width 1))

-	)

-)

diff --git a/fpga/usrp1/megacells/fifo_4kx16_dc.cmp b/fpga/usrp1/megacells/fifo_4kx16_dc.cmp
deleted file mode 100755
index 356de4d62..000000000
--- a/fpga/usrp1/megacells/fifo_4kx16_dc.cmp
+++ /dev/null
@@ -1,31 +0,0 @@
---Copyright (C) 1991-2006 Altera Corporation

---Your use of Altera Corporation's design tools, logic functions 

---and other software and tools, and its AMPP partner logic 

---functions, and any output files any of the foregoing 

---(including device programming or simulation files), and any 

---associated documentation or information are expressly subject 

---to the terms and conditions of the Altera Program License 

---Subscription Agreement, Altera MegaCore Function License 

---Agreement, or other applicable license agreement, including, 

---without limitation, that your use is for the sole purpose of 

---programming logic devices manufactured by Altera and sold by 

---Altera or its authorized distributors.  Please refer to the 

---applicable agreement for further details.

-

-

-component fifo_4kx16_dc

-	PORT

-	(

-		aclr		: IN STD_LOGIC  := '0';

-		data		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);

-		rdclk		: IN STD_LOGIC ;

-		rdreq		: IN STD_LOGIC ;

-		wrclk		: IN STD_LOGIC ;

-		wrreq		: IN STD_LOGIC ;

-		q		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0);

-		rdempty		: OUT STD_LOGIC ;

-		rdusedw		: OUT STD_LOGIC_VECTOR (11 DOWNTO 0);

-		wrfull		: OUT STD_LOGIC ;

-		wrusedw		: OUT STD_LOGIC_VECTOR (11 DOWNTO 0)

-	);

-end component;

diff --git a/fpga/usrp1/megacells/fifo_4kx16_dc.inc b/fpga/usrp1/megacells/fifo_4kx16_dc.inc
deleted file mode 100755
index c14c01836..000000000
--- a/fpga/usrp1/megacells/fifo_4kx16_dc.inc
+++ /dev/null
@@ -1,32 +0,0 @@
---Copyright (C) 1991-2006 Altera Corporation

---Your use of Altera Corporation's design tools, logic functions 

---and other software and tools, and its AMPP partner logic 

---functions, and any output files any of the foregoing 

---(including device programming or simulation files), and any 

---associated documentation or information are expressly subject 

---to the terms and conditions of the Altera Program License 

---Subscription Agreement, Altera MegaCore Function License 

---Agreement, or other applicable license agreement, including, 

---without limitation, that your use is for the sole purpose of 

---programming logic devices manufactured by Altera and sold by 

---Altera or its authorized distributors.  Please refer to the 

---applicable agreement for further details.

-

-

-FUNCTION fifo_4kx16_dc 

-(

-	aclr,

-	data[15..0],

-	rdclk,

-	rdreq,

-	wrclk,

-	wrreq

-)

-

-RETURNS (

-	q[15..0],

-	rdempty,

-	rdusedw[11..0],

-	wrfull,

-	wrusedw[11..0]

-);

diff --git a/fpga/usrp1/megacells/fifo_4kx16_dc.v b/fpga/usrp1/megacells/fifo_4kx16_dc.v
deleted file mode 100755
index 1f09000e3..000000000
--- a/fpga/usrp1/megacells/fifo_4kx16_dc.v
+++ /dev/null
@@ -1,178 +0,0 @@
-// megafunction wizard: %FIFO%

-// GENERATION: STANDARD

-// VERSION: WM1.0

-// MODULE: dcfifo 

-

-// ============================================================

-// File Name: fifo_4kx16_dc.v

-// Megafunction Name(s):

-// 			dcfifo

-// ============================================================

-// ************************************************************

-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!

-//

-// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition

-// ************************************************************

-

-

-//Copyright (C) 1991-2006 Altera Corporation

-//Your use of Altera Corporation's design tools, logic functions 

-//and other software and tools, and its AMPP partner logic 

-//functions, and any output files any of the foregoing 

-//(including device programming or simulation files), and any 

-//associated documentation or information are expressly subject 

-//to the terms and conditions of the Altera Program License 

-//Subscription Agreement, Altera MegaCore Function License 

-//Agreement, or other applicable license agreement, including, 

-//without limitation, that your use is for the sole purpose of 

-//programming logic devices manufactured by Altera and sold by 

-//Altera or its authorized distributors.  Please refer to the 

-//applicable agreement for further details.

-

-

-// synopsys translate_off

-`timescale 1 ps / 1 ps

-// synopsys translate_on

-module fifo_4kx16_dc (

-	aclr,

-	data,

-	rdclk,

-	rdreq,

-	wrclk,

-	wrreq,

-	q,

-	rdempty,

-	rdusedw,

-	wrfull,

-	wrusedw);

-

-	input	  aclr;

-	input	[15:0]  data;

-	input	  rdclk;

-	input	  rdreq;

-	input	  wrclk;

-	input	  wrreq;

-	output	[15:0]  q;

-	output	  rdempty;

-	output	[11:0]  rdusedw;

-	output	  wrfull;

-	output	[11:0]  wrusedw;

-

-	wire  sub_wire0;

-	wire [11:0] sub_wire1;

-	wire  sub_wire2;

-	wire [15:0] sub_wire3;

-	wire [11:0] sub_wire4;

-	wire  rdempty = sub_wire0;

-	wire [11:0] wrusedw = sub_wire1[11:0];

-	wire  wrfull = sub_wire2;

-	wire [15:0] q = sub_wire3[15:0];

-	wire [11:0] rdusedw = sub_wire4[11:0];

-

-	dcfifo	dcfifo_component (

-				.wrclk (wrclk),

-				.rdreq (rdreq),

-				.aclr (aclr),

-				.rdclk (rdclk),

-				.wrreq (wrreq),

-				.data (data),

-				.rdempty (sub_wire0),

-				.wrusedw (sub_wire1),

-				.wrfull (sub_wire2),

-				.q (sub_wire3),

-				.rdusedw (sub_wire4)

-				// synopsys translate_off

-				,

-				.wrempty (),

-				.rdfull ()

-				// synopsys translate_on

-				);

-	defparam

-		dcfifo_component.add_ram_output_register = "OFF",

-		dcfifo_component.clocks_are_synchronized = "FALSE",

-		dcfifo_component.intended_device_family = "Cyclone",

-		dcfifo_component.lpm_numwords = 4096,

-		dcfifo_component.lpm_showahead = "ON",

-		dcfifo_component.lpm_type = "dcfifo",

-		dcfifo_component.lpm_width = 16,

-		dcfifo_component.lpm_widthu = 12,

-		dcfifo_component.overflow_checking = "OFF",

-		dcfifo_component.underflow_checking = "OFF",

-		dcfifo_component.use_eab = "ON";

-

-

-endmodule

-

-// ============================================================

-// CNX file retrieval info

-// ============================================================

-// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"

-// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"

-// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"

-// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"

-// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"

-// Retrieval info: PRIVATE: Clock NUMERIC "4"

-// Retrieval info: PRIVATE: Depth NUMERIC "4096"

-// Retrieval info: PRIVATE: Empty NUMERIC "1"

-// Retrieval info: PRIVATE: Full NUMERIC "1"

-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"

-// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"

-// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"

-// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"

-// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"

-// Retrieval info: PRIVATE: Optimize NUMERIC "2"

-// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"

-// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"

-// Retrieval info: PRIVATE: UsedW NUMERIC "1"

-// Retrieval info: PRIVATE: Width NUMERIC "16"

-// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"

-// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"

-// Retrieval info: PRIVATE: rsFull NUMERIC "0"

-// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"

-// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"

-// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"

-// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"

-// Retrieval info: PRIVATE: wsFull NUMERIC "1"

-// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"

-// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"

-// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"

-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"

-// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"

-// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"

-// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"

-// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"

-// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"

-// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"

-// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"

-// Retrieval info: CONSTANT: USE_EAB STRING "ON"

-// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr

-// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]

-// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]

-// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk

-// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty

-// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq

-// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]

-// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk

-// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull

-// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq

-// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]

-// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0

-// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0

-// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0

-// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0

-// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0

-// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0

-// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0

-// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0

-// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0

-// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0

-// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0

-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all

-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.v TRUE

-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.inc TRUE

-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.cmp TRUE

-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.bsf TRUE

-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_inst.v TRUE

-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_bb.v TRUE

-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_waveforms.html FALSE

-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_wave*.jpg FALSE

diff --git a/fpga/usrp1/megacells/fifo_4kx16_dc_bb.v b/fpga/usrp1/megacells/fifo_4kx16_dc_bb.v
deleted file mode 100755
index 91c3c322f..000000000
--- a/fpga/usrp1/megacells/fifo_4kx16_dc_bb.v
+++ /dev/null
@@ -1,130 +0,0 @@
-// megafunction wizard: %FIFO%VBB%

-// GENERATION: STANDARD

-// VERSION: WM1.0

-// MODULE: dcfifo 

-

-// ============================================================

-// File Name: fifo_4kx16_dc.v

-// Megafunction Name(s):

-// 			dcfifo

-// ============================================================

-// ************************************************************

-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!

-//

-// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition

-// ************************************************************

-

-//Copyright (C) 1991-2006 Altera Corporation

-//Your use of Altera Corporation's design tools, logic functions 

-//and other software and tools, and its AMPP partner logic 

-//functions, and any output files any of the foregoing 

-//(including device programming or simulation files), and any 

-//associated documentation or information are expressly subject 

-//to the terms and conditions of the Altera Program License 

-//Subscription Agreement, Altera MegaCore Function License 

-//Agreement, or other applicable license agreement, including, 

-//without limitation, that your use is for the sole purpose of 

-//programming logic devices manufactured by Altera and sold by 

-//Altera or its authorized distributors.  Please refer to the 

-//applicable agreement for further details.

-

-module fifo_4kx16_dc (

-	aclr,

-	data,

-	rdclk,

-	rdreq,

-	wrclk,

-	wrreq,

-	q,

-	rdempty,

-	rdusedw,

-	wrfull,

-	wrusedw);

-

-	input	  aclr;

-	input	[15:0]  data;

-	input	  rdclk;

-	input	  rdreq;

-	input	  wrclk;

-	input	  wrreq;

-	output	[15:0]  q;

-	output	  rdempty;

-	output	[11:0]  rdusedw;

-	output	  wrfull;

-	output	[11:0]  wrusedw;

-

-endmodule

-

-// ============================================================

-// CNX file retrieval info

-// ============================================================

-// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"

-// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"

-// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"

-// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"

-// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"

-// Retrieval info: PRIVATE: Clock NUMERIC "4"

-// Retrieval info: PRIVATE: Depth NUMERIC "4096"

-// Retrieval info: PRIVATE: Empty NUMERIC "1"

-// Retrieval info: PRIVATE: Full NUMERIC "1"

-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"

-// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"

-// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"

-// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"

-// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"

-// Retrieval info: PRIVATE: Optimize NUMERIC "2"

-// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"

-// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"

-// Retrieval info: PRIVATE: UsedW NUMERIC "1"

-// Retrieval info: PRIVATE: Width NUMERIC "16"

-// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"

-// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"

-// Retrieval info: PRIVATE: rsFull NUMERIC "0"

-// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"

-// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"

-// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"

-// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"

-// Retrieval info: PRIVATE: wsFull NUMERIC "1"

-// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"

-// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"

-// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"

-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"

-// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"

-// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"

-// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"

-// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"

-// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"

-// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"

-// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"

-// Retrieval info: CONSTANT: USE_EAB STRING "ON"

-// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr

-// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]

-// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]

-// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk

-// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty

-// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq

-// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]

-// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk

-// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull

-// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq

-// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]

-// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0

-// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0

-// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0

-// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0

-// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0

-// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0

-// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0

-// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0

-// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0

-// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0

-// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0

-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all

-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.v TRUE

-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.inc TRUE

-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.cmp TRUE

-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.bsf TRUE

-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_inst.v TRUE

-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_bb.v TRUE

-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_waveforms.html FALSE

-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_wave*.jpg FALSE

diff --git a/fpga/usrp1/megacells/fifo_4kx16_dc_inst.v b/fpga/usrp1/megacells/fifo_4kx16_dc_inst.v
deleted file mode 100755
index 566f27a17..000000000
--- a/fpga/usrp1/megacells/fifo_4kx16_dc_inst.v
+++ /dev/null
@@ -1,13 +0,0 @@
-fifo_4kx16_dc	fifo_4kx16_dc_inst (

-	.aclr ( aclr_sig ),

-	.data ( data_sig ),

-	.rdclk ( rdclk_sig ),

-	.rdreq ( rdreq_sig ),

-	.wrclk ( wrclk_sig ),

-	.wrreq ( wrreq_sig ),

-	.q ( q_sig ),

-	.rdempty ( rdempty_sig ),

-	.rdusedw ( rdusedw_sig ),

-	.wrfull ( wrfull_sig ),

-	.wrusedw ( wrusedw_sig )

-	);

diff --git a/fpga/usrp1/megacells/mylpm_addsub.bsf b/fpga/usrp1/megacells/mylpm_addsub.bsf
deleted file mode 100755
index e5c1ded7f..000000000
--- a/fpga/usrp1/megacells/mylpm_addsub.bsf
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 1991-2003 Altera Corporation
-Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-support information,  device programming or simulation file,  and any other
-associated  documentation or information  provided by  Altera  or a partner
-under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-other  use  of such  megafunction  design,  netlist,  support  information,
-device programming or simulation file,  or any other  related documentation
-or information  is prohibited  for  any  other purpose,  including, but not
-limited to  modification,  reverse engineering,  de-compiling, or use  with
-any other  silicon devices,  unless such use is  explicitly  licensed under
-a separate agreement with  Altera  or a megafunction partner.  Title to the
-intellectual property,  including patents,  copyrights,  trademarks,  trade
-secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-support  information,  device programming or simulation file,  or any other
-related documentation or information provided by  Altera  or a megafunction
-partner, remains with Altera, the megafunction partner, or their respective
-licensors. No other licenses, including any licenses needed under any third
-party's intellectual property, are provided herein.
-*/
-(header "symbol" (version "1.1"))
-(symbol
-	(rect 0 0 160 112)
-	(text "mylpm_addsub" (rect 26 2 145 21)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 93 30 108)(font "Arial" ))
-	(port
-		(pt 0 56)
-		(input)
-		(text "dataa[15..0]" (rect 0 0 75 16)(font "Arial" (font_size 8)))
-		(text "dataa[15..0]" (rect 4 40 73 56)(font "Arial" (font_size 8)))
-		(line (pt 0 56)(pt 64 56)(line_width 3))
-	)
-	(port
-		(pt 0 88)
-		(input)
-		(text "datab[15..0]" (rect 0 0 75 16)(font "Arial" (font_size 8)))
-		(text "datab[15..0]" (rect 4 72 73 88)(font "Arial" (font_size 8)))
-		(line (pt 0 88)(pt 64 88)(line_width 3))
-	)
-	(port
-		(pt 0 72)
-		(input)
-		(text "clock" (rect 0 0 34 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 4 56 35 72)(font "Arial" (font_size 8)))
-		(line (pt 0 72)(pt 64 72)(line_width 1))
-	)
-	(port
-		(pt 0 32)
-		(input)
-		(text "add_sub" (rect 0 0 53 16)(font "Arial" (font_size 8)))
-		(text "add_sub" (rect 4 16 53 32)(font "Arial" (font_size 8)))
-		(line (pt 0 32)(pt 80 32)(line_width 1))
-	)
-	(port
-		(pt 160 72)
-		(output)
-		(text "result[15..0]" (rect 0 0 75 16)(font "Arial" (font_size 8)))
-		(text "result[15..0]" (rect 88 56 157 72)(font "Arial" (font_size 8)))
-		(line (pt 160 72)(pt 96 72)(line_width 3))
-	)
-	(drawing
-		(text "A" (rect 66 48 75 64)(font "Arial" (font_size 8)))
-		(text "B" (rect 66 80 75 96)(font "Arial" (font_size 8)))
-		(text "A+B/A-B" (rect 82 37 134 53)(font "Arial" (font_size 8)))
-		(line (pt 64 48)(pt 96 56)(line_width 1))
-		(line (pt 96 56)(pt 96 88)(line_width 1))
-		(line (pt 96 88)(pt 64 96)(line_width 1))
-		(line (pt 64 96)(pt 64 48)(line_width 1))
-		(line (pt 80 32)(pt 80 52)(line_width 1))
-		(line (pt 106 40)(pt 125 40)(line_width 1))
-		(line (pt 64 66)(pt 70 72)(line_width 1))
-		(line (pt 70 72)(pt 64 78)(line_width 1))
-	)
-)
diff --git a/fpga/usrp1/megacells/mylpm_addsub.cmp b/fpga/usrp1/megacells/mylpm_addsub.cmp
deleted file mode 100755
index 311c54a5b..000000000
--- a/fpga/usrp1/megacells/mylpm_addsub.cmp
+++ /dev/null
@@ -1,31 +0,0 @@
---Copyright (C) 1991-2003 Altera Corporation
---Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
---support information,  device programming or simulation file,  and any other
---associated  documentation or information  provided by  Altera  or a partner
---under  Altera's   Megafunction   Partnership   Program  may  be  used  only
---to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
---other  use  of such  megafunction  design,  netlist,  support  information,
---device programming or simulation file,  or any other  related documentation
---or information  is prohibited  for  any  other purpose,  including, but not
---limited to  modification,  reverse engineering,  de-compiling, or use  with
---any other  silicon devices,  unless such use is  explicitly  licensed under
---a separate agreement with  Altera  or a megafunction partner.  Title to the
---intellectual property,  including patents,  copyrights,  trademarks,  trade
---secrets,  or maskworks,  embodied in any such megafunction design, netlist,
---support  information,  device programming or simulation file,  or any other
---related documentation or information provided by  Altera  or a megafunction
---partner, remains with Altera, the megafunction partner, or their respective
---licensors. No other licenses, including any licenses needed under any third
---party's intellectual property, are provided herein.
-
-
-component mylpm_addsub
-	PORT
-	(
-		add_sub		: IN STD_LOGIC ;
-		dataa		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-		datab		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-		clock		: IN STD_LOGIC ;
-		result		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
-	);
-end component;
diff --git a/fpga/usrp1/megacells/mylpm_addsub.inc b/fpga/usrp1/megacells/mylpm_addsub.inc
deleted file mode 100755
index d8b283f49..000000000
--- a/fpga/usrp1/megacells/mylpm_addsub.inc
+++ /dev/null
@@ -1,32 +0,0 @@
---Copyright (C) 1991-2003 Altera Corporation
---Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
---support information,  device programming or simulation file,  and any other
---associated  documentation or information  provided by  Altera  or a partner
---under  Altera's   Megafunction   Partnership   Program  may  be  used  only
---to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
---other  use  of such  megafunction  design,  netlist,  support  information,
---device programming or simulation file,  or any other  related documentation
---or information  is prohibited  for  any  other purpose,  including, but not
---limited to  modification,  reverse engineering,  de-compiling, or use  with
---any other  silicon devices,  unless such use is  explicitly  licensed under
---a separate agreement with  Altera  or a megafunction partner.  Title to the
---intellectual property,  including patents,  copyrights,  trademarks,  trade
---secrets,  or maskworks,  embodied in any such megafunction design, netlist,
---support  information,  device programming or simulation file,  or any other
---related documentation or information provided by  Altera  or a megafunction
---partner, remains with Altera, the megafunction partner, or their respective
---licensors. No other licenses, including any licenses needed under any third
---party's intellectual property, are provided herein.
-
-
-FUNCTION mylpm_addsub 
-(
-	add_sub,
-	dataa[15..0],
-	datab[15..0],
-	clock
-)
-
-RETURNS (
-	result[15..0]
-);
diff --git a/fpga/usrp1/megacells/mylpm_addsub.v b/fpga/usrp1/megacells/mylpm_addsub.v
deleted file mode 100755
index 0566f7e57..000000000
--- a/fpga/usrp1/megacells/mylpm_addsub.v
+++ /dev/null
@@ -1,102 +0,0 @@
-// megafunction wizard: %LPM_ADD_SUB%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: lpm_add_sub 
-
-// ============================================================
-// File Name: mylpm_addsub.v
-// Megafunction Name(s):
-// 			lpm_add_sub
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-// ************************************************************
-
-
-//Copyright (C) 1991-2003 Altera Corporation
-//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-//support information,  device programming or simulation file,  and any other
-//associated  documentation or information  provided by  Altera  or a partner
-//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-//other  use  of such  megafunction  design,  netlist,  support  information,
-//device programming or simulation file,  or any other  related documentation
-//or information  is prohibited  for  any  other purpose,  including, but not
-//limited to  modification,  reverse engineering,  de-compiling, or use  with
-//any other  silicon devices,  unless such use is  explicitly  licensed under
-//a separate agreement with  Altera  or a megafunction partner.  Title to the
-//intellectual property,  including patents,  copyrights,  trademarks,  trade
-//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-//support  information,  device programming or simulation file,  or any other
-//related documentation or information provided by  Altera  or a megafunction
-//partner, remains with Altera, the megafunction partner, or their respective
-//licensors. No other licenses, including any licenses needed under any third
-//party's intellectual property, are provided herein.
-
-
-module mylpm_addsub (
-	add_sub,
-	dataa,
-	datab,
-	clock,
-	result);
-
-	input	  add_sub;
-	input	[15:0]  dataa;
-	input	[15:0]  datab;
-	input	  clock;
-	output	[15:0]  result;
-
-	wire [15:0] sub_wire0;
-	wire [15:0] result = sub_wire0[15:0];
-
-	lpm_add_sub	lpm_add_sub_component (
-				.dataa (dataa),
-				.add_sub (add_sub),
-				.datab (datab),
-				.clock (clock),
-				.result (sub_wire0));
-	defparam
-		lpm_add_sub_component.lpm_width = 16,
-		lpm_add_sub_component.lpm_direction = "UNUSED",
-		lpm_add_sub_component.lpm_type = "LPM_ADD_SUB",
-		lpm_add_sub_component.lpm_hint = "ONE_INPUT_IS_CONSTANT=NO",
-		lpm_add_sub_component.lpm_pipeline = 1;
-
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: nBit NUMERIC "16"
-// Retrieval info: PRIVATE: Function NUMERIC "2"
-// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
-// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
-// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
-// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
-// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
-// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-// Retrieval info: PRIVATE: Overflow NUMERIC "0"
-// Retrieval info: PRIVATE: Latency NUMERIC "1"
-// Retrieval info: PRIVATE: aclr NUMERIC "0"
-// Retrieval info: PRIVATE: clken NUMERIC "0"
-// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
-// Retrieval info: CONSTANT: LPM_DIRECTION STRING "UNUSED"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
-// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO"
-// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
-// Retrieval info: USED_PORT: add_sub 0 0 0 0 INPUT NODEFVAL add_sub
-// Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL result[15..0]
-// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL dataa[15..0]
-// Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL datab[15..0]
-// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-// Retrieval info: CONNECT: @add_sub 0 0 0 0 add_sub 0 0 0 0
-// Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
-// Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0
-// Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0
-// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
diff --git a/fpga/usrp1/megacells/mylpm_addsub_bb.v b/fpga/usrp1/megacells/mylpm_addsub_bb.v
deleted file mode 100755
index 598d3da52..000000000
--- a/fpga/usrp1/megacells/mylpm_addsub_bb.v
+++ /dev/null
@@ -1,35 +0,0 @@
-//Copyright (C) 1991-2003 Altera Corporation
-//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-//support information,  device programming or simulation file,  and any other
-//associated  documentation or information  provided by  Altera  or a partner
-//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-//other  use  of such  megafunction  design,  netlist,  support  information,
-//device programming or simulation file,  or any other  related documentation
-//or information  is prohibited  for  any  other purpose,  including, but not
-//limited to  modification,  reverse engineering,  de-compiling, or use  with
-//any other  silicon devices,  unless such use is  explicitly  licensed under
-//a separate agreement with  Altera  or a megafunction partner.  Title to the
-//intellectual property,  including patents,  copyrights,  trademarks,  trade
-//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-//support  information,  device programming or simulation file,  or any other
-//related documentation or information provided by  Altera  or a megafunction
-//partner, remains with Altera, the megafunction partner, or their respective
-//licensors. No other licenses, including any licenses needed under any third
-//party's intellectual property, are provided herein.
-
-module mylpm_addsub (
-	add_sub,
-	dataa,
-	datab,
-	clock,
-	result);
-
-	input	  add_sub;
-	input	[15:0]  dataa;
-	input	[15:0]  datab;
-	input	  clock;
-	output	[15:0]  result;
-
-endmodule
-
diff --git a/fpga/usrp1/megacells/mylpm_addsub_inst.v b/fpga/usrp1/megacells/mylpm_addsub_inst.v
deleted file mode 100755
index dd732bd6d..000000000
--- a/fpga/usrp1/megacells/mylpm_addsub_inst.v
+++ /dev/null
@@ -1,7 +0,0 @@
-mylpm_addsub	mylpm_addsub_inst (
-	.add_sub ( add_sub_sig ),
-	.dataa ( dataa_sig ),
-	.datab ( datab_sig ),
-	.clock ( clock_sig ),
-	.result ( result_sig )
-	);
diff --git a/fpga/usrp1/megacells/pll.v b/fpga/usrp1/megacells/pll.v
deleted file mode 100644
index dacd11f23..000000000
--- a/fpga/usrp1/megacells/pll.v
+++ /dev/null
@@ -1,207 +0,0 @@
-// megafunction wizard: %ALTPLL%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: altpll 
-
-// ============================================================
-// File Name: pll.v
-// Megafunction Name(s):
-// 			altpll
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 4.0 Build 214 3/25/2004 SP 1 SJ Web Edition
-// ************************************************************
-
-
-//Copyright (C) 1991-2004 Altera Corporation
-//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-//support information,  device programming or simulation file,  and any other
-//associated  documentation or information  provided by  Altera  or a partner
-//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-//other  use  of such  megafunction  design,  netlist,  support  information,
-//device programming or simulation file,  or any other  related documentation
-//or information  is prohibited  for  any  other purpose,  including, but not
-//limited to  modification,  reverse engineering,  de-compiling, or use  with
-//any other  silicon devices,  unless such use is  explicitly  licensed under
-//a separate agreement with  Altera  or a megafunction partner.  Title to the
-//intellectual property,  including patents,  copyrights,  trademarks,  trade
-//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-//support  information,  device programming or simulation file,  or any other
-//related documentation or information provided by  Altera  or a megafunction
-//partner, remains with Altera, the megafunction partner, or their respective
-//licensors. No other licenses, including any licenses needed under any third
-//party's intellectual property, are provided herein.
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module pll (
-	inclk0,
-	c0);
-
-	input	  inclk0;
-	output	  c0;
-
-	wire [5:0] sub_wire0;
-	wire [0:0] sub_wire4 = 1'h0;
-	wire [0:0] sub_wire1 = sub_wire0[0:0];
-	wire  c0 = sub_wire1;
-	wire  sub_wire2 = inclk0;
-	wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
-
-	altpll	altpll_component (
-				.inclk (sub_wire3),
-				.clk (sub_wire0)
-				// synopsys translate_off
-,
-				.fbin (),
-				.pllena (),
-				.clkswitch (),
-				.areset (),
-				.pfdena (),
-				.clkena (),
-				.extclkena (),
-				.scanclk (),
-				.scanaclr (),
-				.scandata (),
-				.scanread (),
-				.scanwrite (),
-				.extclk (),
-				.clkbad (),
-				.activeclock (),
-				.locked (),
-				.clkloss (),
-				.scandataout (),
-				.scandone (),
-				.sclkout1 (),
-				.sclkout0 (),
-				.enable0 (),
-				.enable1 ()
-				// synopsys translate_on
-
-);
-	defparam
-		altpll_component.clk0_duty_cycle = 50,
-		altpll_component.lpm_type = "altpll",
-		altpll_component.clk0_multiply_by = 1,
-		altpll_component.inclk0_input_frequency = 20833,
-		altpll_component.clk0_divide_by = 1,
-		altpll_component.pll_type = "AUTO",
-		altpll_component.clk0_time_delay = "0",
-		altpll_component.intended_device_family = "Cyclone",
-		altpll_component.operation_mode = "NORMAL",
-		altpll_component.compensate_clock = "CLK0",
-		altpll_component.clk0_phase_shift = "-3000";
-
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "-3.00000000"
-// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-// Retrieval info: PRIVATE: TIME_SHIFT0 STRING "0.00000000"
-// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_0 STRING "inclk;fbin;pllena;clkswitch;areset"
-// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
-// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_1 STRING "pfdena;clkena;extclkena;scanclk;scanaclr"
-// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_2 STRING "scandata;scanread;scanwrite;clk;extclk"
-// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "528.000"
-// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_3 STRING "clkbad;activeclock;locked;clkloss;scandataout"
-// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000"
-// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_4 STRING "scandone;sclkout1;sclkout0;enable0;enable1"
-// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
-// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
-// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
-// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833"
-// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-// Retrieval info: CONSTANT: CLK0_TIME_DELAY STRING "0"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "-3000"
-// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
-// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
-// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
-// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
-// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v TRUE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE FALSE
diff --git a/fpga/usrp1/megacells/pll_bb.v b/fpga/usrp1/megacells/pll_bb.v
deleted file mode 100644
index debadaa25..000000000
--- a/fpga/usrp1/megacells/pll_bb.v
+++ /dev/null
@@ -1,29 +0,0 @@
-//Copyright (C) 1991-2004 Altera Corporation
-//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-//support information,  device programming or simulation file,  and any other
-//associated  documentation or information  provided by  Altera  or a partner
-//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-//other  use  of such  megafunction  design,  netlist,  support  information,
-//device programming or simulation file,  or any other  related documentation
-//or information  is prohibited  for  any  other purpose,  including, but not
-//limited to  modification,  reverse engineering,  de-compiling, or use  with
-//any other  silicon devices,  unless such use is  explicitly  licensed under
-//a separate agreement with  Altera  or a megafunction partner.  Title to the
-//intellectual property,  including patents,  copyrights,  trademarks,  trade
-//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-//support  information,  device programming or simulation file,  or any other
-//related documentation or information provided by  Altera  or a megafunction
-//partner, remains with Altera, the megafunction partner, or their respective
-//licensors. No other licenses, including any licenses needed under any third
-//party's intellectual property, are provided herein.
-
-module pll (
-	inclk0,
-	c0);
-
-	input	  inclk0;
-	output	  c0;
-
-endmodule
-
diff --git a/fpga/usrp1/megacells/pll_inst.v b/fpga/usrp1/megacells/pll_inst.v
deleted file mode 100644
index 97db58ba0..000000000
--- a/fpga/usrp1/megacells/pll_inst.v
+++ /dev/null
@@ -1,4 +0,0 @@
-pll	pll_inst (
-	.inclk0 ( inclk0_sig ),
-	.c0 ( c0_sig )
-	);
diff --git a/fpga/usrp1/megacells/sub32.bsf b/fpga/usrp1/megacells/sub32.bsf
deleted file mode 100755
index 753fdc738..000000000
--- a/fpga/usrp1/megacells/sub32.bsf
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 1991-2003 Altera Corporation
-Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-support information,  device programming or simulation file,  and any other
-associated  documentation or information  provided by  Altera  or a partner
-under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-other  use  of such  megafunction  design,  netlist,  support  information,
-device programming or simulation file,  or any other  related documentation
-or information  is prohibited  for  any  other purpose,  including, but not
-limited to  modification,  reverse engineering,  de-compiling, or use  with
-any other  silicon devices,  unless such use is  explicitly  licensed under
-a separate agreement with  Altera  or a megafunction partner.  Title to the
-intellectual property,  including patents,  copyrights,  trademarks,  trade
-secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-support  information,  device programming or simulation file,  or any other
-related documentation or information provided by  Altera  or a megafunction
-partner, remains with Altera, the megafunction partner, or their respective
-licensors. No other licenses, including any licenses needed under any third
-party's intellectual property, are provided herein.
-*/
-(header "symbol" (version "1.1"))
-(symbol
-	(rect 0 0 160 128)
-	(text "sub32" (rect 58 2 109 21)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 109 31 124)(font "Arial" ))
-	(port
-		(pt 0 40)
-		(input)
-		(text "dataa[31..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "dataa[31..0]" (rect 4 24 73 40)(font "Arial" (font_size 8)))
-		(line (pt 0 40)(pt 64 40)(line_width 3))
-	)
-	(port
-		(pt 0 72)
-		(input)
-		(text "datab[31..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "datab[31..0]" (rect 4 56 73 72)(font "Arial" (font_size 8)))
-		(line (pt 0 72)(pt 64 72)(line_width 3))
-	)
-	(port
-		(pt 0 56)
-		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 4 40 35 56)(font "Arial" (font_size 8)))
-		(line (pt 0 56)(pt 64 56)(line_width 1))
-	)
-	(port
-		(pt 0 96)
-		(input)
-		(text "clken" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clken" (rect 4 80 35 96)(font "Arial" (font_size 8)))
-		(line (pt 0 96)(pt 74 96)(line_width 1))
-	)
-	(port
-		(pt 0 112)
-		(input)
-		(text "aclr" (rect 0 0 24 16)(font "Arial" (font_size 8)))
-		(text "aclr" (rect 4 96 25 112)(font "Arial" (font_size 8)))
-		(line (pt 0 112)(pt 85 112)(line_width 1))
-	)
-	(port
-		(pt 160 56)
-		(output)
-		(text "result[31..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "result[31..0]" (rect 88 40 157 56)(font "Arial" (font_size 8)))
-		(line (pt 160 56)(pt 96 56)(line_width 3))
-	)
-	(drawing
-		(text "A" (rect 66 32 75 48)(font "Arial" (font_size 8)))
-		(text "B" (rect 66 64 75 80)(font "Arial" (font_size 8)))
-		(text "A-B" (rect 72 48 94 64)(font "Arial" (font_size 8)))
-		(line (pt 64 32)(pt 96 40)(line_width 1))
-		(line (pt 96 40)(pt 96 72)(line_width 1))
-		(line (pt 96 72)(pt 64 80)(line_width 1))
-		(line (pt 64 80)(pt 64 32)(line_width 1))
-		(line (pt 74 96)(pt 74 77)(line_width 1))
-		(line (pt 85 112)(pt 85 74)(line_width 1))
-		(line (pt 64 50)(pt 70 56)(line_width 1))
-		(line (pt 70 56)(pt 64 62)(line_width 1))
-	)
-)
diff --git a/fpga/usrp1/megacells/sub32.cmp b/fpga/usrp1/megacells/sub32.cmp
deleted file mode 100755
index 0d5b62ef9..000000000
--- a/fpga/usrp1/megacells/sub32.cmp
+++ /dev/null
@@ -1,32 +0,0 @@
---Copyright (C) 1991-2003 Altera Corporation
---Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
---support information,  device programming or simulation file,  and any other
---associated  documentation or information  provided by  Altera  or a partner
---under  Altera's   Megafunction   Partnership   Program  may  be  used  only
---to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
---other  use  of such  megafunction  design,  netlist,  support  information,
---device programming or simulation file,  or any other  related documentation
---or information  is prohibited  for  any  other purpose,  including, but not
---limited to  modification,  reverse engineering,  de-compiling, or use  with
---any other  silicon devices,  unless such use is  explicitly  licensed under
---a separate agreement with  Altera  or a megafunction partner.  Title to the
---intellectual property,  including patents,  copyrights,  trademarks,  trade
---secrets,  or maskworks,  embodied in any such megafunction design, netlist,
---support  information,  device programming or simulation file,  or any other
---related documentation or information provided by  Altera  or a megafunction
---partner, remains with Altera, the megafunction partner, or their respective
---licensors. No other licenses, including any licenses needed under any third
---party's intellectual property, are provided herein.
-
-
-component sub32
-	PORT
-	(
-		dataa		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-		datab		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-		clock		: IN STD_LOGIC ;
-		aclr		: IN STD_LOGIC ;
-		clken		: IN STD_LOGIC ;
-		result		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
-	);
-end component;
diff --git a/fpga/usrp1/megacells/sub32.inc b/fpga/usrp1/megacells/sub32.inc
deleted file mode 100755
index 3c64e21c5..000000000
--- a/fpga/usrp1/megacells/sub32.inc
+++ /dev/null
@@ -1,33 +0,0 @@
---Copyright (C) 1991-2003 Altera Corporation
---Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
---support information,  device programming or simulation file,  and any other
---associated  documentation or information  provided by  Altera  or a partner
---under  Altera's   Megafunction   Partnership   Program  may  be  used  only
---to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
---other  use  of such  megafunction  design,  netlist,  support  information,
---device programming or simulation file,  or any other  related documentation
---or information  is prohibited  for  any  other purpose,  including, but not
---limited to  modification,  reverse engineering,  de-compiling, or use  with
---any other  silicon devices,  unless such use is  explicitly  licensed under
---a separate agreement with  Altera  or a megafunction partner.  Title to the
---intellectual property,  including patents,  copyrights,  trademarks,  trade
---secrets,  or maskworks,  embodied in any such megafunction design, netlist,
---support  information,  device programming or simulation file,  or any other
---related documentation or information provided by  Altera  or a megafunction
---partner, remains with Altera, the megafunction partner, or their respective
---licensors. No other licenses, including any licenses needed under any third
---party's intellectual property, are provided herein.
-
-
-FUNCTION sub32 
-(
-	dataa[31..0],
-	datab[31..0],
-	clock,
-	aclr,
-	clken
-)
-
-RETURNS (
-	result[31..0]
-);
diff --git a/fpga/usrp1/megacells/sub32.v b/fpga/usrp1/megacells/sub32.v
deleted file mode 100755
index dd825d91a..000000000
--- a/fpga/usrp1/megacells/sub32.v
+++ /dev/null
@@ -1,675 +0,0 @@
-// megafunction wizard: %LPM_ADD_SUB%CBX%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: lpm_add_sub 
-
-// ============================================================
-// File Name: sub32.v
-// Megafunction Name(s):
-// 			lpm_add_sub
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-// ************************************************************
-
-
-//Copyright (C) 1991-2003 Altera Corporation
-//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-//support information,  device programming or simulation file,  and any other
-//associated  documentation or information  provided by  Altera  or a partner
-//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-//other  use  of such  megafunction  design,  netlist,  support  information,
-//device programming or simulation file,  or any other  related documentation
-//or information  is prohibited  for  any  other purpose,  including, but not
-//limited to  modification,  reverse engineering,  de-compiling, or use  with
-//any other  silicon devices,  unless such use is  explicitly  licensed under
-//a separate agreement with  Altera  or a megafunction partner.  Title to the
-//intellectual property,  including patents,  copyrights,  trademarks,  trade
-//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-//support  information,  device programming or simulation file,  or any other
-//related documentation or information provided by  Altera  or a megafunction
-//partner, remains with Altera, the megafunction partner, or their respective
-//licensors. No other licenses, including any licenses needed under any third
-//party's intellectual property, are provided herein.
-
-
-//lpm_add_sub DEVICE_FAMILY=Cyclone LPM_DIRECTION=SUB LPM_PIPELINE=1 LPM_WIDTH=32 aclr clken clock dataa datab result
-//VERSION_BEGIN 3.0 cbx_lpm_add_sub 2003:04:10:18:28:42:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ  VERSION_END
-
-//synthesis_resources = lut 32 
-module  sub32_add_sub_cqa
-	( 
-	aclr,
-	clken,
-	clock,
-	dataa,
-	datab,
-	result) /* synthesis synthesis_clearbox=1 */;
-	input   aclr;
-	input   clken;
-	input   clock;
-	input   [31:0]  dataa;
-	input   [31:0]  datab;
-	output   [31:0]  result;
-
-	wire  [0:0]   wire_add_sub_cella_0cout;
-	wire  [0:0]   wire_add_sub_cella_1cout;
-	wire  [0:0]   wire_add_sub_cella_2cout;
-	wire  [0:0]   wire_add_sub_cella_3cout;
-	wire  [0:0]   wire_add_sub_cella_4cout;
-	wire  [0:0]   wire_add_sub_cella_5cout;
-	wire  [0:0]   wire_add_sub_cella_6cout;
-	wire  [0:0]   wire_add_sub_cella_7cout;
-	wire  [0:0]   wire_add_sub_cella_8cout;
-	wire  [0:0]   wire_add_sub_cella_9cout;
-	wire  [0:0]   wire_add_sub_cella_10cout;
-	wire  [0:0]   wire_add_sub_cella_11cout;
-	wire  [0:0]   wire_add_sub_cella_12cout;
-	wire  [0:0]   wire_add_sub_cella_13cout;
-	wire  [0:0]   wire_add_sub_cella_14cout;
-	wire  [0:0]   wire_add_sub_cella_15cout;
-	wire  [0:0]   wire_add_sub_cella_16cout;
-	wire  [0:0]   wire_add_sub_cella_17cout;
-	wire  [0:0]   wire_add_sub_cella_18cout;
-	wire  [0:0]   wire_add_sub_cella_19cout;
-	wire  [0:0]   wire_add_sub_cella_20cout;
-	wire  [0:0]   wire_add_sub_cella_21cout;
-	wire  [0:0]   wire_add_sub_cella_22cout;
-	wire  [0:0]   wire_add_sub_cella_23cout;
-	wire  [0:0]   wire_add_sub_cella_24cout;
-	wire  [0:0]   wire_add_sub_cella_25cout;
-	wire  [0:0]   wire_add_sub_cella_26cout;
-	wire  [0:0]   wire_add_sub_cella_27cout;
-	wire  [0:0]   wire_add_sub_cella_28cout;
-	wire  [0:0]   wire_add_sub_cella_29cout;
-	wire  [0:0]   wire_add_sub_cella_30cout;
-	wire  [31:0]   wire_add_sub_cella_dataa;
-	wire  [31:0]   wire_add_sub_cella_datab;
-	wire  [31:0]   wire_add_sub_cella_regout;
-
-	stratix_lcell   add_sub_cella_0
-	( 
-	.aclr(aclr),
-	.cin(1'b1),
-	.clk(clock),
-	.cout(wire_add_sub_cella_0cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[0:0]),
-	.datab(wire_add_sub_cella_datab[0:0]),
-	.ena(clken),
-	.regout(wire_add_sub_cella_regout[0:0]));
-	defparam
-		add_sub_cella_0.cin_used = "true",
-		add_sub_cella_0.lut_mask = "69b2",
-		add_sub_cella_0.operation_mode = "arithmetic",
-		add_sub_cella_0.sum_lutc_input = "cin",
-		add_sub_cella_0.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_1
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_0cout[0:0]),
-	.clk(clock),
-	.cout(wire_add_sub_cella_1cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[1:1]),
-	.datab(wire_add_sub_cella_datab[1:1]),
-	.ena(clken),
-	.regout(wire_add_sub_cella_regout[1:1]));
-	defparam
-		add_sub_cella_1.cin_used = "true",
-		add_sub_cella_1.lut_mask = "69b2",
-		add_sub_cella_1.operation_mode = "arithmetic",
-		add_sub_cella_1.sum_lutc_input = "cin",
-		add_sub_cella_1.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_2
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_1cout[0:0]),
-	.clk(clock),
-	.cout(wire_add_sub_cella_2cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[2:2]),
-	.datab(wire_add_sub_cella_datab[2:2]),
-	.ena(clken),
-	.regout(wire_add_sub_cella_regout[2:2]));
-	defparam
-		add_sub_cella_2.cin_used = "true",
-		add_sub_cella_2.lut_mask = "69b2",
-		add_sub_cella_2.operation_mode = "arithmetic",
-		add_sub_cella_2.sum_lutc_input = "cin",
-		add_sub_cella_2.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_3
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_2cout[0:0]),
-	.clk(clock),
-	.cout(wire_add_sub_cella_3cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[3:3]),
-	.datab(wire_add_sub_cella_datab[3:3]),
-	.ena(clken),
-	.regout(wire_add_sub_cella_regout[3:3]));
-	defparam
-		add_sub_cella_3.cin_used = "true",
-		add_sub_cella_3.lut_mask = "69b2",
-		add_sub_cella_3.operation_mode = "arithmetic",
-		add_sub_cella_3.sum_lutc_input = "cin",
-		add_sub_cella_3.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_4
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_3cout[0:0]),
-	.clk(clock),
-	.cout(wire_add_sub_cella_4cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[4:4]),
-	.datab(wire_add_sub_cella_datab[4:4]),
-	.ena(clken),
-	.regout(wire_add_sub_cella_regout[4:4]));
-	defparam
-		add_sub_cella_4.cin_used = "true",
-		add_sub_cella_4.lut_mask = "69b2",
-		add_sub_cella_4.operation_mode = "arithmetic",
-		add_sub_cella_4.sum_lutc_input = "cin",
-		add_sub_cella_4.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_5
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_4cout[0:0]),
-	.clk(clock),
-	.cout(wire_add_sub_cella_5cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[5:5]),
-	.datab(wire_add_sub_cella_datab[5:5]),
-	.ena(clken),
-	.regout(wire_add_sub_cella_regout[5:5]));
-	defparam
-		add_sub_cella_5.cin_used = "true",
-		add_sub_cella_5.lut_mask = "69b2",
-		add_sub_cella_5.operation_mode = "arithmetic",
-		add_sub_cella_5.sum_lutc_input = "cin",
-		add_sub_cella_5.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_6
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_5cout[0:0]),
-	.clk(clock),
-	.cout(wire_add_sub_cella_6cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[6:6]),
-	.datab(wire_add_sub_cella_datab[6:6]),
-	.ena(clken),
-	.regout(wire_add_sub_cella_regout[6:6]));
-	defparam
-		add_sub_cella_6.cin_used = "true",
-		add_sub_cella_6.lut_mask = "69b2",
-		add_sub_cella_6.operation_mode = "arithmetic",
-		add_sub_cella_6.sum_lutc_input = "cin",
-		add_sub_cella_6.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_7
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_6cout[0:0]),
-	.clk(clock),
-	.cout(wire_add_sub_cella_7cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[7:7]),
-	.datab(wire_add_sub_cella_datab[7:7]),
-	.ena(clken),
-	.regout(wire_add_sub_cella_regout[7:7]));
-	defparam
-		add_sub_cella_7.cin_used = "true",
-		add_sub_cella_7.lut_mask = "69b2",
-		add_sub_cella_7.operation_mode = "arithmetic",
-		add_sub_cella_7.sum_lutc_input = "cin",
-		add_sub_cella_7.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_8
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_7cout[0:0]),
-	.clk(clock),
-	.cout(wire_add_sub_cella_8cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[8:8]),
-	.datab(wire_add_sub_cella_datab[8:8]),
-	.ena(clken),
-	.regout(wire_add_sub_cella_regout[8:8]));
-	defparam
-		add_sub_cella_8.cin_used = "true",
-		add_sub_cella_8.lut_mask = "69b2",
-		add_sub_cella_8.operation_mode = "arithmetic",
-		add_sub_cella_8.sum_lutc_input = "cin",
-		add_sub_cella_8.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_9
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_8cout[0:0]),
-	.clk(clock),
-	.cout(wire_add_sub_cella_9cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[9:9]),
-	.datab(wire_add_sub_cella_datab[9:9]),
-	.ena(clken),
-	.regout(wire_add_sub_cella_regout[9:9]));
-	defparam
-		add_sub_cella_9.cin_used = "true",
-		add_sub_cella_9.lut_mask = "69b2",
-		add_sub_cella_9.operation_mode = "arithmetic",
-		add_sub_cella_9.sum_lutc_input = "cin",
-		add_sub_cella_9.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_10
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_9cout[0:0]),
-	.clk(clock),
-	.cout(wire_add_sub_cella_10cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[10:10]),
-	.datab(wire_add_sub_cella_datab[10:10]),
-	.ena(clken),
-	.regout(wire_add_sub_cella_regout[10:10]));
-	defparam
-		add_sub_cella_10.cin_used = "true",
-		add_sub_cella_10.lut_mask = "69b2",
-		add_sub_cella_10.operation_mode = "arithmetic",
-		add_sub_cella_10.sum_lutc_input = "cin",
-		add_sub_cella_10.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_11
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_10cout[0:0]),
-	.clk(clock),
-	.cout(wire_add_sub_cella_11cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[11:11]),
-	.datab(wire_add_sub_cella_datab[11:11]),
-	.ena(clken),
-	.regout(wire_add_sub_cella_regout[11:11]));
-	defparam
-		add_sub_cella_11.cin_used = "true",
-		add_sub_cella_11.lut_mask = "69b2",
-		add_sub_cella_11.operation_mode = "arithmetic",
-		add_sub_cella_11.sum_lutc_input = "cin",
-		add_sub_cella_11.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_12
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_11cout[0:0]),
-	.clk(clock),
-	.cout(wire_add_sub_cella_12cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[12:12]),
-	.datab(wire_add_sub_cella_datab[12:12]),
-	.ena(clken),
-	.regout(wire_add_sub_cella_regout[12:12]));
-	defparam
-		add_sub_cella_12.cin_used = "true",
-		add_sub_cella_12.lut_mask = "69b2",
-		add_sub_cella_12.operation_mode = "arithmetic",
-		add_sub_cella_12.sum_lutc_input = "cin",
-		add_sub_cella_12.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_13
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_12cout[0:0]),
-	.clk(clock),
-	.cout(wire_add_sub_cella_13cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[13:13]),
-	.datab(wire_add_sub_cella_datab[13:13]),
-	.ena(clken),
-	.regout(wire_add_sub_cella_regout[13:13]));
-	defparam
-		add_sub_cella_13.cin_used = "true",
-		add_sub_cella_13.lut_mask = "69b2",
-		add_sub_cella_13.operation_mode = "arithmetic",
-		add_sub_cella_13.sum_lutc_input = "cin",
-		add_sub_cella_13.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_14
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_13cout[0:0]),
-	.clk(clock),
-	.cout(wire_add_sub_cella_14cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[14:14]),
-	.datab(wire_add_sub_cella_datab[14:14]),
-	.ena(clken),
-	.regout(wire_add_sub_cella_regout[14:14]));
-	defparam
-		add_sub_cella_14.cin_used = "true",
-		add_sub_cella_14.lut_mask = "69b2",
-		add_sub_cella_14.operation_mode = "arithmetic",
-		add_sub_cella_14.sum_lutc_input = "cin",
-		add_sub_cella_14.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_15
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_14cout[0:0]),
-	.clk(clock),
-	.cout(wire_add_sub_cella_15cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[15:15]),
-	.datab(wire_add_sub_cella_datab[15:15]),
-	.ena(clken),
-	.regout(wire_add_sub_cella_regout[15:15]));
-	defparam
-		add_sub_cella_15.cin_used = "true",
-		add_sub_cella_15.lut_mask = "69b2",
-		add_sub_cella_15.operation_mode = "arithmetic",
-		add_sub_cella_15.sum_lutc_input = "cin",
-		add_sub_cella_15.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_16
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_15cout[0:0]),
-	.clk(clock),
-	.cout(wire_add_sub_cella_16cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[16:16]),
-	.datab(wire_add_sub_cella_datab[16:16]),
-	.ena(clken),
-	.regout(wire_add_sub_cella_regout[16:16]));
-	defparam
-		add_sub_cella_16.cin_used = "true",
-		add_sub_cella_16.lut_mask = "69b2",
-		add_sub_cella_16.operation_mode = "arithmetic",
-		add_sub_cella_16.sum_lutc_input = "cin",
-		add_sub_cella_16.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_17
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_16cout[0:0]),
-	.clk(clock),
-	.cout(wire_add_sub_cella_17cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[17:17]),
-	.datab(wire_add_sub_cella_datab[17:17]),
-	.ena(clken),
-	.regout(wire_add_sub_cella_regout[17:17]));
-	defparam
-		add_sub_cella_17.cin_used = "true",
-		add_sub_cella_17.lut_mask = "69b2",
-		add_sub_cella_17.operation_mode = "arithmetic",
-		add_sub_cella_17.sum_lutc_input = "cin",
-		add_sub_cella_17.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_18
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_17cout[0:0]),
-	.clk(clock),
-	.cout(wire_add_sub_cella_18cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[18:18]),
-	.datab(wire_add_sub_cella_datab[18:18]),
-	.ena(clken),
-	.regout(wire_add_sub_cella_regout[18:18]));
-	defparam
-		add_sub_cella_18.cin_used = "true",
-		add_sub_cella_18.lut_mask = "69b2",
-		add_sub_cella_18.operation_mode = "arithmetic",
-		add_sub_cella_18.sum_lutc_input = "cin",
-		add_sub_cella_18.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_19
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_18cout[0:0]),
-	.clk(clock),
-	.cout(wire_add_sub_cella_19cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[19:19]),
-	.datab(wire_add_sub_cella_datab[19:19]),
-	.ena(clken),
-	.regout(wire_add_sub_cella_regout[19:19]));
-	defparam
-		add_sub_cella_19.cin_used = "true",
-		add_sub_cella_19.lut_mask = "69b2",
-		add_sub_cella_19.operation_mode = "arithmetic",
-		add_sub_cella_19.sum_lutc_input = "cin",
-		add_sub_cella_19.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_20
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_19cout[0:0]),
-	.clk(clock),
-	.cout(wire_add_sub_cella_20cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[20:20]),
-	.datab(wire_add_sub_cella_datab[20:20]),
-	.ena(clken),
-	.regout(wire_add_sub_cella_regout[20:20]));
-	defparam
-		add_sub_cella_20.cin_used = "true",
-		add_sub_cella_20.lut_mask = "69b2",
-		add_sub_cella_20.operation_mode = "arithmetic",
-		add_sub_cella_20.sum_lutc_input = "cin",
-		add_sub_cella_20.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_21
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_20cout[0:0]),
-	.clk(clock),
-	.cout(wire_add_sub_cella_21cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[21:21]),
-	.datab(wire_add_sub_cella_datab[21:21]),
-	.ena(clken),
-	.regout(wire_add_sub_cella_regout[21:21]));
-	defparam
-		add_sub_cella_21.cin_used = "true",
-		add_sub_cella_21.lut_mask = "69b2",
-		add_sub_cella_21.operation_mode = "arithmetic",
-		add_sub_cella_21.sum_lutc_input = "cin",
-		add_sub_cella_21.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_22
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_21cout[0:0]),
-	.clk(clock),
-	.cout(wire_add_sub_cella_22cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[22:22]),
-	.datab(wire_add_sub_cella_datab[22:22]),
-	.ena(clken),
-	.regout(wire_add_sub_cella_regout[22:22]));
-	defparam
-		add_sub_cella_22.cin_used = "true",
-		add_sub_cella_22.lut_mask = "69b2",
-		add_sub_cella_22.operation_mode = "arithmetic",
-		add_sub_cella_22.sum_lutc_input = "cin",
-		add_sub_cella_22.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_23
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_22cout[0:0]),
-	.clk(clock),
-	.cout(wire_add_sub_cella_23cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[23:23]),
-	.datab(wire_add_sub_cella_datab[23:23]),
-	.ena(clken),
-	.regout(wire_add_sub_cella_regout[23:23]));
-	defparam
-		add_sub_cella_23.cin_used = "true",
-		add_sub_cella_23.lut_mask = "69b2",
-		add_sub_cella_23.operation_mode = "arithmetic",
-		add_sub_cella_23.sum_lutc_input = "cin",
-		add_sub_cella_23.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_24
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_23cout[0:0]),
-	.clk(clock),
-	.cout(wire_add_sub_cella_24cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[24:24]),
-	.datab(wire_add_sub_cella_datab[24:24]),
-	.ena(clken),
-	.regout(wire_add_sub_cella_regout[24:24]));
-	defparam
-		add_sub_cella_24.cin_used = "true",
-		add_sub_cella_24.lut_mask = "69b2",
-		add_sub_cella_24.operation_mode = "arithmetic",
-		add_sub_cella_24.sum_lutc_input = "cin",
-		add_sub_cella_24.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_25
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_24cout[0:0]),
-	.clk(clock),
-	.cout(wire_add_sub_cella_25cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[25:25]),
-	.datab(wire_add_sub_cella_datab[25:25]),
-	.ena(clken),
-	.regout(wire_add_sub_cella_regout[25:25]));
-	defparam
-		add_sub_cella_25.cin_used = "true",
-		add_sub_cella_25.lut_mask = "69b2",
-		add_sub_cella_25.operation_mode = "arithmetic",
-		add_sub_cella_25.sum_lutc_input = "cin",
-		add_sub_cella_25.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_26
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_25cout[0:0]),
-	.clk(clock),
-	.cout(wire_add_sub_cella_26cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[26:26]),
-	.datab(wire_add_sub_cella_datab[26:26]),
-	.ena(clken),
-	.regout(wire_add_sub_cella_regout[26:26]));
-	defparam
-		add_sub_cella_26.cin_used = "true",
-		add_sub_cella_26.lut_mask = "69b2",
-		add_sub_cella_26.operation_mode = "arithmetic",
-		add_sub_cella_26.sum_lutc_input = "cin",
-		add_sub_cella_26.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_27
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_26cout[0:0]),
-	.clk(clock),
-	.cout(wire_add_sub_cella_27cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[27:27]),
-	.datab(wire_add_sub_cella_datab[27:27]),
-	.ena(clken),
-	.regout(wire_add_sub_cella_regout[27:27]));
-	defparam
-		add_sub_cella_27.cin_used = "true",
-		add_sub_cella_27.lut_mask = "69b2",
-		add_sub_cella_27.operation_mode = "arithmetic",
-		add_sub_cella_27.sum_lutc_input = "cin",
-		add_sub_cella_27.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_28
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_27cout[0:0]),
-	.clk(clock),
-	.cout(wire_add_sub_cella_28cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[28:28]),
-	.datab(wire_add_sub_cella_datab[28:28]),
-	.ena(clken),
-	.regout(wire_add_sub_cella_regout[28:28]));
-	defparam
-		add_sub_cella_28.cin_used = "true",
-		add_sub_cella_28.lut_mask = "69b2",
-		add_sub_cella_28.operation_mode = "arithmetic",
-		add_sub_cella_28.sum_lutc_input = "cin",
-		add_sub_cella_28.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_29
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_28cout[0:0]),
-	.clk(clock),
-	.cout(wire_add_sub_cella_29cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[29:29]),
-	.datab(wire_add_sub_cella_datab[29:29]),
-	.ena(clken),
-	.regout(wire_add_sub_cella_regout[29:29]));
-	defparam
-		add_sub_cella_29.cin_used = "true",
-		add_sub_cella_29.lut_mask = "69b2",
-		add_sub_cella_29.operation_mode = "arithmetic",
-		add_sub_cella_29.sum_lutc_input = "cin",
-		add_sub_cella_29.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_30
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_29cout[0:0]),
-	.clk(clock),
-	.cout(wire_add_sub_cella_30cout[0:0]),
-	.dataa(wire_add_sub_cella_dataa[30:30]),
-	.datab(wire_add_sub_cella_datab[30:30]),
-	.ena(clken),
-	.regout(wire_add_sub_cella_regout[30:30]));
-	defparam
-		add_sub_cella_30.cin_used = "true",
-		add_sub_cella_30.lut_mask = "69b2",
-		add_sub_cella_30.operation_mode = "arithmetic",
-		add_sub_cella_30.sum_lutc_input = "cin",
-		add_sub_cella_30.lpm_type = "stratix_lcell";
-	stratix_lcell   add_sub_cella_31
-	( 
-	.aclr(aclr),
-	.cin(wire_add_sub_cella_30cout[0:0]),
-	.clk(clock),
-	.dataa(wire_add_sub_cella_dataa[31:31]),
-	.datab(wire_add_sub_cella_datab[31:31]),
-	.ena(clken),
-	.regout(wire_add_sub_cella_regout[31:31]));
-	defparam
-		add_sub_cella_31.cin_used = "true",
-		add_sub_cella_31.lut_mask = "6969",
-		add_sub_cella_31.operation_mode = "normal",
-		add_sub_cella_31.sum_lutc_input = "cin",
-		add_sub_cella_31.lpm_type = "stratix_lcell";
-	assign
-		wire_add_sub_cella_dataa = dataa,
-		wire_add_sub_cella_datab = datab;
-	assign
-		result = wire_add_sub_cella_regout;
-endmodule //sub32_add_sub_cqa
-//VALID FILE
-
-
-module sub32 (
-	dataa,
-	datab,
-	clock,
-	aclr,
-	clken,
-	result)/* synthesis synthesis_clearbox = 1 */;
-
-	input	[31:0]  dataa;
-	input	[31:0]  datab;
-	input	  clock;
-	input	  aclr;
-	input	  clken;
-	output	[31:0]  result;
-
-	wire [31:0] sub_wire0;
-	wire [31:0] result = sub_wire0[31:0];
-
-	sub32_add_sub_cqa	sub32_add_sub_cqa_component (
-				.dataa (dataa),
-				.datab (datab),
-				.clken (clken),
-				.aclr (aclr),
-				.clock (clock),
-				.result (sub_wire0));
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: nBit NUMERIC "32"
-// Retrieval info: PRIVATE: Function NUMERIC "1"
-// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
-// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
-// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
-// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
-// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
-// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-// Retrieval info: PRIVATE: Overflow NUMERIC "0"
-// Retrieval info: PRIVATE: Latency NUMERIC "1"
-// Retrieval info: PRIVATE: aclr NUMERIC "1"
-// Retrieval info: PRIVATE: clken NUMERIC "1"
-// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
-// Retrieval info: CONSTANT: LPM_DIRECTION STRING "SUB"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
-// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO"
-// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
-// Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL dataa[31..0]
-// Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL datab[31..0]
-// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
-// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL clken
-// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
-// Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
-// Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
-// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
-// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
diff --git a/fpga/usrp1/megacells/sub32_bb.v b/fpga/usrp1/megacells/sub32_bb.v
deleted file mode 100755
index 488ab51cf..000000000
--- a/fpga/usrp1/megacells/sub32_bb.v
+++ /dev/null
@@ -1,37 +0,0 @@
-//Copyright (C) 1991-2003 Altera Corporation
-//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-//support information,  device programming or simulation file,  and any other
-//associated  documentation or information  provided by  Altera  or a partner
-//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-//other  use  of such  megafunction  design,  netlist,  support  information,
-//device programming or simulation file,  or any other  related documentation
-//or information  is prohibited  for  any  other purpose,  including, but not
-//limited to  modification,  reverse engineering,  de-compiling, or use  with
-//any other  silicon devices,  unless such use is  explicitly  licensed under
-//a separate agreement with  Altera  or a megafunction partner.  Title to the
-//intellectual property,  including patents,  copyrights,  trademarks,  trade
-//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-//support  information,  device programming or simulation file,  or any other
-//related documentation or information provided by  Altera  or a megafunction
-//partner, remains with Altera, the megafunction partner, or their respective
-//licensors. No other licenses, including any licenses needed under any third
-//party's intellectual property, are provided herein.
-
-module sub32 (
-	dataa,
-	datab,
-	clock,
-	aclr,
-	clken,
-	result)/* synthesis synthesis_clearbox = 1 */;
-
-	input	[31:0]  dataa;
-	input	[31:0]  datab;
-	input	  clock;
-	input	  aclr;
-	input	  clken;
-	output	[31:0]  result;
-
-endmodule
-
diff --git a/fpga/usrp1/megacells/sub32_inst.v b/fpga/usrp1/megacells/sub32_inst.v
deleted file mode 100755
index 1916fc524..000000000
--- a/fpga/usrp1/megacells/sub32_inst.v
+++ /dev/null
@@ -1,8 +0,0 @@
-sub32	sub32_inst (
-	.dataa ( dataa_sig ),
-	.datab ( datab_sig ),
-	.clock ( clock_sig ),
-	.aclr ( aclr_sig ),
-	.clken ( clken_sig ),
-	.result ( result_sig )
-	);