Removed copy of FPGA source files.

1 files changed, 0 insertions, 37 deletions

diff --git a/fpga/usrp1/megacells/sub32_bb.v b/fpga/usrp1/megacells/sub32_bb.v
deleted file mode 100755
index 488ab51cf..000000000
--- a/fpga/usrp1/megacells/sub32_bb.v
+++ /dev/null
@@ -1,37 +0,0 @@
-//Copyright (C) 1991-2003 Altera Corporation
-//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-//support information,  device programming or simulation file,  and any other
-//associated  documentation or information  provided by  Altera  or a partner
-//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-//other  use  of such  megafunction  design,  netlist,  support  information,
-//device programming or simulation file,  or any other  related documentation
-//or information  is prohibited  for  any  other purpose,  including, but not
-//limited to  modification,  reverse engineering,  de-compiling, or use  with
-//any other  silicon devices,  unless such use is  explicitly  licensed under
-//a separate agreement with  Altera  or a megafunction partner.  Title to the
-//intellectual property,  including patents,  copyrights,  trademarks,  trade
-//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-//support  information,  device programming or simulation file,  or any other
-//related documentation or information provided by  Altera  or a megafunction
-//partner, remains with Altera, the megafunction partner, or their respective
-//licensors. No other licenses, including any licenses needed under any third
-//party's intellectual property, are provided herein.
-
-module sub32 (
-	dataa,
-	datab,
-	clock,
-	aclr,
-	clken,
-	result)/* synthesis synthesis_clearbox = 1 */;
-
-	input	[31:0]  dataa;
-	input	[31:0]  datab;
-	input	  clock;
-	input	  aclr;
-	input	  clken;
-	output	[31:0]  result;
-
-endmodule
-