Merge branch 'master' of git@ettus.sourcerepo.com:ettus/uhdpriv into usrp_e

Conflicts:
	.gitignore

1 files changed, 31 insertions, 0 deletions

diff --git a/fpga/usrp1/megacells/fifo_4kx16_dc.cmp b/fpga/usrp1/megacells/fifo_4kx16_dc.cmp
new file mode 100755
index 000000000..356de4d62
--- /dev/null
+++ b/fpga/usrp1/megacells/fifo_4kx16_dc.cmp
@@ -0,0 +1,31 @@
+--Copyright (C) 1991-2006 Altera Corporation

+--Your use of Altera Corporation's design tools, logic functions 

+--and other software and tools, and its AMPP partner logic 

+--functions, and any output files any of the foregoing 

+--(including device programming or simulation files), and any 

+--associated documentation or information are expressly subject 

+--to the terms and conditions of the Altera Program License 

+--Subscription Agreement, Altera MegaCore Function License 

+--Agreement, or other applicable license agreement, including, 

+--without limitation, that your use is for the sole purpose of 

+--programming logic devices manufactured by Altera and sold by 

+--Altera or its authorized distributors.  Please refer to the 

+--applicable agreement for further details.

+

+

+component fifo_4kx16_dc

+	PORT

+	(

+		aclr		: IN STD_LOGIC  := '0';

+		data		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);

+		rdclk		: IN STD_LOGIC ;

+		rdreq		: IN STD_LOGIC ;

+		wrclk		: IN STD_LOGIC ;

+		wrreq		: IN STD_LOGIC ;

+		q		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0);

+		rdempty		: OUT STD_LOGIC ;

+		rdusedw		: OUT STD_LOGIC_VECTOR (11 DOWNTO 0);

+		wrfull		: OUT STD_LOGIC ;

+		wrusedw		: OUT STD_LOGIC_VECTOR (11 DOWNTO 0)

+	);

+end component;