Removed copy of FPGA source files.

1 files changed, 0 insertions, 30 deletions

diff --git a/fpga/usrp1/megacells/fifo_1kx16.cmp b/fpga/usrp1/megacells/fifo_1kx16.cmp
deleted file mode 100755
index 9b2c2c0c3..000000000
--- a/fpga/usrp1/megacells/fifo_1kx16.cmp
+++ /dev/null
@@ -1,30 +0,0 @@
---Copyright (C) 1991-2006 Altera Corporation

---Your use of Altera Corporation's design tools, logic functions 

---and other software and tools, and its AMPP partner logic 

---functions, and any output files any of the foregoing 

---(including device programming or simulation files), and any 

---associated documentation or information are expressly subject 

---to the terms and conditions of the Altera Program License 

---Subscription Agreement, Altera MegaCore Function License 

---Agreement, or other applicable license agreement, including, 

---without limitation, that your use is for the sole purpose of 

---programming logic devices manufactured by Altera and sold by 

---Altera or its authorized distributors.  Please refer to the 

---applicable agreement for further details.

-

-

-component fifo_1kx16

-	PORT

-	(

-		aclr		: IN STD_LOGIC ;

-		clock		: IN STD_LOGIC ;

-		data		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);

-		rdreq		: IN STD_LOGIC ;

-		wrreq		: IN STD_LOGIC ;

-		almost_empty		: OUT STD_LOGIC ;

-		empty		: OUT STD_LOGIC ;

-		full		: OUT STD_LOGIC ;

-		q		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0);

-		usedw		: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)

-	);

-end component;