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authorJosh Blum <josh@joshknows.com>2010-04-15 11:24:24 -0700
committerJosh Blum <josh@joshknows.com>2010-04-15 11:24:24 -0700
commit05d77f772317de5d925301aa11bb9a880656dd05 (patch)
tree0910bfb9265fab1644a3d3a1706719f1b038d193 /fpga/usrp1/megacells/add32.bsf
parent16818dc98e97b69a028c47e66ebfb16e32565533 (diff)
downloaduhd-05d77f772317de5d925301aa11bb9a880656dd05.tar.gz
uhd-05d77f772317de5d925301aa11bb9a880656dd05.tar.bz2
uhd-05d77f772317de5d925301aa11bb9a880656dd05.zip
moved usrp1 and usrp2 fpga dirs into fpga subdirectory
Diffstat (limited to 'fpga/usrp1/megacells/add32.bsf')
-rwxr-xr-xfpga/usrp1/megacells/add32.bsf62
1 files changed, 62 insertions, 0 deletions
diff --git a/fpga/usrp1/megacells/add32.bsf b/fpga/usrp1/megacells/add32.bsf
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index 000000000..b2da9fc2a
--- /dev/null
+++ b/fpga/usrp1/megacells/add32.bsf
@@ -0,0 +1,62 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2003 Altera Corporation
+Any megafunction design, and related netlist (encrypted or decrypted),
+support information, device programming or simulation file, and any other
+associated documentation or information provided by Altera or a partner
+under Altera's Megafunction Partnership Program may be used only
+to program PLD devices (but not masked PLD devices) from Altera. Any
+other use of such megafunction design, netlist, support information,
+device programming or simulation file, or any other related documentation
+or information is prohibited for any other purpose, including, but not
+limited to modification, reverse engineering, de-compiling, or use with
+any other silicon devices, unless such use is explicitly licensed under
+a separate agreement with Altera or a megafunction partner. Title to the
+intellectual property, including patents, copyrights, trademarks, trade
+secrets, or maskworks, embodied in any such megafunction design, netlist,
+support information, device programming or simulation file, or any other
+related documentation or information provided by Altera or a megafunction
+partner, remains with Altera, the megafunction partner, or their respective
+licensors. No other licenses, including any licenses needed under any third
+party's intellectual property, are provided herein.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+ (rect 0 0 160 96)
+ (text "add32" (rect 58 2 111 21)(font "Arial" (font_size 10)))
+ (text "inst" (rect 8 77 31 92)(font "Arial" ))
+ (port
+ (pt 0 40)
+ (input)
+ (text "dataa[7..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
+ (text "dataa[7..0]" (rect 4 24 66 40)(font "Arial" (font_size 8)))
+ (line (pt 0 40)(pt 64 40)(line_width 3))
+ )
+ (port
+ (pt 0 72)
+ (input)
+ (text "datab[7..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
+ (text "datab[7..0]" (rect 4 56 66 72)(font "Arial" (font_size 8)))
+ (line (pt 0 72)(pt 64 72)(line_width 3))
+ )
+ (port
+ (pt 160 56)
+ (output)
+ (text "result[7..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
+ (text "result[7..0]" (rect 95 40 157 56)(font "Arial" (font_size 8)))
+ (line (pt 160 56)(pt 96 56)(line_width 3))
+ )
+ (drawing
+ (text "A" (rect 66 32 75 48)(font "Arial" (font_size 8)))
+ (text "B" (rect 66 64 75 80)(font "Arial" (font_size 8)))
+ (text "A+B" (rect 68 48 94 64)(font "Arial" (font_size 8)))
+ (line (pt 64 32)(pt 96 40)(line_width 1))
+ (line (pt 96 40)(pt 96 72)(line_width 1))
+ (line (pt 96 72)(pt 64 80)(line_width 1))
+ (line (pt 64 80)(pt 64 32)(line_width 1))
+ )
+)