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| author | Josh Blum <josh@joshknows.com> | 2010-04-15 11:24:41 -0700 |
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| committer | Josh Blum <josh@joshknows.com> | 2010-04-15 11:24:41 -0700 |
| commit | 3a196c5d614fbec9b1010b3082245614ba5e0dc9 (patch) | |
| tree | 784f075298f5d86c9e7429ce0ff977deaf4315c8 /fpga/usrp1/TODO | |
| parent | cbf7a0916f0455743d8446a8edc0f0775e3e63ed (diff) | |
| parent | 05d77f772317de5d925301aa11bb9a880656dd05 (diff) | |
| download | uhd-3a196c5d614fbec9b1010b3082245614ba5e0dc9.tar.gz uhd-3a196c5d614fbec9b1010b3082245614ba5e0dc9.tar.bz2 uhd-3a196c5d614fbec9b1010b3082245614ba5e0dc9.zip | |
Merge branch 'udp'
Diffstat (limited to 'fpga/usrp1/TODO')
| -rw-r--r-- | fpga/usrp1/TODO | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/fpga/usrp1/TODO b/fpga/usrp1/TODO new file mode 100644 index 000000000..76287c3d4 --- /dev/null +++ b/fpga/usrp1/TODO @@ -0,0 +1,23 @@ + + +Area Reduction +============== +Reduce one or both stages of dec/interp to max rate of 8 instead of 16 +Optimize CICs to minimize registers +Reduce width of RX CORDIC +Fix CORDIC wasted logic cells from bad synthesis +Progressively narrow x,y,z on CORDIC +16-bit wide FIFOs, split IQ/channels on other side (?) + +Enhancements +============ +Halfband filter in Spartan 3 +Muxing of inputs +Switch over to newfc +RAM interface? + +Other +===== +Capture/Transmit straight samples (no DUC/DDC) + + |