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| author | Josh Blum <josh@joshknows.com> | 2010-04-15 11:24:24 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-04-15 11:24:24 -0700 |
| commit | 05d77f772317de5d925301aa11bb9a880656dd05 (patch) | |
| tree | 0910bfb9265fab1644a3d3a1706719f1b038d193 /fpga/usrp1/Makefile.extra | |
| parent | 16818dc98e97b69a028c47e66ebfb16e32565533 (diff) | |
| download | uhd-05d77f772317de5d925301aa11bb9a880656dd05.tar.gz uhd-05d77f772317de5d925301aa11bb9a880656dd05.tar.bz2 uhd-05d77f772317de5d925301aa11bb9a880656dd05.zip | |
moved usrp1 and usrp2 fpga dirs into fpga subdirectory
Diffstat (limited to 'fpga/usrp1/Makefile.extra')
| -rw-r--r-- | fpga/usrp1/Makefile.extra | 181 |
1 files changed, 181 insertions, 0 deletions
diff --git a/fpga/usrp1/Makefile.extra b/fpga/usrp1/Makefile.extra new file mode 100644 index 000000000..56df23c98 --- /dev/null +++ b/fpga/usrp1/Makefile.extra @@ -0,0 +1,181 @@ +EXTRA_DIST = \ + gen_makefile_extra.py \ + inband_lib/chan_fifo_reader.v \ + inband_lib/channel_demux.v \ + inband_lib/channel_ram.v \ + inband_lib/cmd_reader.v \ + inband_lib/packet_builder.v \ + inband_lib/register_io.v \ + inband_lib/rx_buffer_inband.v \ + inband_lib/tx_buffer_inband.v \ + inband_lib/tx_packer.v \ + inband_lib/usb_packet_fifo.v \ + megacells/accum32.bsf \ + megacells/accum32.cmp \ + megacells/accum32.inc \ + megacells/accum32.v \ + megacells/accum32_bb.v \ + megacells/accum32_inst.v \ + megacells/add32.bsf \ + megacells/add32.cmp \ + megacells/add32.inc \ + megacells/add32.v \ + megacells/add32_bb.v \ + megacells/add32_inst.v \ + megacells/addsub16.bsf \ + megacells/addsub16.cmp \ + megacells/addsub16.inc \ + megacells/addsub16.v \ + megacells/addsub16_bb.v \ + megacells/addsub16_inst.v \ + megacells/bustri.bsf \ + megacells/bustri.cmp \ + megacells/bustri.inc \ + megacells/bustri.v \ + megacells/bustri_bb.v \ + megacells/bustri_inst.v \ + megacells/clk_doubler.v \ + megacells/clk_doubler_bb.v \ + megacells/dspclkpll.v \ + megacells/dspclkpll_bb.v \ + megacells/fifo_1kx16.bsf \ + megacells/fifo_1kx16.cmp \ + megacells/fifo_1kx16.inc \ + megacells/fifo_1kx16.v \ + megacells/fifo_1kx16_bb.v \ + megacells/fifo_1kx16_inst.v \ + megacells/fifo_2k.v \ + megacells/fifo_2k_bb.v \ + megacells/fifo_4k.v \ + megacells/fifo_4k_18.v \ + megacells/fifo_4k_bb.v \ + megacells/fifo_4kx16_dc.bsf \ + megacells/fifo_4kx16_dc.cmp \ + megacells/fifo_4kx16_dc.inc \ + megacells/fifo_4kx16_dc.v \ + megacells/fifo_4kx16_dc_bb.v \ + megacells/fifo_4kx16_dc_inst.v \ + megacells/mylpm_addsub.bsf \ + megacells/mylpm_addsub.cmp \ + megacells/mylpm_addsub.inc \ + megacells/mylpm_addsub.v \ + megacells/mylpm_addsub_bb.v \ + megacells/mylpm_addsub_inst.v \ + megacells/pll.v \ + megacells/pll_bb.v \ + megacells/pll_inst.v \ + megacells/sub32.bsf \ + megacells/sub32.cmp \ + megacells/sub32.inc \ + megacells/sub32.v \ + megacells/sub32_bb.v \ + megacells/sub32_inst.v \ + models/bustri.v \ + models/fifo.v \ + models/fifo_1c_1k.v \ + models/fifo_1c_2k.v \ + models/fifo_1c_4k.v \ + models/fifo_1k.v \ + models/fifo_2k.v \ + models/fifo_4k.v \ + models/fifo_4k_18.v \ + models/pll.v \ + models/ssram.v \ + sdr_lib/adc_interface.v \ + sdr_lib/atr_delay.v \ + sdr_lib/bidir_reg.v \ + sdr_lib/cic_dec_shifter.v \ + sdr_lib/cic_decim.v \ + sdr_lib/cic_int_shifter.v \ + sdr_lib/cic_interp.v \ + sdr_lib/clk_divider.v \ + sdr_lib/cordic.v \ + sdr_lib/cordic_stage.v \ + sdr_lib/ddc.v \ + sdr_lib/dpram.v \ + sdr_lib/duc.v \ + sdr_lib/ext_fifo.v \ + sdr_lib/gen_cordic_consts.py \ + sdr_lib/gen_sync.v \ + sdr_lib/hb/acc.v \ + sdr_lib/hb/coeff_rom.v \ + sdr_lib/hb/halfband_decim.v \ + sdr_lib/hb/halfband_interp.v \ + sdr_lib/hb/hbd_tb/test_hbd.v \ + sdr_lib/hb/mac.v \ + sdr_lib/hb/mult.v \ + sdr_lib/hb/ram16_2port.v \ + sdr_lib/hb/ram16_2sum.v \ + sdr_lib/hb/ram32_2sum.v \ + sdr_lib/io_pins.v \ + sdr_lib/master_control.v \ + sdr_lib/master_control_multi.v \ + sdr_lib/phase_acc.v \ + sdr_lib/ram.v \ + sdr_lib/ram16.v \ + sdr_lib/ram32.v \ + sdr_lib/ram64.v \ + sdr_lib/rssi.v \ + sdr_lib/rx_buffer.v \ + sdr_lib/rx_chain.v \ + sdr_lib/rx_chain_dual.v \ + sdr_lib/rx_dcoffset.v \ + sdr_lib/serial_io.v \ + sdr_lib/setting_reg.v \ + sdr_lib/setting_reg_masked.v \ + sdr_lib/sign_extend.v \ + sdr_lib/strobe_gen.v \ + sdr_lib/tx_buffer.v \ + sdr_lib/tx_chain.v \ + sdr_lib/tx_chain_hb.v \ + tb/cbus_tb.v \ + tb/cordic_tb.v \ + tb/decim_tb.v \ + tb/fullchip_tb.v \ + tb/interp_tb.v \ + tb/justinterp_tb.v \ + tb/usrp_tasks.v \ + toplevel/include/common_config_1rxhb_1tx.vh \ + toplevel/include/common_config_2rx_0tx.vh \ + toplevel/include/common_config_2rxhb_0tx.vh \ + toplevel/include/common_config_2rxhb_2tx.vh \ + toplevel/include/common_config_4rx_0tx.vh \ + toplevel/include/common_config_bottom.vh \ + toplevel/mrfm/biquad_2stage.v \ + toplevel/mrfm/biquad_6stage.v \ + toplevel/mrfm/mrfm.csf \ + toplevel/mrfm/mrfm.esf \ + toplevel/mrfm/mrfm.psf \ + toplevel/mrfm/mrfm.py \ + toplevel/mrfm/mrfm.qpf \ + toplevel/mrfm/mrfm.qsf \ + toplevel/mrfm/mrfm.v \ + toplevel/mrfm/mrfm.vh \ + toplevel/mrfm/mrfm_compensator.v \ + toplevel/mrfm/mrfm_fft.py \ + toplevel/mrfm/mrfm_proc.v \ + toplevel/mrfm/shifter.v \ + toplevel/sizetest/sizetest.csf \ + toplevel/sizetest/sizetest.psf \ + toplevel/sizetest/sizetest.v \ + toplevel/usrp_inband_usb/config.vh \ + toplevel/usrp_inband_usb/usrp_inband_usb.csf \ + toplevel/usrp_inband_usb/usrp_inband_usb.esf \ + toplevel/usrp_inband_usb/usrp_inband_usb.psf \ + toplevel/usrp_inband_usb/usrp_inband_usb.qpf \ + toplevel/usrp_inband_usb/usrp_inband_usb.qsf \ + toplevel/usrp_inband_usb/usrp_inband_usb.v \ + toplevel/usrp_multi/config.vh \ + toplevel/usrp_multi/usrp_multi.csf \ + toplevel/usrp_multi/usrp_multi.esf \ + toplevel/usrp_multi/usrp_multi.psf \ + toplevel/usrp_multi/usrp_multi.qpf \ + toplevel/usrp_multi/usrp_multi.qsf \ + toplevel/usrp_multi/usrp_multi.v \ + toplevel/usrp_std/config.vh \ + toplevel/usrp_std/usrp_std.csf \ + toplevel/usrp_std/usrp_std.esf \ + toplevel/usrp_std/usrp_std.psf \ + toplevel/usrp_std/usrp_std.qpf \ + toplevel/usrp_std/usrp_std.qsf \ + toplevel/usrp_std/usrp_std.v |