fpga: tools: Add modelsim to make sim targets

This adds a simulation make target that allows you to run ModelSim
natively rather than through Vivado.

Adds or modifies the following simulation make targets:
make vlint    - Brake up compilation to Verilog/SystemVerilog/VHDL
make modelsim - Depends on make vlint and invokes modelsim

Adds the following variables:
MODELSIM_ARGS - Added to invocation of ModelSim
SVLOG_ARGS    - Added to SystemVerilog invocation of vlog
VLOG_ARGS     - Added to Verilog invocation of vlog
VHDL_ARGS     - Added to VHDL invocation of vcom

1 files changed, 3 insertions, 2 deletions

diff --git a/fpga/docs/usrp3/sim/running_testbenches.md b/fpga/docs/usrp3/sim/running_testbenches.md
index 2e2068e5e..4afd66fe0 100644
--- a/fpga/docs/usrp3/sim/running_testbenches.md
+++ b/fpga/docs/usrp3/sim/running_testbenches.md
@@ -17,8 +17,9 @@ all supported simulator targets. Currently, the following targets will work:
     cleanall:   Cleanup everything!
     xsim:       Run the simulation using the Xilinx Vivado Simulator
     xclean:     Cleanup Xilinx Vivado Simulator intermediate files
-    vsim:       Run the simulation using Modelsim
-    vclean:     Cleanup Modelsim intermediate files
+    vsim:       Run the simulation using ModelSim simulator via Vivado 
+    modelsim:   Runs the simulation using ModelSim without Vivado
+    vclean:     Cleanup ModelSim intermediate files
 
 
 ## Using Xilinx Vivado XSim