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authorJosh Blum <josh@joshknows.com>2012-02-04 15:12:37 -0800
committerJosh Blum <josh@joshknows.com>2012-02-04 15:12:37 -0800
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treeeae9f0133f86f66f13fbfb35c9efd8fcf6c50a06 /fpga/README
parent04e9d23d5f9f300164182597b0e0525063bd91e4 (diff)
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-This is a placeholder for the fpga code (verilog, makefiles, corgens...)
-
-The layout should have a common library and various top level builds
-and testbenches that are organized hierarchically.