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authorJosh Blum <josh@joshknows.com>2012-02-17 18:18:26 -0800
committerJosh Blum <josh@joshknows.com>2012-02-17 18:18:26 -0800
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-This is a placeholder for the fpga code (verilog, makefiles, corgens...)
-
-The layout should have a common library and various top level builds
-and testbenches that are organized hierarchically.