fpga: ci: Add build definitions for FPGA CI

Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com>
Co-authored-by: Max Köhler <max.koehler@ni.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>

7 files changed, 483 insertions, 0 deletions

diff --git a/fpga/.ci/scripts/cleanup_incomplete_ip_builds.py b/fpga/.ci/scripts/cleanup_incomplete_ip_builds.py
new file mode 100644
index 000000000..75c08db72
--- /dev/null
+++ b/fpga/.ci/scripts/cleanup_incomplete_ip_builds.py
@@ -0,0 +1,35 @@
+#!/usr/bin/env python3
+#
+# Copyright 2021 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+# Description:
+#
+#   Our pipelines reuse IP builds to save time. In the case where an IP build
+#   fails or is terminated before completion, it is sometimes necessary to
+#   clean up the build so that the next build can complete properly. This
+#   script searches for and deletes any incomplete IP builds.
+#
+
+import argparse
+import os
+import shutil
+
+# argument parsing
+parser = argparse.ArgumentParser(description="This script removes all directories where the .build_lock file still exists")
+parser.add_argument('--directory', '-d', required=True, help='directory to search for lock files (recursively)')
+args = parser.parse_args()
+
+# search .build_lock files
+lockFiles = []
+for root, dirs, files in os.walk(args.directory):
+  for file in files:
+    if file == ".build_lock":
+      lockFiles.append(os.path.join(root, file))
+
+# remove all directories containing lock files
+for lockFile in lockFiles:
+  dirPath = os.path.dirname(lockFile)
+  print("delete " + dirPath)
+  shutil.rmtree(dirPath)
diff --git a/fpga/.ci/templates/check_clean_repo_steps.yml b/fpga/.ci/templates/check_clean_repo_steps.yml
new file mode 100644
index 000000000..7ac034dd8
--- /dev/null
+++ b/fpga/.ci/templates/check_clean_repo_steps.yml
@@ -0,0 +1,58 @@
+#
+# Copyright 2021 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+# Description:
+#
+#   Checks for a clean repository (no untracked or modified files).
+#
+
+parameters:
+  # Directory to execute the commands in
+  - name: directory
+    type: string
+    default: $(Agent.BuildDirectory)/s
+
+steps:
+# Windows based calls
+- powershell: |
+    # Using git status as a way to check for a clean repo can produce
+    # misleading results when the line endings have been modified (XmlParse has
+    # a tendency to modify line endings). "git diff" seems to produce more
+    # reliable results, and the --exit-code is useful for detecting a change/no
+    # change summary.
+
+    # Check for modified files
+    git diff --exit-code;          if (-not $?) {throw "git diff should be empty"}
+
+    # Check for modified files that are staged
+    git diff --cached --exit-code; if (-not $?) {throw "git diff of staged changes should be empty"}
+
+    # Check for untracked files
+    git add .                      # add all untracked files
+    git diff --cached --exit-code; if (-not $?) {throw "There should be no untracked files"}
+  displayName: 'Check clean repository (Windows)'
+  condition: eq( variables['Agent.OS'], 'Windows_NT' )
+  workingDirectory: ${{ parameters.directory }}
+
+# Linux based calls
+- bash: |
+    # Using git status as a way to check for a clean repo can produce
+    # misleading results when the line endings have been modified (XmlParse has
+    # a tendency to modify line endings). "git diff" seems to produce more
+    # reliable results, and the --exit-code is useful for detecting a change/no
+    # change summary.
+
+    # Check for modified files
+    git diff --exit-code          || exit 1
+
+    # Checked for modified files that are staged
+    git diff --cached --exit-code || exit 1
+
+    # Check for untracked files
+    git add .                      # add all untracked files
+    git diff --cached --exit-code || exit 1
+  displayName: 'Check clean repository (Linux)'
+  condition: eq( variables['Agent.OS'], 'Linux' )
+  workingDirectory: ${{ parameters.directory }}
diff --git a/fpga/.ci/templates/fpga_build.yml b/fpga/.ci/templates/fpga_build.yml
new file mode 100644
index 000000000..dbc41b790
--- /dev/null
+++ b/fpga/.ci/templates/fpga_build.yml
@@ -0,0 +1,82 @@
+#
+# Copyright 2021 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+# Description:
+#
+#   This template should be used for all FPGA builds within the uhddev
+#   repository. Exports the FPGA build results (bitfile, device tree and timing
+#   report from build directory) as artifacts 'FPGA image <target>'.
+#
+#   See description for the parameters below.
+#
+
+parameters:
+  ### Required parameters
+  # FPGA target to be built e.g. X410_XG
+  - name: target
+    type: string
+
+  ### Optional parameters
+  # Set to true if the intermediate files from build-<target> directory should
+  # be exported for debugging as artifact 'FPGA build <target> (<attempt>)'
+  - name: debug
+    type: boolean
+    default: false
+  # Checkout repository in a clean state as described in
+  # https://docs.microsoft.com/en-us/azure/devops/pipelines/yaml-schema?view=azure-devops&tabs=schema%2Cparameter-schema#checkout
+  - name: clean
+    type: boolean
+    default: true
+  # Default timeout of 4h
+  - name: timeout
+    type: number
+    default: 240
+
+jobs:
+- job: FPGA_${{ parameters.target }}
+  displayName: 'Build FPGA ${{ parameters.target }}'
+  pool:
+    name: de-dre-lab
+    demands:
+    - ettus_fpga_build
+    - vivado2019.1
+  timeoutInMinutes: ${{ parameters.timeout }}
+  steps:
+    # Currently limited to be executed in same repo.
+    # Removes all unversioned files if necessary.
+    # Checkout path defined by single repository case in
+    # https://docs.microsoft.com/en-us/azure/devops/pipelines/repos/multi-repo-checkout?view=azure-devops#checkout-path
+    - checkout: self
+      clean: ${{ parameters.clean }}
+
+    # Remove incomplete IP builds due to aborted previous runs.
+    - bash: |
+        python3 cleanup_incomplete_ip_builds.py -d fpga/usrp3/top/x400
+      workingDirectory: $(Agent.BuildDirectory)/s/fpga/.ci/scripts/
+      displayName: 'Incomplete IP Cleanup'
+
+    # Clean export directories and run FPGA build.
+    - bash: |
+        rm -rf build
+        rm -rf build-${{ parameters.target }}
+        source setupenv.sh
+        make ${{ parameters.target }}
+      workingDirectory: $(Agent.BuildDirectory)/s/fpga/usrp3/top/x400
+      displayName: 'Build Target'
+
+    # Publish the final result only if all previous steps passed
+    - publish: $(Agent.BuildDirectory)/s/fpga/usrp3/top/x400/build
+      artifact: 'FPGA image ${{ parameters.target }}'
+      displayName: 'Publish FPGA'
+
+    # Publish intermediate files.
+    - publish: $(Agent.BuildDirectory)/s/fpga/usrp3/top/x400/build-${{ parameters.target }}
+      artifact: 'FPGA build ${{ parameters.target }} ($(System.JobAttempt))'
+      condition: and(always(), eq('${{ parameters.debug }}', true))
+      displayName: 'Publish Build Directory'
+
+    # Check if FPGA build left any untracked files.
+    - ${{ if eq(parameters.debug, true) }}:
+      - template: check_clean_repo_steps.yml
diff --git a/fpga/.ci/templates/mb_cpld_build.yml b/fpga/.ci/templates/mb_cpld_build.yml
new file mode 100644
index 000000000..53aa0736f
--- /dev/null
+++ b/fpga/.ci/templates/mb_cpld_build.yml
@@ -0,0 +1,67 @@
+#
+# Copyright 2021 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+# Description:
+#
+#   This template is used to build the MB CPLD within the uhddev repository.
+#   Exports the CPLD build results (from build directory) as artifacts 'MB CPLD
+#   image'.
+#
+#   See description for the parameters below.
+#
+
+parameters:
+  ### Optional parameters
+  # Set to true if the intermediate files from build-<target> directory should
+  # be exported for debugging as artifact 'MB CPLD build (<attempt>)'
+  - name: debug
+    type: boolean
+    default: false
+  # Checkout repository in a clean state as described in
+  # https://docs.microsoft.com/en-us/azure/devops/pipelines/yaml-schema?view=azure-devops&tabs=schema%2Cparameter-schema#checkout
+  - name: clean
+    type: boolean
+    default: true
+
+jobs:
+- job: MB_CPLD
+  displayName: 'Build MB CPLD'
+  pool:
+    name: de-dre-lab
+    demands:
+    - ettus_fpga_build
+    - quartus18.1_lite
+  timeoutInMinutes: 30
+  steps:
+    # Currently limited to be executed in same repo.
+    # Removes all unversioned files if necessary.
+    # Checkout path defined by single repository case in
+    # https://docs.microsoft.com/en-us/azure/devops/pipelines/repos/multi-repo-checkout?view=azure-devops#checkout-path
+    - checkout: self
+      clean: ${{ parameters.clean }}
+
+    # Run CPLD build
+    # Increase license server timeout as there might appear timeouts during
+    # static timing analysis which end up setting the build to fail.
+    - script: |
+        call set FLEXLM_TIMEOUT=20000000
+        call make
+      workingDirectory: $(Agent.BuildDirectory)/s/fpga/usrp3/top/x400/cpld
+      displayName: 'Build CPLD'
+
+    # Publish the final result only if all previous steps passed
+    - publish: $(Agent.BuildDirectory)/s/fpga/usrp3/top/x400/cpld/build
+      artifact: 'MB CPLD image'
+      displayName: 'Publish CPLD'
+
+    # always publish intermediate files
+    - publish: $(Agent.BuildDirectory)/s/fpga/usrp3/top/x400/cpld/output_files
+      artifact: 'MB CPLD build ($(System.JobAttempt))'
+      condition: and(always(), eq('${{ parameters.debug }}', true))
+      displayName: 'Publish Build Directory'
+
+    # Check if FPGA build left any untracked files.
+    - ${{ if eq(parameters.debug, true) }}:
+      - template: check_clean_repo_steps.yml
diff --git a/fpga/.ci/templates/regmap.yml b/fpga/.ci/templates/regmap.yml
new file mode 100644
index 000000000..b477ddc06
--- /dev/null
+++ b/fpga/.ci/templates/regmap.yml
@@ -0,0 +1,60 @@
+#
+# Copyright 2021 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+# Description:
+#
+#   This template is used to build the FPGA register map within the uhddev
+#   repository. Exports the regmap as artifact 'Regmap'.
+#
+#   See description for the parameters below.
+#
+
+parameters:
+  ### Optional parameters
+  # Set to true to check existence of temporary files after job completion
+  - name: debug
+    type: boolean
+    default: false
+  # Checkout repository in a clean state as described in
+  # https://docs.microsoft.com/en-us/azure/devops/pipelines/yaml-schema?view=azure-devops&tabs=schema%2Cparameter-schema#checkout
+  - name: clean
+    type: boolean
+    default: true
+
+jobs:
+- job: Regmap
+  displayName: 'Generate Register Map'
+  pool:
+    name: de-dre-lab
+    demands:
+    - hwSetup
+  timeoutInMinutes: 30
+  steps:
+    # Currently limited to be executed in same repo.
+    # Removes all unversioned files if necessary.
+    # Checkout path defined by single repository case in
+    # https://docs.microsoft.com/en-us/azure/devops/pipelines/repos/multi-repo-checkout?view=azure-devops#checkout-path
+    - checkout: self
+      clean: ${{ parameters.clean }}
+
+    - script: |
+        call hwSetup
+        call make regmap
+      workingDirectory: $(Agent.BuildDirectory)/s/fpga/nitools/x400/fpga
+      displayName: 'XmlParse'
+
+    # Publish the final result only if all previous steps passed
+    - publish: $(Agent.BuildDirectory)/s/fpga/usrp3/top/x400/doc
+      artifact: 'FPGA regmap'
+      displayName: 'Publish Regmap'
+
+    # Check if FPGA build left any untracked files.
+    - ${{ if eq(parameters.debug, true) }}:
+      # Generated regmap has issue with line endings.
+      # Staging the files resolves these changes and still report any
+      # modifications for the check below.
+      - script: git add -A
+        displayName: 'Stage all files'
+      - template: check_clean_repo_steps.yml
diff --git a/fpga/.ci/templates/zbx_cpld_build.yml b/fpga/.ci/templates/zbx_cpld_build.yml
new file mode 100644
index 000000000..b1fb598f2
--- /dev/null
+++ b/fpga/.ci/templates/zbx_cpld_build.yml
@@ -0,0 +1,67 @@
+#
+# Copyright 2021 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+# Description:
+#
+#   This template is used to build the ZBX daughterboard CPLD within the uhddev
+#   repository. Exports the CPLD build results (from build directory) as
+#   artifacts 'ZBX CPLD image'.
+#
+#   See description for the parameters below.
+#
+
+parameters:
+  ### Optional parameters
+  # Set to true if the intermediate files from build-<target> directory should
+  # be exported for debugging as artifact 'ZBX CPLD build (<attempt>)'
+  - name: debug
+    type: boolean
+    default: false
+  # Checkout repository in a clean state as described in
+  # https://docs.microsoft.com/en-us/azure/devops/pipelines/yaml-schema?view=azure-devops&tabs=schema%2Cparameter-schema#checkout
+  - name: clean
+    type: boolean
+    default: true
+
+jobs:
+- job: ZBX_CPLD
+  displayName: 'Build ZBX CPLD'
+  pool:
+    name: de-dre-lab
+    demands:
+    - ettus_fpga_build
+    - quartus18.1_lite
+  timeoutInMinutes: 30
+  steps:
+    # Currently limited to be executed in same repo.
+    # Removes all unversioned files if necessary.
+    # Checkout path defined by single repository case in
+    # https://docs.microsoft.com/en-us/azure/devops/pipelines/repos/multi-repo-checkout?view=azure-devops#checkout-path
+    - checkout: self
+      clean: ${{ parameters.clean }}
+
+    # Run CPLD build
+    # Increase license server timeout as there might appear timeouts during
+    # static timing analysis which end up setting the build to fail.
+    - script: |
+        call set FLEXLM_TIMEOUT=20000000
+        call make
+      workingDirectory: $(Agent.BuildDirectory)/s/fpga/usrp3/top/x400/dboards/zbx/cpld
+      displayName: 'Build CPLD'
+
+    # Publish the final result only if all previous steps passed
+    - publish: $(Agent.BuildDirectory)/s/fpga/usrp3/top/x400/dboards/zbx/cpld/build
+      artifact: 'ZBX CPLD image'
+      displayName: 'Publish CPLD'
+
+    # Always publish intermediate files
+    - publish: $(Agent.BuildDirectory)/s/fpga/usrp3/top/x400/dboards/zbx/cpld/output_files
+      artifact: 'ZBX CPLD build ($(System.JobAttempt))'
+      condition: and(always(), eq('${{ parameters.debug }}', true))
+      displayName: 'Publish Build Directory'
+
+    # Check if FPGA build left any untracked files.
+    - ${{ if eq(parameters.debug, true) }}:
+      - template: check_clean_repo_steps.yml
diff --git a/fpga/.ci/x4xx-pr-check.yml b/fpga/.ci/x4xx-pr-check.yml
new file mode 100644
index 000000000..3de9f674d
--- /dev/null
+++ b/fpga/.ci/x4xx-pr-check.yml
@@ -0,0 +1,114 @@
+#
+# Copyright 2021 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+# Description:
+#
+#   This pipeline is used to test building  the FPGA and CPLD for each pull
+#   request.
+#
+#   See https://aka.ms/yaml for pipeline YAML documentation.
+#
+
+trigger:
+- none
+
+# Filter for target branches and paths on PRs. See:
+# https://docs.microsoft.com/en-us/azure/devops/pipelines/build/triggers?view=azure-devops&tabs=yaml#pr-triggers
+pr:
+  branches:
+    include:
+    - master
+  paths:
+    include:
+    - fpga/usrp3/lib
+    - fpga/usrp3/tools
+    - fpga/usrp3/top/x400
+    - fpga/.ci
+
+jobs:
+# -------------------------------------------------------------------
+# Build XG FPGA (100 MHz)
+# -------------------------------------------------------------------
+- template: templates/fpga_build.yml
+  parameters:
+    target: X410_XG_100
+    debug: true  # to be able to debug any failed attempts
+    clean: false # for speedup of PR testing
+    timeout: 360
+
+# -------------------------------------------------------------------
+# Build X4 FPGA (200 MHz)
+# -------------------------------------------------------------------
+- template: templates/fpga_build.yml
+  parameters:
+    target: X410_X4_200
+    debug: true  # to be able to debug any failed attempts
+    clean: false # for speedup of PR testing
+    timeout: 360
+
+# -------------------------------------------------------------------
+# Build C1 FPGA (400 MHz)
+# -------------------------------------------------------------------
+- template: templates/fpga_build.yml
+  parameters:
+    target: X410_C1_400
+    debug: true  # to be able to debug any failed attempts
+    clean: false # for speedup of PR testing
+    timeout: 360
+
+# -------------------------------------------------------------------
+# Make CPLD
+# -------------------------------------------------------------------
+#- template: templates/mb_cpld_build.yml
+#  parameters:
+#    debug: true  # to be able to debug any failed attempts
+
+# -------------------------------------------------------------------
+# Make ZBX CPLD
+# -------------------------------------------------------------------
+#- template: templates/zbx_cpld_build.yml
+#  parameters:
+#    debug: true  # to be able to debug any failed attempts
+
+# -------------------------------------------------------------------
+# Build IP
+# -------------------------------------------------------------------
+- job: IP
+  displayName: 'Build IP'
+  pool:
+    name: de-dre-lab
+    demands:
+    - ettus_fpga_build
+    - vivado2019.1
+  timeoutInMinutes: 120
+  steps:
+    - checkout: self
+      clean: false
+
+    - bash: |
+        python3 cleanup_incomplete_ip_builds.py -d $BUILD_SOURCESDIRECTORY/fpga/usrp3/top/x400
+      workingDirectory: fpga/.ci/scripts/
+      displayName: 'Incomplete IP Cleanup'
+
+    # Delete everything except for the build-ip directory, which is expected to
+    # remain for speed-up.
+    - bash: |
+        git clean -xdff -e build-ip
+      displayName: 'git clean'
+
+    - bash: |
+        source setupenv.sh
+        make X410_IP
+      workingDirectory: fpga/usrp3/top/x400
+
+    - publish: fpga/usrp3/top/x400/build-ip
+      artifact: 'IP ($(System.JobAttempt))'
+      condition: failed()
+
+    - publish: fpga/usrp3/top/x400/build-ip
+      artifact: 'IP'
+      condition: succeeded()
+
+    - template: templates/check_clean_repo_steps.yml