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authorHumberto Jimenez <humberto.jimenez@ni.com>2022-03-25 16:40:20 -0500
committerWade Fife <wade.fife@ettus.com>2022-03-30 14:27:23 -0500
commitcdd83b78427da44ca924d969f121654024e6e041 (patch)
tree9f9c1595e726091ee64d399a1eed768bcd92764b /fpga/.ci/templates
parente1d98d2bcd21cae4807021564815b6d766575f73 (diff)
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fpga: ci: Add X4_400 to CI targets default list
Diffstat (limited to 'fpga/.ci/templates')
-rw-r--r--fpga/.ci/templates/stages-fpga-pipeline.yml24
1 files changed, 15 insertions, 9 deletions
diff --git a/fpga/.ci/templates/stages-fpga-pipeline.yml b/fpga/.ci/templates/stages-fpga-pipeline.yml
index 3bd98e390..5be4a0b36 100644
--- a/fpga/.ci/templates/stages-fpga-pipeline.yml
+++ b/fpga/.ci/templates/stages-fpga-pipeline.yml
@@ -22,6 +22,14 @@ parameters:
- name: clean_ip_build
type: boolean
default: false
+# Option to publish intermediate files
+- name: publish_int_files
+ type: boolean
+ default: false
+# Create images package
+- name: package_images
+ type: boolean
+ default: false
# Build X410 FPGA targets
- name: build_x410
type: boolean
@@ -33,14 +41,12 @@ parameters:
X410_X4_200:
target_name: X410_X4_200
timeout: 480
-# Option to publish intermediate files
-- name: publish_int_files
- type: boolean
- default: false
-# Create images package
-- name: package_images
- type: boolean
- default: false
+ X410_X4_400:
+ target_name: X410_X4_400
+ timeout: 480
+ X410_CG_400:
+ target_name: X410_CG_400
+ timeout: 480
resources:
@@ -81,7 +87,7 @@ stages:
- stage: build_x410_targets_stage
displayName: Build X410 FPGA Targets
dependsOn: build_x410_ip_stage
- condition: and(succeeded('build_x410_ip_stage'), eq('${{ parameters.build_x410 }}', 'true'))
+ condition: succeeded('build_x410_ip_stage')
jobs:
- template: job-build-fpga.yml
parameters: