fpga: ci: Add testbench pipeline

1 files changed, 32 insertions, 0 deletions

diff --git a/fpga/.ci/hwtools/root.py b/fpga/.ci/hwtools/root.py
new file mode 100644
index 000000000..082676df7
--- /dev/null
+++ b/fpga/.ci/hwtools/root.py
@@ -0,0 +1,32 @@
+#!/usr/bin/env python
+#
+# Copyright 2021 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+# Description:
+#
+#   Setup script for configuring the pipeline agent's environment to allow us
+#   to run proprietary EDA vendor tools.
+#
+
+import sys
+
+def do_setup():
+    from rootapiclass import rootapi
+
+    rootapi.set_workspace_name(name="uhddev", pretty_name="UHD FPGA")
+    rootapi.set_major_version("1")
+
+    rootapi.add_tool(name="hwtools", version="head")
+    rootapi.add_tool(name="Vivado",   version="2019.1", allowlater=False)
+    rootapi.add_tool(name="modelsim", version="2020.4", allowlater=True)
+
+def do_finish():
+    pass
+
+def do_publish():
+    pass
+
+if __name__ == "__main__":
+    sys.exit(-1)