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| author | Trung N Tran <trung.tran@ettus.com> | 2017-07-13 14:01:33 -0700 |
|---|---|---|
| committer | Brent Stapleton <bstapleton@g.hmc.edu> | 2018-08-22 14:31:34 -0700 |
| commit | d5c6e34bd3a9e63bfe661e2d8b38ceb85c4d6d18 (patch) | |
| tree | 111cbc296f330a8e944957da46693ceba4e2a36d /fpga-src | |
| parent | 0aede451a2f1006aa67450a7d0a07d18a92be138 (diff) | |
| download | uhd-d5c6e34bd3a9e63bfe661e2d8b38ceb85c4d6d18.tar.gz uhd-d5c6e34bd3a9e63bfe661e2d8b38ceb85c4d6d18.tar.bz2 uhd-d5c6e34bd3a9e63bfe661e2d8b38ceb85c4d6d18.zip | |
RFNoC: Convert SR_READBACK_REG_FIFOSIZE to bytes
Change the RB_FIFOSIZE register to store the FIFO size in bytes
instead of log2 of bytes.
Diffstat (limited to 'fpga-src')
| m--------- | fpga-src | 0 |
1 files changed, 0 insertions, 0 deletions
diff --git a/fpga-src b/fpga-src -Subproject c398755579f01a1d020e742fb7d129950939a5d +Subproject 615d9b8eeb94ee2d19c3b1e7aa526d4999495e0 |