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| author | Martin Braun <martin.braun@ettus.com> | 2019-01-11 13:39:55 -0800 |
|---|---|---|
| committer | Brent Stapleton <brent.stapleton@ettus.com> | 2019-01-15 11:43:11 -0800 |
| commit | 853c2a2263e54c1e1fd9562b479a17122a6d9b37 (patch) | |
| tree | 21cd9504eb524274bf09e09eb1f0d34beb9293bc /fpga-src | |
| parent | 66df76097953ecd3ea7e0154049da949f2306743 (diff) | |
| download | uhd-853c2a2263e54c1e1fd9562b479a17122a6d9b37.tar.gz uhd-853c2a2263e54c1e1fd9562b479a17122a6d9b37.tar.bz2 uhd-853c2a2263e54c1e1fd9562b479a17122a6d9b37.zip | |
docs: Add comments for TwinRX and MCR
The TwinRX dboards only support a master clock rate of 200 MHz, which is
now emphasized in the manual. In addition, the meaning of tick rate,
sampling rate, and master clock rate in the TwinRX context is explained.
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