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| author | Josh Blum <josh@joshknows.com> | 2012-03-06 18:51:31 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-03-23 14:36:56 -0700 |
| commit | 672a77767faf0070e94de0c8acd74328a301cae5 (patch) | |
| tree | 9d838d8d2b7452660fac6aa8e110d3d4ed3a7b9a /firmware | |
| parent | 12223186e7ba8a433ef13945a0e4f4077a3a5542 (diff) | |
| download | uhd-672a77767faf0070e94de0c8acd74328a301cae5.tar.gz uhd-672a77767faf0070e94de0c8acd74328a301cae5.tar.bz2 uhd-672a77767faf0070e94de0c8acd74328a301cae5.zip | |
fifo ctrl: ~usrp2_fifo_ctrl acks, usrp2 DCM workaround, bootloader no blinkie
Diffstat (limited to 'firmware')
| -rw-r--r-- | firmware/zpu/lib/clocks.c | 5 | ||||
| -rw-r--r-- | firmware/zpu/lib/u2_init.c | 2 |
2 files changed, 6 insertions, 1 deletions
diff --git a/firmware/zpu/lib/clocks.c b/firmware/zpu/lib/clocks.c index c1e8ce827..bc1954e13 100644 --- a/firmware/zpu/lib/clocks.c +++ b/firmware/zpu/lib/clocks.c @@ -43,7 +43,10 @@ clocks_init(void) //enable the 100MHz clock output to the FPGA for 50MHz CPU clock clocks_enable_fpga_clk(true, 1); - spi_wait(); + //! Cannot SPI wait since SPI is on DSP clock + //! because DSP clock goes away until DCM reset. + //! However, spi is quick, the cpu is slow, its already ready... + //spi_wait(); //wait for the clock to stabilize while(!clocks_lock_detect()); diff --git a/firmware/zpu/lib/u2_init.c b/firmware/zpu/lib/u2_init.c index 71bd2c594..77c8c0722 100644 --- a/firmware/zpu/lib/u2_init.c +++ b/firmware/zpu/lib/u2_init.c @@ -51,6 +51,7 @@ u2_init(void) hal_enable_ints(); // flash all leds to let us know board is alive +#ifndef BOOTLOADER hal_set_led_src(0x0, 0x1f); /* software ctrl */ hal_set_leds(0x0, 0x1f); mdelay(300); hal_set_leds(LED_E, LED_E); mdelay(300); @@ -61,6 +62,7 @@ u2_init(void) hal_set_leds(0x0, 0x1f); mdelay(100); hal_set_leds(blinks, 0x1f); mdelay(100); } +#endif hal_set_led_src(0x1f & ~LED_D, 0x1f); /* hardware ctrl */ hal_set_leds(LED_D, 0x1f); // Leave one on |