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authorJosh Blum <josh@joshknows.com>2012-01-24 08:27:48 -0800
committerJosh Blum <josh@joshknows.com>2012-01-24 08:27:48 -0800
commitd2e4354f7842d7adbdb11367cd8e98af6e463c14 (patch)
tree8a23d370d2768b9d1363230d00797326d7a7c5dd /firmware/zpu
parentb8e41cbbc9666a9758d0f9f3a57272530716935a (diff)
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usrp2: firmware should reset dsp on icmp pkt
1) This should kill any streaming, the previous calls would just stop continuous streaming 2) The breaks were changed to returns to avoid reprogramming the framer.
Diffstat (limited to 'firmware/zpu')
-rw-r--r--firmware/zpu/apps/txrx_uhd.c18
-rw-r--r--firmware/zpu/lib/memory_map.h1
2 files changed, 8 insertions, 11 deletions
diff --git a/firmware/zpu/apps/txrx_uhd.c b/firmware/zpu/apps/txrx_uhd.c
index f9eedfc7d..8cc108f9d 100644
--- a/firmware/zpu/apps/txrx_uhd.c
+++ b/firmware/zpu/apps/txrx_uhd.c
@@ -54,23 +54,19 @@ static void handle_udp_data_packet(
//handle ICMP destination unreachable
if (payload == NULL) switch(src.port){
case USRP2_UDP_RX_DSP0_PORT:
- //the end continuous streaming command
- sr_rx_ctrl0->cmd = 1 << 31 | 1 << 28; //no samples now
- sr_rx_ctrl0->time_secs = 0;
- sr_rx_ctrl0->time_ticks = 0; //latch the command
- break;
+ //reset dsp to stop streaming
+ sr_rx_ctrl0->clear = 1;
+ return;
case USRP2_UDP_RX_DSP1_PORT:
- //the end continuous streaming command
- sr_rx_ctrl1->cmd = 1 << 31 | 1 << 28; //no samples now
- sr_rx_ctrl1->time_secs = 0;
- sr_rx_ctrl1->time_ticks = 0; //latch the command
- break;
+ //reset dsp to stop streaming
+ sr_rx_ctrl1->clear = 1;
+ return;
case USRP2_UDP_TX_DSP0_PORT:
//end async update packets per second
sr_tx_ctrl->cyc_per_up = 0;
- break;
+ return;
default: return;
}
diff --git a/firmware/zpu/lib/memory_map.h b/firmware/zpu/lib/memory_map.h
index 75727bb23..84298d3c1 100644
--- a/firmware/zpu/lib/memory_map.h
+++ b/firmware/zpu/lib/memory_map.h
@@ -302,6 +302,7 @@ typedef struct {
volatile uint32_t cmd; // {now, chain, num_samples(30)
volatile uint32_t time_secs;
volatile uint32_t time_ticks;
+ volatile uint32_t clear;
} sr_rx_ctrl_t;
#define sr_rx_ctrl0 ((sr_rx_ctrl_t *) _SR_ADDR(SR_RX_CTRL0))