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| author | Josh Blum <josh@joshknows.com> | 2012-03-06 16:32:58 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-03-23 14:36:56 -0700 |
| commit | 12223186e7ba8a433ef13945a0e4f4077a3a5542 (patch) | |
| tree | 2ddcdc4be2f21e9eb1faec62a366b187520845a5 /firmware/zpu | |
| parent | 08e2432cdeeabd7010252b4a747a385e1b189614 (diff) | |
| download | uhd-12223186e7ba8a433ef13945a0e4f4077a3a5542.tar.gz uhd-12223186e7ba8a433ef13945a0e4f4077a3a5542.tar.bz2 uhd-12223186e7ba8a433ef13945a0e4f4077a3a5542.zip | |
fifo ctrl: spi core work and host implementation
Diffstat (limited to 'firmware/zpu')
| -rw-r--r-- | firmware/zpu/lib/memory_map.h | 2 | ||||
| -rw-r--r-- | firmware/zpu/lib/spi.c | 24 |
2 files changed, 11 insertions, 15 deletions
diff --git a/firmware/zpu/lib/memory_map.h b/firmware/zpu/lib/memory_map.h index 8568872d0..4290ee20a 100644 --- a/firmware/zpu/lib/memory_map.h +++ b/firmware/zpu/lib/memory_map.h @@ -122,6 +122,8 @@ typedef struct { volatile uint32_t irqs; } router_status_t; +#define SPI_READY_IRQ (1 << 12) + #define router_status ((router_status_t *) READBACK_BASE) #define readback_mux ((router_status_t *) READBACK_BASE) //alias with a better name diff --git a/firmware/zpu/lib/spi.c b/firmware/zpu/lib/spi.c index de3645fe3..190658d61 100644 --- a/firmware/zpu/lib/spi.c +++ b/firmware/zpu/lib/spi.c @@ -19,17 +19,17 @@ #include "spi.h" #include "memory_map.h" #include "nonstdio.h" -#include "mdelay.h" void spi_init(void) { - spi_core->divider = 100; + spi_core->divider = 10; } void spi_wait(void) { - //assumption that divider is reasonably small - mdelay(1); + while ((readback_mux->irqs & SPI_READY_IRQ) == 0){ + //NOP + } } uint32_t spi_transact(bool readback, int slave, uint32_t data, int length, uint32_t flags) @@ -37,20 +37,14 @@ uint32_t spi_transact(bool readback, int slave, uint32_t data, int length, uint3 uint32_t control_word = 0; control_word |= (slave << SPI_CORE_SLAVE_SELECT_SHIFT); control_word |= (length << SPI_CORE_NUM_BITS_SHIFT); - if ((flags & SPI_PUSH_RISE) != 0) control_word |= (1 << SPI_CORE_DATA_IN_EDGE_SHIFT); - if ((flags & SPI_PUSH_FALL) != 0) control_word |= (0 << SPI_CORE_DATA_IN_EDGE_SHIFT); - if ((flags & SPI_LATCH_RISE) != 0) control_word |= (1 << SPI_CORE_DATA_OUT_EDGE_SHIFT); - if ((flags & SPI_LATCH_FALL) != 0) control_word |= (0 << SPI_CORE_DATA_OUT_EDGE_SHIFT); - - uint32_t data_out_rev = 0; - for (size_t i = 0; i < length; i++){ - const int bit = ((data >> i) & 0x1); - data_out_rev |= (bit << (length - i - 1)); - } + if ((flags & SPI_PUSH_RISE) != 0) control_word |= (1 << SPI_CORE_DATA_OUT_EDGE_SHIFT); + if ((flags & SPI_PUSH_FALL) != 0) control_word |= (0 << SPI_CORE_DATA_OUT_EDGE_SHIFT); + if ((flags & SPI_LATCH_RISE) != 0) control_word |= (1 << SPI_CORE_DATA_IN_EDGE_SHIFT); + if ((flags & SPI_LATCH_FALL) != 0) control_word |= (0 << SPI_CORE_DATA_IN_EDGE_SHIFT); spi_wait(); spi_core->control = control_word; - spi_core->data = data_out_rev; + spi_core->data = (data << (32 - length)); if (readback) spi_wait(); |