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author | Josh Blum <josh@joshknows.com> | 2010-12-27 16:53:59 -0800 |
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committer | Josh Blum <josh@joshknows.com> | 2010-12-27 16:53:59 -0800 |
commit | 57681c7659992eb6b7d78db91f888487d4e2a260 (patch) | |
tree | 36dd430e8221983187f154f4ac2654bc3d2234df /firmware/zpu/usrp2 | |
parent | 60e7e634a2c50f7b19f266b636a9d97aa704dd24 (diff) | |
download | uhd-57681c7659992eb6b7d78db91f888487d4e2a260.tar.gz uhd-57681c7659992eb6b7d78db91f888487d4e2a260.tar.bz2 uhd-57681c7659992eb6b7d78db91f888487d4e2a260.zip |
packet_router: code tweaks, renamed instances of buffer pool, removed unused ctrl reg
Diffstat (limited to 'firmware/zpu/usrp2')
-rw-r--r-- | firmware/zpu/usrp2/memory_map.h | 47 |
1 files changed, 22 insertions, 25 deletions
diff --git a/firmware/zpu/usrp2/memory_map.h b/firmware/zpu/usrp2/memory_map.h index a2de29cdb..ca7453c24 100644 --- a/firmware/zpu/usrp2/memory_map.h +++ b/firmware/zpu/usrp2/memory_map.h @@ -18,7 +18,7 @@ /* Overall Memory Map * 0000-7FFF 32K RAM space (16K on 1500, 24K on 2000, 32K on DSP) - * 8000-BFFF 16K Buffer Pool + * 8000-BFFF 16K Packet Router * C000-FFFF 16K Peripherals */ @@ -45,20 +45,18 @@ #define RAM_BASE 0x0000 //////////////////////////////////////////////////////////////// -// Buffer Pool RAM, Slave 1 +// Packet Router RAM, Slave 1 // -// The buffers themselves are located in Slave 1, Buffer Pool RAM. -// The status registers are in Slave 5, Buffer Pool Status. +// The buffers themselves are located in Slave 1, Packet Router RAM. +// The status registers are in Slave 5, Packet Router Status. // The control register is in Slave 7, Settings Bus. -#define BUFFER_POOL_RAM_BASE 0x8000 +#define ROUTER_RAM_BASE 0x8000 -#define BP_NLINES 0x0200 // number of 32-bit lines in a buffer +#define RAM_NLINES 0x0200 // number of 32-bit lines in a buffer -#define buffer_pool_ram \ - ((uint32_t *) BUFFER_POOL_RAM_BASE) - -#define buffer_ram(n) (&buffer_pool_ram[(n) * BP_NLINES]) +#define _router_ram ((uint32_t *) ROUTER_RAM_BASE) +#define router_ram(n) (&_router_ram[(n) * RAM_NLINES]) ///////////////////////////////////////////////////// @@ -162,13 +160,13 @@ typedef struct { #define gpio_base ((gpio_regs_t *) GPIO_BASE) /////////////////////////////////////////////////// -// Buffer Pool Status, Slave 5 +// Packet Router Status, Slave 5 // -// The buffers themselves are located in Slave 1, Buffer Pool RAM. -// The status registers are in Slave 5, Buffer Pool Status. +// The buffers themselves are located in Slave 1, Packet Router RAM. +// The status registers are in Slave 5, Packet Router Status. // The control register is in Slave 7, Settings Bus. -#define BUFFER_POOL_STATUS_BASE 0xCC00 +#define ROUTER_STATUS_BASE 0xCC00 typedef struct { volatile uint32_t _padding[8]; @@ -178,9 +176,9 @@ typedef struct { volatile uint32_t irqs; volatile uint32_t pri_enc_bp_status; volatile uint32_t cycle_count; -} buffer_pool_status_t; +} router_status_t; -#define buffer_pool_status ((buffer_pool_status_t *) BUFFER_POOL_STATUS_BASE) +#define router_status ((router_status_t *) ROUTER_STATUS_BASE) // The hw_config register @@ -193,7 +191,7 @@ typedef struct { inline static int hwconfig_simulation_p(void) { - return buffer_pool_status->hw_config & HWC_SIMULATION; + return router_status->hw_config & HWC_SIMULATION; } /*! @@ -203,7 +201,7 @@ hwconfig_simulation_p(void) inline static int hwconfig_wishbone_divisor(void) { - return buffer_pool_status->hw_config & HWC_WB_CLK_DIV_MASK; + return router_status->hw_config & HWC_WB_CLK_DIV_MASK; } /////////////////////////////////////////////////// @@ -225,13 +223,13 @@ hwconfig_wishbone_divisor(void) #define MISC_OUTPUT_BASE 0xD400 #define TX_PROTOCOL_ENGINE_BASE 0xD480 #define RX_PROTOCOL_ENGINE_BASE 0xD4C0 -#define BUFFER_POOL_CTRL_BASE 0xD500 +#define ROUTER_CTRL_BASE 0xD500 #define LAST_SETTING_REG 0xD7FC // last valid setting register #define SR_MISC 0 #define SR_TX_PROT_ENG 32 #define SR_RX_PROT_ENG 48 -#define SR_BUFFER_POOL_CTRL 64 +#define SR_ROUTER_CTRL 64 #define SR_UDP_SM 96 #define SR_TX_DSP 208 #define SR_TX_CTRL 224 @@ -243,18 +241,17 @@ hwconfig_wishbone_divisor(void) #define _SR_ADDR(sr) (MISC_OUTPUT_BASE + (sr) * sizeof(uint32_t)) -// --- buffer pool control regs --- +// --- packet router control regs --- typedef struct { - volatile uint32_t misc_ctrl; + volatile uint32_t mode_ctrl; volatile uint32_t ip_addr; - volatile uint32_t ctrl_ports; //ctrl (low 16) other (high 16) volatile uint32_t data_ports; //dsp0 (low 16) dsp1 (high 16) volatile uint32_t cpu_out_ctrl; volatile uint32_t cpu_inp_ctrl; -} buffer_pool_ctrl_t; +} router_ctrl_t; -#define buffer_pool_ctrl ((buffer_pool_ctrl_t *) BUFFER_POOL_CTRL_BASE) +#define router_ctrl ((router_ctrl_t *) ROUTER_CTRL_BASE) // --- misc outputs --- |