Merge branch 'usrp2_fw_clock_cleanup' into usrp2_dual_dsp

3 files changed, 16 insertions, 284 deletions

diff --git a/firmware/zpu/lib/clock_bits.h b/firmware/zpu/lib/clock_bits.h
deleted file mode 100644
index d2052e941..000000000
--- a/firmware/zpu/lib/clock_bits.h
+++ /dev/null
@@ -1,55 +0,0 @@
-//
-// Copyright 2010 Ettus Research LLC
-//
-/*
- * Copyright 2008 Free Software Foundation, Inc.
- * 
- * This file is part of GNU Radio
- * 
- * GNU Radio is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 3, or (at your option)
- * any later version.
- * 
- * GNU Radio is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- * 
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-#ifndef INCLUDED_USRP2_CLOCK_BITS_H
-#define INCLUDED_USRP2_CLOCK_BITS_H
-
-#define	_MC_WE_LOCK			0x0001
-#define	_MC_MIMO_CLK_INPUT		0x0002		// else SMA input
-
-/*
- * Derived masks (use these):
- *
- * We get our input from 1 of three places:
- *  Our free running oscilator, our SMA connector, or from the MIMO connector
- */
-#define	MC_WE_DONT_LOCK			0x0000
-#define	MC_WE_LOCK_TO_SMA		(_MC_WE_LOCK | 0)
-#define	MC_WE_LOCK_TO_MIMO		(_MC_WE_LOCK | _MC_MIMO_CLK_INPUT)
-
-/*
- * Independent of the source of the clock, we may or may not drive our
- * clock onto the mimo connector.  Note that there are dedicated clock
- * signals in each direction, so disaster doesn't occurs if we're
- * unnecessarily providing clock.
- */
-#define	MC_PROVIDE_CLK_TO_MIMO		0x0004
-
-#define MC_REF_CLK_MASK          0x0f
-
-#define MC_PPS_SOURCE_SMA        (0x00 << 4)
-#define MC_PPS_SOURCE_MIMO       (0x01 << 4)
-
-#define MC_PPS_POLARITY_NEG      (0x00 << 5)
-#define MC_PPS_POLARITY_POS      (0x01 << 5)
-
-#endif /* INCLUDED_USRP2_CLOCK_BITS_H */
diff --git a/firmware/zpu/lib/clocks.c b/firmware/zpu/lib/clocks.c
index 2b352a385..c1e8ce827 100644
--- a/firmware/zpu/lib/clocks.c
+++ b/firmware/zpu/lib/clocks.c
@@ -1,4 +1,6 @@
-/* -*- c++ -*- */
+//
+// Copyright 2010-2011 Ettus Research LLC
+//
 /*
  * Copyright 2008 Free Software Foundation, Inc.
  *
@@ -16,119 +18,39 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#ifdef HAVE_CONFIG_H
-#include <config.h>
-#endif
 #include <clocks.h>
-
+#include <stdbool.h>
 #include "memory_map.h"
 #include "ad9510.h"
 #include "spi.h"
-#include "u2_init.h"
 
-//USRP2PLUS clocks:
-//Clock 0: testclk
-//Clock 1: FPGA clk
-//Clock 2: ADC clk
-//Clock 3: DAC clk
-//Clock 4: SER clk
-//Clock 5: TX dboard clk
-//Clock 6: EXP clk
-//Clock 7: RX dboard clk
+/*!
+ * \brief Lock Detect -- Return True if our PLL is locked
+ */
+bool clocks_lock_detect();
 
-//TODO: should have enough brains to init the FPGA clock for USRP2+. all others are suspect.
-//note that without EEPROM support u2_hw_rev_major is going to be incorrect.
+/*!
+ * \brief Enable or disable fpga clock.  Disabling would wedge and require a power cycle.
+ */
+void clocks_enable_fpga_clk(bool enable, int divisor);
 
 void 
 clocks_init(void)
 {
   // Set up basic clocking functions in AD9510
-  ad9510_write_reg(0x45, 0x01); // CLK2 drives distribution
+  ad9510_write_reg(0x45, 0x01);
 
   //enable the 100MHz clock output to the FPGA for 50MHz CPU clock
   clocks_enable_fpga_clk(true, 1);
 
   spi_wait();
 
-  // Set up PLL for 10 MHz reference
-  // Reg 4, A counter, Don't Care
-//  ad9510_write_reg(0x05, 0x00);  // Reg 5, B counter MSBs, 0
-//  ad9510_write_reg(0x06, 0x05);  // Reg 6, B counter LSBs, 5
-  // Reg 7, Loss of reference detect, doesn't work yet, 0
-//  ad9510_write_reg(0x5A, 0x01); // Update Regs
-
-  // Primary clock configuration
-//  clocks_mimo_config(MC_WE_DONT_LOCK);
-
-
   //wait for the clock to stabilize
   while(!clocks_lock_detect());
 
   //issue a reset to the DCM so it locks up to the new freq
   output_regs->clk_ctrl |= CLK_RESET;
-
-  // Set up other clocks
-  //clocks_enable_test_clk(false, 0);
-  //clocks_enable_tx_dboard(false, 0);
-  //clocks_enable_rx_dboard(false, 0);
-//  clocks_enable_eth_phyclk(false, 0); //PHY clk is separate now (u2r4, u2p)
-
-  // Enable clock to ADCs and DACs
-  //clocks_enable_dac_clk(true, 1);
-  //clocks_enable_adc_clk(true, 1);
-}
-
-/*
-void
-clocks_mimo_config(int flags)
-{
-  if (flags & _MC_WE_LOCK){
-    // Reg 8, Charge pump on, dig lock det, positive PFD, 47
-    ad9510_write_reg(0x08, 0x47);
-  }
-  else {
-    // Reg 8, Charge pump off, dig lock det, positive PFD
-    ad9510_write_reg(0x08, 0x00);
-  }
-  
-  // Reg 9, Charge pump current, 0x40=3mA, 0x00=650uA
-  ad9510_write_reg(0x09, 0x00);
-  // Reg A, Prescaler of 2, everything normal 04
-  ad9510_write_reg(0x0A, 0x04);
-  // Reg B, R Div MSBs, 0
-  ad9510_write_reg(0x0B, 0x00);
-  // Reg C, R Div LSBs, 1
-  ad9510_write_reg(0x0C, 0x01);
-  // Reg D, Antibacklash, Digital lock det, 0
-
-  ad9510_write_reg(0x5A, 0x01); // Update Regs
-
-  spi_wait();
-  
-  // Allow for clock switchover
-  // The below masks include 0x10, which issues a reset to the DCM.  
-  if (flags & _MC_WE_LOCK){		// WE LOCK
-    if (flags & _MC_MIMO_CLK_INPUT) {
-      // Turn on ref output and choose the MIMO connector
-      output_regs->clk_ctrl = 0x15;  
-    }
-    else {
-      // turn on ref output and choose the SMA
-      output_regs->clk_ctrl = 0x1C; 
-    }
-  }
-  else {				// WE DONT LOCK
-    // Disable both ext clk inputs
-    output_regs->clk_ctrl = 0x10;
-  }
-
-  // Do we drive a clock onto the MIMO connector?
-//  if (flags & MC_PROVIDE_CLK_TO_MIMO)
-//    clocks_enable_clkexp_out(true,10);
-//  else
-//    clocks_enable_clkexp_out(false,0); 
 }
-*/
 
 bool 
 clocks_lock_detect()
@@ -188,79 +110,9 @@ clocks_enable_XXX_clk(bool enable, int divisor, int reg_en, int reg_div, int mod
   ad9510_write_reg(0x5A, 0x01);  // Update Regs
 }
 
-// Clock 0
-/*void
-clocks_enable_test_clk(bool enable, int divisor)
-{
-  clocks_enable_XXX_clk(enable,divisor,0x3C,0x48,CLOCK_MODE_PECL);
-}*/
-
 // Clock 1
 void
 clocks_enable_fpga_clk(bool enable, int divisor)
 {
   clocks_enable_XXX_clk(enable,divisor,0x3D,0x4A,CLOCK_MODE_PECL);
 }
-/*
-// Clock 2 on Rev 3, Clock 5 on Rev 4, Clock 6 on USRP2+
-void
-clocks_enable_clkexp_out(bool enable, int divisor)
-{
-  if(u2_hw_rev_major == 3)
-    clocks_enable_XXX_clk(enable,divisor,0x3E,0x4C,CLOCK_MODE_PECL);
-  else if(u2_hw_rev_major == 4) {
-    ad9510_write_reg(0x34,0x00);  // Turn on fine delay
-    ad9510_write_reg(0x35,0x00);  // Set Full Scale to nearly 10ns
-    ad9510_write_reg(0x36,0x1c);  // Set fine delay.  0x20 is midscale
-    clocks_enable_XXX_clk(enable,divisor,0x41,0x52,CLOCK_MODE_LVDS);
-  }
-	else if(u2_hw_rev_major == 10) {
-		ad9510_write_reg(0x34, 0x00);
-		ad9510_write_reg(0x35, 0x00);
-		ad9510_write_reg(0x36, 0x1C);
-		clocks_enable_XXX_clk(enable, divisor, 0x42, 0x52, CLOCK_MODE_LVDS);
-	}
-  else
-    putstr("ERR (clocks_enable_clkexp_out): Invalid hw rev, don't know what to do!\n");
-}
-*/
-/*
-// Clock 5 on Rev 3, none (was 2) on Rev 4, none on USRP2+
-void
-clocks_enable_eth_phyclk(bool enable, int divisor)
-{
-  if(u2_hw_rev_major == 3)
-    clocks_enable_XXX_clk(enable,divisor,0x41,0x52,CLOCK_MODE_LVDS);
-  else if(u2_hw_rev_major == 4)
-    clocks_enable_XXX_clk(enable,divisor,0x3E,0x4C,CLOCK_MODE_PECL);
-  else
-    putstr("(clocks_enable_eth_phyclk): no eth PHY clock or invalid hw rev\n"); //not really an error
-}
-*/
-// Clock 3
-/*void
-clocks_enable_dac_clk(bool enable, int divisor)
-{
-  clocks_enable_XXX_clk(enable,divisor,0x3F,0x4E,CLOCK_MODE_PECL);
-}*/
-
-// Clock 4
-/*void
-clocks_enable_adc_clk(bool enable, int divisor)
-{
-  clocks_enable_XXX_clk(enable,divisor,0x40,0x50,CLOCK_MODE_LVDS);
-}*/
-
-// Clock 6
-/*void
-clocks_enable_tx_dboard(bool enable, int divisor)
-{
-  clocks_enable_XXX_clk(enable,divisor,0x42,0x54,CLOCK_MODE_CMOS);
-}*/
-
-// Clock 7
-/*void
-clocks_enable_rx_dboard(bool enable, int divisor)
-{
-  clocks_enable_XXX_clk(enable,divisor,0x43,0x56,CLOCK_MODE_CMOS);
-}*/
diff --git a/firmware/zpu/lib/clocks.h b/firmware/zpu/lib/clocks.h
index 28d1d542f..7bc7a3cda 100644
--- a/firmware/zpu/lib/clocks.h
+++ b/firmware/zpu/lib/clocks.h
@@ -1,5 +1,5 @@
 //
-// Copyright 2010 Ettus Research LLC
+// Copyright 2010-2011 Ettus Research LLC
 //
 /*
  * Copyright 2008 Free Software Foundation, Inc.
@@ -21,75 +21,10 @@
 #ifndef INCLUDED_CLOCKS_H
 #define INCLUDED_CLOCKS_H
 
-/*
- * Routines to configure our multitude of clocks
- */
-
-#include <stdbool.h>
-#include "clock_bits.h"
-
-
 /*!
- * One time call to initialize all clocks to a reasonable state.  We
- * come out of here using our free running 100MHz oscilator and not
- * providing a clock to the MIMO connector (CMC_WE_DONT_LOCK)
+ * One time call to initialize the master clock to a reasonable state.
+ * We come out of here using our free running 100MHz oscillator.
  */
 void clocks_init(void);
 
-
-/*!
- * \brief MIMO clock configuration.
- *
- * Configure our master clock source, and whether or not we drive a
- * clock onto the mimo connector.  See MC_flags in usrp2_mimo_config.h.
- */
-//void clocks_mimo_config(int flags);
-
-/*!
- * \brief Lock Detect -- Return True if our PLL is locked
- */
-bool clocks_lock_detect();
-
-/*!
- * \brief Enable or disable test clock (extra clock signal)
- */
-//void clocks_enable_test_clk(bool enable, int divisor);
-
-/*!
- * \brief Enable or disable fpga clock.  Disabling would wedge and require a power cycle.
- */
-void clocks_enable_fpga_clk(bool enable, int divisor);
-
-/*!
- * \brief Enable or disable clock output sent to MIMO connector
- */
-//void clocks_enable_clkexp_out(bool enable, int divisor);
-
-/*!
- * \brief Enable or disable ethernet phyclk, should always be disabled
- */
-//void clocks_enable_eth_phyclk(bool enable, int divisor);
-
-/*!
- * \brief Enable or disable clock to DAC
- */
-//void clocks_enable_dac_clk(bool enable, int divisor);
-
-/*!
- * \brief Enable or disable clock to ADC
- */
-//void clocks_enable_adc_clk(bool enable, int divisor);
-
-/*!
- * \brief Enable or disable clock to Rx daughterboard
- */
-//void clocks_enable_rx_dboard(bool enable, int divisor);
-
-
-/*!
- * \brief Enable or disable clock to Tx daughterboard
- */
-//void clocks_enable_tx_dboard(bool enable, int divisor);
-
-
 #endif /* INCLUDED_CLOCKS_H */