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| author | Ashish Chaudhari <ashish@ettus.com> | 2018-02-20 11:42:56 -0800 |
|---|---|---|
| committer | Ashish Chaudhari <ashish.chaudhari@ettus.com> | 2018-02-21 16:50:18 -0800 |
| commit | d5109ae99e5da24707a8d7a6d57b96f6deabbede (patch) | |
| tree | 7f06c5cbb5e820323f083731fac0d2477e04c06c /firmware/usrp3 | |
| parent | cf644768c43cc15844e3f1b64f6e363634719f5e (diff) | |
| download | uhd-d5109ae99e5da24707a8d7a6d57b96f6deabbede.tar.gz uhd-d5109ae99e5da24707a8d7a6d57b96f6deabbede.tar.bz2 uhd-d5109ae99e5da24707a8d7a6d57b96f6deabbede.zip | |
rfnoc,x300: Multiple clocking changes
- Moved bus_clk <=> ce_clk crossing to axi_wrapper in FPGA
which resulted in a noc_shell compat bump
- Change x300 bus_clk frequency to 187.5 MHz
Diffstat (limited to 'firmware/usrp3')
| -rwxr-xr-x | firmware/usrp3/x300/x300_aurora_bist.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/firmware/usrp3/x300/x300_aurora_bist.py b/firmware/usrp3/x300/x300_aurora_bist.py index 5f7a22a3b..962494b46 100755 --- a/firmware/usrp3/x300/x300_aurora_bist.py +++ b/firmware/usrp3/x300/x300_aurora_bist.py @@ -61,7 +61,7 @@ MAC_CTRL_PHY_RESET = 0x00000200 MAC_CTRL_BIST_RATE_MSK = 0x000001F8 MAC_CTRL_BIST_RATE_OFFSET = 3 -BUS_CLK_RATE = 166.66e6 +BUS_CLK_RATE = 187.50e6 BIST_MAX_TIME_LIMIT = math.floor(pow(2,48)/BUS_CLK_RATE)-1 ######################################################################## |