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authorAshish Chaudhari <ashish@ettus.com>2015-02-17 12:23:09 -0800
committerAshish Chaudhari <ashish@ettus.com>2015-02-17 12:23:09 -0800
commit230cf5d76ac2417c36713e82bcd0fbe7986b7847 (patch)
tree3b26eddabd81588a32b956d7f1d0ed3f5c42c135 /firmware/usrp3/x300
parent3157734691882662fae4f86475a78db8fee1b441 (diff)
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x300: Multiple firmware fixes for Vivado
- Refactored SFP+ hotplug handler - GigE link state comes from SFP+ status and PHY status - Multiple tracing enhancements - Bumped firmware compat number to 4 - Bumpled FPGA compat number to 10
Diffstat (limited to 'firmware/usrp3/x300')
-rw-r--r--firmware/usrp3/x300/x300_defs.h1
-rw-r--r--firmware/usrp3/x300/x300_init.c34
-rw-r--r--firmware/usrp3/x300/x300_main.c4
3 files changed, 20 insertions, 19 deletions
diff --git a/firmware/usrp3/x300/x300_defs.h b/firmware/usrp3/x300/x300_defs.h
index 65c5d5a23..c4011bd12 100644
--- a/firmware/usrp3/x300/x300_defs.h
+++ b/firmware/usrp3/x300/x300_defs.h
@@ -51,6 +51,7 @@ static const int RB_SPI_RDY = 1;
static const int RB_SPI_DATA = 2;
static const int RB_ETH_TYPE0 = 4;
static const int RB_ETH_TYPE1 = 5;
+static const int RB_FPGA_COMPAT = 6;
static const int RB_SFPP_STATUS0 = 8;
static const int RB_SFPP_STATUS1 = 9;
diff --git a/firmware/usrp3/x300/x300_init.c b/firmware/usrp3/x300/x300_init.c
index 480e68a14..ef97412a2 100644
--- a/firmware/usrp3/x300/x300_init.c
+++ b/firmware/usrp3/x300/x300_init.c
@@ -130,7 +130,11 @@ void x300_init(void)
//udp_uart_init(UART0_BASE, X300_GPSDO_UDP_PORT);
//now we can init the rest with prints
- UHD_FW_TRACE_FSTR(INFO, "[ZPU Init Begin -- CPU CLOCK is %d MHz]", (CPU_CLOCK/1000000));
+ UHD_FW_TRACE(INFO, "[ZPU Initializing]");
+ UHD_FW_TRACE_FSTR(INFO, "-- Firmware Compat Number: %u.%u", (int)X300_FW_COMPAT_MAJOR, (int)X300_FW_COMPAT_MINOR);
+ uint32_t fpga_compat = wb_peek32(SR_ADDR(SET0_BASE, RB_FPGA_COMPAT));
+ UHD_FW_TRACE_FSTR(INFO, "-- FPGA Compat Number: %u.%u", (fpga_compat>>16), (fpga_compat&0xFFFF));
+ UHD_FW_TRACE_FSTR(INFO, "-- Clock Frequency: %u MHz", (CPU_CLOCK/1000000));
//i2c rate init
wb_i2c_init(I2C0_BASE, CPU_CLOCK);
@@ -140,30 +144,26 @@ void x300_init(void)
//hold phy in reset
wb_poke32(SR_ADDR(SET0_BASE, SR_SW_RST), SW_RST_PHY);
- UHD_FW_TRACE_FSTR(INFO, "eth0 is %2dG", ((wb_peek32(SR_ADDR(RB0_BASE, RB_ETH_TYPE0))==1) ? 10 : 1));
- UHD_FW_TRACE_FSTR(INFO, "eth1 is %2dG", ((wb_peek32(SR_ADDR(RB0_BASE, RB_ETH_TYPE1))==1) ? 10 : 1));
-
//setup net stack and eth state machines
init_network();
//phy reset release
wb_poke32(SR_ADDR(SET0_BASE, SR_SW_RST), 0);
- // For eth interfaces, initialize the PHY's
- mdelay(100);
- if (wb_peek32(SR_ADDR(RB0_BASE, RB_ETH_TYPE0)) == 1) {
- xge_ethernet_init(0);
- }
- if (wb_peek32(SR_ADDR(RB0_BASE, RB_ETH_TYPE1)) == 1) {
- xge_ethernet_init(1);
- }
-
//print network summary
for (uint8_t e = 0; e < ethernet_ninterfaces(); e++)
{
- UHD_FW_TRACE_FSTR(INFO, " MAC%u: %s", (int)e, mac_addr_to_str(u3_net_stack_get_mac_addr(e)));
- UHD_FW_TRACE_FSTR(INFO, " IP%u: %s", (int)e, ip_addr_to_str(u3_net_stack_get_ip_addr(e)));
- UHD_FW_TRACE_FSTR(INFO, " SUBNET%u: %s", (int)e, ip_addr_to_str(u3_net_stack_get_subnet(e)));
- UHD_FW_TRACE_FSTR(INFO, " BCAST%u: %s", (int)e, ip_addr_to_str(u3_net_stack_get_bcast(e)));
+ uint32_t offset = SR_ADDR(RB0_BASE, ((e==1)?RB_ETH_TYPE1:RB_ETH_TYPE0));
+ UHD_FW_TRACE_FSTR(INFO, "Ethernet Port %u:", (int)e);
+ UHD_FW_TRACE_FSTR(INFO, "-- PHY: %s", ((wb_peek32(offset)==1) ? "10Gbps" : "1Gbps"));
+ UHD_FW_TRACE_FSTR(INFO, "-- MAC: %s", mac_addr_to_str(u3_net_stack_get_mac_addr(e)));
+ UHD_FW_TRACE_FSTR(INFO, "-- IP: %s", ip_addr_to_str(u3_net_stack_get_ip_addr(e)));
+ UHD_FW_TRACE_FSTR(INFO, "-- SUBNET: %s", ip_addr_to_str(u3_net_stack_get_subnet(e)));
+ UHD_FW_TRACE_FSTR(INFO, "-- BCAST: %s", ip_addr_to_str(u3_net_stack_get_bcast(e)));
}
+
+ // For eth interfaces, initialize the PHY's
+ mdelay(100);
+ ethernet_init(0);
+ ethernet_init(1);
}
diff --git a/firmware/usrp3/x300/x300_main.c b/firmware/usrp3/x300/x300_main.c
index b8c4fb41a..3b812a2c4 100644
--- a/firmware/usrp3/x300/x300_main.c
+++ b/firmware/usrp3/x300/x300_main.c
@@ -445,12 +445,12 @@ int main(void)
static const uint32_t tick_delta = CPU_CLOCK/1000;
if (ticks_passed > tick_delta)
{
+ poll_sfpp_status(0); // Every so often poll XGE Phy to look for SFP+ hotplug events.
+ poll_sfpp_status(1); // Every so often poll XGE Phy to look for SFP+ hotplug events.
handle_link_state(); //deal with router table update
handle_claim(); //deal with the host claim register
update_leds(); //run the link and activity leds
garp(); //send periodic garps
- xge_poll_sfpp_status(0); // Every so often poll XGE Phy to look for SFP+ hotplug events.
- xge_poll_sfpp_status(1); // Every so often poll XGE Phy to look for SFP+ hotplug events.
last_cronjob = wb_peek32(SR_ADDR(RB0_BASE, RB_COUNTER));
}