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| author | Nicholas Corgan <nick.corgan@ettus.com> | 2014-08-15 12:57:10 -0700 |
|---|---|---|
| committer | Nicholas Corgan <nick.corgan@ettus.com> | 2014-08-20 09:42:26 -0700 |
| commit | 2de96cd57c3f19bfa778ccad280ad19170af0967 (patch) | |
| tree | 88e5235bbbc1df0dd5d6ce1883203a09f3e07ea3 /firmware/octoclock/include/octoclock.h | |
| parent | 9fb6c2919ad9e7e736c837186861b362ba80cdfa (diff) | |
| download | uhd-2de96cd57c3f19bfa778ccad280ad19170af0967.tar.gz uhd-2de96cd57c3f19bfa778ccad280ad19170af0967.tar.bz2 uhd-2de96cd57c3f19bfa778ccad280ad19170af0967.zip | |
OctoClock: bugfixes/improvements
* Fixed Ethernet initialization problem
* Improved external reference detection
* Added gratuitous ARP, sent upon power-up
* Tweaked host-side timing for initialization and firmware burning
* Fixed logic for dealing with firmware incompatibility
* Misc efficiency/reliability improvements to firmware's network code
Diffstat (limited to 'firmware/octoclock/include/octoclock.h')
| -rw-r--r-- | firmware/octoclock/include/octoclock.h | 21 |
1 files changed, 16 insertions, 5 deletions
diff --git a/firmware/octoclock/include/octoclock.h b/firmware/octoclock/include/octoclock.h index 3c6254eba..849ab7f96 100644 --- a/firmware/octoclock/include/octoclock.h +++ b/firmware/octoclock/include/octoclock.h @@ -27,14 +27,25 @@ #define F_CPU 12500000UL /* - * Working with the AVR timer + * Timer 0 (8-bit) + * * Set prescaler to 8 + * * Enable overflow interrupt + * * Set timer to 0 */ -// Prescaler: 1024, Timer: 0 -#define TIMER_INIT() TCCR1B = (1 << CS12) | (1 << CS10); \ +#define TIMER0_INIT() TCCR0 = (1 << CS01); \ + TIMSK |= (1 << TOIE0); \ + TCNT0 = 0; +/* + * Timer 1 (16-bit) + * * Set prescaler to 1024 + * * Enable overflow interrupt + * * Set timer to 0 + */ +#define TIMER1_INIT() TCCR1B = (1 << CS12) | (1 << CS10); \ + TIMSK |= (1<<TOIE1); \ TCNT1 = 0; -#define TENTH_SECOND 13 -#define FIVE_SECONDS 61035 +#define TIMER1_ONE_SECOND ((uint32_t)(12207)) // Locations of OctoClock information in EEPROM #define OCTOCLOCK_EEPROM_MAC_ADDR 0 |