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authorNick Foster <nick@nerdnetworks.org>2010-07-29 10:12:45 -0700
committerNick Foster <nick@nerdnetworks.org>2010-07-29 10:12:45 -0700
commitf39c4538a3ca25c79f6b793ee0b6448051dcd751 (patch)
treed1bb5ccad239d8618a66e5c6a0eb14079c211429 /firmware/microblaze/usrp2
parentf9cec099f9909bbdf7b9f1c20db9c81173a9b98d (diff)
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Clock bugs, LED order.
Figured out cold-start problem with Matt's help -- the DCM wasn't being reset. This also explains why USRP2 didn't like it when clocks_mimo_config was omitted -- it was sneakily resetting the DCM while enabling/disabling ref outputs. Also re-did USRP2P LED order and genericized the LED settings so LED_D is LED_D for both USRP2 and USRP2P.
Diffstat (limited to 'firmware/microblaze/usrp2')
-rw-r--r--firmware/microblaze/usrp2/memory_map.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/firmware/microblaze/usrp2/memory_map.h b/firmware/microblaze/usrp2/memory_map.h
index 4c9ead615..41a2820bc 100644
--- a/firmware/microblaze/usrp2/memory_map.h
+++ b/firmware/microblaze/usrp2/memory_map.h
@@ -375,6 +375,10 @@ typedef struct {
volatile uint32_t led_src; // HW or SW control for LEDs
} output_regs_t;
+#define CLK_RESET (1<<4)
+#define CLK_ENABLE (1<<3) | (1<<2)
+#define CLK_SEL (1<<1) | (1<<0)
+
#define SERDES_ENABLE 8
#define SERDES_PRBSEN 4
#define SERDES_LOOPEN 2