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authorJosh Blum <josh@joshknows.com>2010-05-27 23:09:09 +0000
committerJosh Blum <josh@joshknows.com>2010-05-27 23:09:09 +0000
commite940d0225944a210584c386d270d09b132b5514b (patch)
tree59188c0b162c29c02ed09a59b32ab84010ecf269 /firmware/microblaze/lib/u2_init.c
parentf113ae17863729f05b6ada815b9817cd16001211 (diff)
parent4eff47a4b66eff61feffe6498b9ecebef94dc6b9 (diff)
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Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
Conflicts: host/utils/CMakeLists.txt
Diffstat (limited to 'firmware/microblaze/lib/u2_init.c')
-rw-r--r--firmware/microblaze/lib/u2_init.c21
1 files changed, 0 insertions, 21 deletions
diff --git a/firmware/microblaze/lib/u2_init.c b/firmware/microblaze/lib/u2_init.c
index 399d834cb..6809101c0 100644
--- a/firmware/microblaze/lib/u2_init.c
+++ b/firmware/microblaze/lib/u2_init.c
@@ -46,15 +46,6 @@ get_hw_rev(void)
bool
u2_init(void)
{
- // Set GPIOs to inputs, disable GPIO streaming
- hal_gpio_set_ddr(GPIO_TX_BANK, 0x0000, 0xffff);
- hal_gpio_set_ddr(GPIO_RX_BANK, 0x0000, 0xffff);
-
- hal_gpio_write(GPIO_TX_BANK, 0x0000, 0xffff); // init s/w output value to zero
- hal_gpio_write(GPIO_RX_BANK, 0x0000, 0xffff);
-
- dsp_rx_regs->gpio_stream_enable = 0; // I, Q LSBs come from DSP
-
hal_io_init();
// init spi, so that we can switch over to the high-speed clock
@@ -67,18 +58,6 @@ u2_init(void)
// set up the default clocks
clocks_init();
- // clocks_enable_test_clk(true,1);
-
- // Enable ADCs
- output_regs->adc_ctrl = ADC_CTRL_ON;
-
- // Initial values for tx and rx mux registers
- dsp_tx_regs->tx_mux = 0x10;
- dsp_rx_regs->rx_mux = 0x44444444;
-
- // Set up serdes
- output_regs->serdes_ctrl = (SERDES_ENABLE | SERDES_RXEN);
-
pic_init(); // progammable interrupt controller
bp_init(); // buffer pool