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authorJosh Blum <josh@joshknows.com>2010-05-27 23:09:09 +0000
committerJosh Blum <josh@joshknows.com>2010-05-27 23:09:09 +0000
commite940d0225944a210584c386d270d09b132b5514b (patch)
tree59188c0b162c29c02ed09a59b32ab84010ecf269 /firmware/microblaze/lib/clocks.h
parentf113ae17863729f05b6ada815b9817cd16001211 (diff)
parent4eff47a4b66eff61feffe6498b9ecebef94dc6b9 (diff)
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Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
Conflicts: host/utils/CMakeLists.txt
Diffstat (limited to 'firmware/microblaze/lib/clocks.h')
-rw-r--r--firmware/microblaze/lib/clocks.h10
1 files changed, 5 insertions, 5 deletions
diff --git a/firmware/microblaze/lib/clocks.h b/firmware/microblaze/lib/clocks.h
index 141fc61e0..43d5a05c2 100644
--- a/firmware/microblaze/lib/clocks.h
+++ b/firmware/microblaze/lib/clocks.h
@@ -53,7 +53,7 @@ bool clocks_lock_detect();
/*!
* \brief Enable or disable test clock (extra clock signal)
*/
-void clocks_enable_test_clk(bool enable, int divisor);
+//void clocks_enable_test_clk(bool enable, int divisor);
/*!
* \brief Enable or disable fpga clock. Disabling would wedge and require a power cycle.
@@ -73,23 +73,23 @@ void clocks_enable_eth_phyclk(bool enable, int divisor);
/*!
* \brief Enable or disable clock to DAC
*/
-void clocks_enable_dac_clk(bool enable, int divisor);
+//void clocks_enable_dac_clk(bool enable, int divisor);
/*!
* \brief Enable or disable clock to ADC
*/
-void clocks_enable_adc_clk(bool enable, int divisor);
+//void clocks_enable_adc_clk(bool enable, int divisor);
/*!
* \brief Enable or disable clock to Rx daughterboard
*/
-void clocks_enable_rx_dboard(bool enable, int divisor);
+//void clocks_enable_rx_dboard(bool enable, int divisor);
/*!
* \brief Enable or disable clock to Tx daughterboard
*/
-void clocks_enable_tx_dboard(bool enable, int divisor);
+//void clocks_enable_tx_dboard(bool enable, int divisor);
#endif /* INCLUDED_CLOCKS_H */