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authorJosh Blum <josh@joshknows.com>2010-08-04 16:33:49 -0700
committerJosh Blum <josh@joshknows.com>2010-08-04 16:33:49 -0700
commit8e1d51d628afb18dc9a36f268dda1e9f48a1c2ad (patch)
tree9aea9b125848fa7fc3ea45c96bff27dde2c1e8fb /firmware/microblaze/lib/clocks.h
parent702d5af8ca0bab8ef295c817017df5952f6aea51 (diff)
parent70abdef8f6c6d24a99caf8d3668f32094b159903 (diff)
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Merge branch 'master' into codec_gains
Conflicts: host/lib/CMakeLists.txt host/lib/utils/gain_handler.cpp
Diffstat (limited to 'firmware/microblaze/lib/clocks.h')
-rw-r--r--firmware/microblaze/lib/clocks.h8
1 files changed, 4 insertions, 4 deletions
diff --git a/firmware/microblaze/lib/clocks.h b/firmware/microblaze/lib/clocks.h
index 43d5a05c2..28d1d542f 100644
--- a/firmware/microblaze/lib/clocks.h
+++ b/firmware/microblaze/lib/clocks.h
@@ -26,7 +26,7 @@
*/
#include <stdbool.h>
-#include <usrp2_clock_bits.h>
+#include "clock_bits.h"
/*!
@@ -43,7 +43,7 @@ void clocks_init(void);
* Configure our master clock source, and whether or not we drive a
* clock onto the mimo connector. See MC_flags in usrp2_mimo_config.h.
*/
-void clocks_mimo_config(int flags);
+//void clocks_mimo_config(int flags);
/*!
* \brief Lock Detect -- Return True if our PLL is locked
@@ -63,12 +63,12 @@ void clocks_enable_fpga_clk(bool enable, int divisor);
/*!
* \brief Enable or disable clock output sent to MIMO connector
*/
-void clocks_enable_clkexp_out(bool enable, int divisor);
+//void clocks_enable_clkexp_out(bool enable, int divisor);
/*!
* \brief Enable or disable ethernet phyclk, should always be disabled
*/
-void clocks_enable_eth_phyclk(bool enable, int divisor);
+//void clocks_enable_eth_phyclk(bool enable, int divisor);
/*!
* \brief Enable or disable clock to DAC