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authorJosh Blum <josh@joshknows.com>2010-05-10 16:37:12 -0700
committerJosh Blum <josh@joshknows.com>2010-05-10 16:37:12 -0700
commit7c7b0d0a0dc8dd0cb4f0229fbc55978d6f2e253c (patch)
treea5b27c2808a544c04c2963a1891896277c735e4a /firmware/microblaze/lib/clocks.h
parentbf7ef6aeb502839797894cac4d7518029a0d04c4 (diff)
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Added a place for serdes control on the host.
Fix bug in codec control. Comment out some clock control in fw code.
Diffstat (limited to 'firmware/microblaze/lib/clocks.h')
-rw-r--r--firmware/microblaze/lib/clocks.h10
1 files changed, 5 insertions, 5 deletions
diff --git a/firmware/microblaze/lib/clocks.h b/firmware/microblaze/lib/clocks.h
index 141fc61e0..43d5a05c2 100644
--- a/firmware/microblaze/lib/clocks.h
+++ b/firmware/microblaze/lib/clocks.h
@@ -53,7 +53,7 @@ bool clocks_lock_detect();
/*!
* \brief Enable or disable test clock (extra clock signal)
*/
-void clocks_enable_test_clk(bool enable, int divisor);
+//void clocks_enable_test_clk(bool enable, int divisor);
/*!
* \brief Enable or disable fpga clock. Disabling would wedge and require a power cycle.
@@ -73,23 +73,23 @@ void clocks_enable_eth_phyclk(bool enable, int divisor);
/*!
* \brief Enable or disable clock to DAC
*/
-void clocks_enable_dac_clk(bool enable, int divisor);
+//void clocks_enable_dac_clk(bool enable, int divisor);
/*!
* \brief Enable or disable clock to ADC
*/
-void clocks_enable_adc_clk(bool enable, int divisor);
+//void clocks_enable_adc_clk(bool enable, int divisor);
/*!
* \brief Enable or disable clock to Rx daughterboard
*/
-void clocks_enable_rx_dboard(bool enable, int divisor);
+//void clocks_enable_rx_dboard(bool enable, int divisor);
/*!
* \brief Enable or disable clock to Tx daughterboard
*/
-void clocks_enable_tx_dboard(bool enable, int divisor);
+//void clocks_enable_tx_dboard(bool enable, int divisor);
#endif /* INCLUDED_CLOCKS_H */