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authorJosh Blum <josh@joshknows.com>2010-07-30 12:43:41 -0700
committerJosh Blum <josh@joshknows.com>2010-07-30 12:43:41 -0700
commit4240d5a2a1b705fe8ed5c3a1d1deef24be00d444 (patch)
tree6c292d10784049bd5f4e92e69de00f227b279cb1 /firmware/microblaze/lib/clocks.h
parent5dca9e6315c5f827d97351316e5bdd3a786dc4f1 (diff)
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usrp2: reorganized firmware directory
Diffstat (limited to 'firmware/microblaze/lib/clocks.h')
-rw-r--r--firmware/microblaze/lib/clocks.h8
1 files changed, 4 insertions, 4 deletions
diff --git a/firmware/microblaze/lib/clocks.h b/firmware/microblaze/lib/clocks.h
index 43d5a05c2..28d1d542f 100644
--- a/firmware/microblaze/lib/clocks.h
+++ b/firmware/microblaze/lib/clocks.h
@@ -26,7 +26,7 @@
*/
#include <stdbool.h>
-#include <usrp2_clock_bits.h>
+#include "clock_bits.h"
/*!
@@ -43,7 +43,7 @@ void clocks_init(void);
* Configure our master clock source, and whether or not we drive a
* clock onto the mimo connector. See MC_flags in usrp2_mimo_config.h.
*/
-void clocks_mimo_config(int flags);
+//void clocks_mimo_config(int flags);
/*!
* \brief Lock Detect -- Return True if our PLL is locked
@@ -63,12 +63,12 @@ void clocks_enable_fpga_clk(bool enable, int divisor);
/*!
* \brief Enable or disable clock output sent to MIMO connector
*/
-void clocks_enable_clkexp_out(bool enable, int divisor);
+//void clocks_enable_clkexp_out(bool enable, int divisor);
/*!
* \brief Enable or disable ethernet phyclk, should always be disabled
*/
-void clocks_enable_eth_phyclk(bool enable, int divisor);
+//void clocks_enable_eth_phyclk(bool enable, int divisor);
/*!
* \brief Enable or disable clock to DAC