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author | Martin Braun <martin.braun@ettus.com> | 2021-12-22 16:59:59 +0100 |
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committer | Wade Fife <wade.fife@ettus.com> | 2022-01-10 08:46:56 -0600 |
commit | c891f2d8738bc1b73bb92d88623f4760f9e2bd1e (patch) | |
tree | 8814370244604991590d694c89cdf9096498d67a /firmware/fx3 | |
parent | a9e313676dfbd5703b4763a7c9dc03e62746335b (diff) | |
download | uhd-c891f2d8738bc1b73bb92d88623f4760f9e2bd1e.tar.gz uhd-c891f2d8738bc1b73bb92d88623f4760f9e2bd1e.tar.bz2 uhd-c891f2d8738bc1b73bb92d88623f4760f9e2bd1e.zip |
fpga: e320: Connect CTRL_IN pins to FPGA
These pins control hardware-controlled fast-lock for tuning or
cycle-accurate gain control. This commit does nothing to these pins
other than expose them into the design and assign them to zero. This
does not change the current behaviour (the motherboard has pull-downs on
these pins, so they're low by default).
Diffstat (limited to 'firmware/fx3')
0 files changed, 0 insertions, 0 deletions