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authorAshish Chaudhari <ashish@ettus.com>2014-08-12 11:19:22 -0700
committerAshish Chaudhari <ashish@ettus.com>2014-08-12 11:19:22 -0700
commit145f1d7cf7aa94f67c7ba349e29daff9a7d85d54 (patch)
tree64a7a89acd187519bcb285c677b492aa1fc7c55e /firmware/fx3/README.md
parent96d1d586735dd47ce9af0d309c3f1c5abf008497 (diff)
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b200: Removed all AD9361 related firmware
- FX3 does not respond to AD9361 firmware transaction VREQs - FX3 does not respond to AD9361 SPI transaction VREQs - Deleted all AD9361 firmware files - Bumped FW compat to 6
Diffstat (limited to 'firmware/fx3/README.md')
-rw-r--r--firmware/fx3/README.md7
1 files changed, 2 insertions, 5 deletions
diff --git a/firmware/fx3/README.md b/firmware/fx3/README.md
index e2e8a13d4..7e94c247c 100644
--- a/firmware/fx3/README.md
+++ b/firmware/fx3/README.md
@@ -9,10 +9,8 @@ show you how to build our firmware source
**A brief "Theory of Operations":**
The host sends commands to the FX3, our USB3 PHY, which has an on-board ARM
-which runs the FX3 firmware code (hex file). That code translates commands into
-SPI commands to/from the AD9361. The SPI lines run through the FPGA (bin or bit
-file), where they are level-translated, and then head to the AD9361. Note that
-the FPGA takes no action on these SPI lines. They are passive pass-throughs.
+which runs the FX3 firmware code (hex file). That code is responsible for
+managing the transport from the host to the FPGA by configuring IO and DMA.
## Setting up the Cypress SDK
@@ -46,7 +44,6 @@ uhd.git/
|
--fx3/
|
- --ad9361/ # From UHD
--b200/ # From UHD
--common/ # From Cypress SDK
--gpif2_designer/ # From UHD