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| author | Nick Foster <nick@ettus.com> | 2012-03-16 11:26:34 -0700 |
|---|---|---|
| committer | Nick Foster <nick@ettus.com> | 2012-03-16 11:27:39 -0700 |
| commit | 63991f7922a4e20888f001b802a8d8c88a8a16ee (patch) | |
| tree | 0026d0cb7a615a66c6dc90826d58015efe0a22ed /firmware/fx2 | |
| parent | f91e247da23c09626cf215a7cede145b09376575 (diff) | |
| download | uhd-63991f7922a4e20888f001b802a8d8c88a8a16ee.tar.gz uhd-63991f7922a4e20888f001b802a8d8c88a8a16ee.tar.bz2 uhd-63991f7922a4e20888f001b802a8d8c88a8a16ee.zip | |
B100: enable_gpif(0) disables FIFO output clock on FX2. this prevents the "stuffing zeroes" problem and improves transport reliability.
Diffstat (limited to 'firmware/fx2')
| -rw-r--r-- | firmware/fx2/b100/usrp_main.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/firmware/fx2/b100/usrp_main.c b/firmware/fx2/b100/usrp_main.c index 7c4dd479d..74427b7d2 100644 --- a/firmware/fx2/b100/usrp_main.c +++ b/firmware/fx2/b100/usrp_main.c @@ -87,9 +87,9 @@ static void clear_fifo(int ep) { void enable_xfers(int enable) { if(enable) { - IFCONFIG |= bmIFSLAVE; + IFCONFIG = bmIFCLKSRC | bm3048MHZ | bmIFCLKOE | bmIFSLAVE; } else { - IFCONFIG &= ~bmIFSLAVE; + IFCONFIG = bmIFCLKSRC | bm3048MHZ | bmIFSLAVE; } set_led_0(enable); } |