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| author | Nick Foster <nick@ettus.com> | 2012-02-06 13:01:15 -0800 |
|---|---|---|
| committer | Nick Foster <nick@ettus.com> | 2012-02-06 13:01:15 -0800 |
| commit | 5c56ca574ffdf7ad469ab3a3f54def944a978bee (patch) | |
| tree | 5f84fd071c325a32a7c9292f5b995d7f8d2aa756 /firmware/fx2 | |
| parent | c6e63c9d2af2c0b2e168aa6fdd63fe7b214927de (diff) | |
| download | uhd-5c56ca574ffdf7ad469ab3a3f54def944a978bee.tar.gz uhd-5c56ca574ffdf7ad469ab3a3f54def944a978bee.tar.bz2 uhd-5c56ca574ffdf7ad469ab3a3f54def944a978bee.zip | |
B100: use FPGA external reset on init
Diffstat (limited to 'firmware/fx2')
| -rw-r--r-- | firmware/fx2/b100/usrp_main.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/firmware/fx2/b100/usrp_main.c b/firmware/fx2/b100/usrp_main.c index 436bdeb36..d9e09ca34 100644 --- a/firmware/fx2/b100/usrp_main.c +++ b/firmware/fx2/b100/usrp_main.c @@ -65,6 +65,11 @@ xdata at USRP_HASH_SLOT_1_ADDR unsigned char hash1[USRP_HASH_SIZE]; //void clear_fpga_data_fifo(void); +//use the B100 fpga_config_cclk/ext_reset line to reset the FPGA +void fpga_reset(int level) { + bitALTERA_DCLK = level; +} + static void get_ep0_data (void) { @@ -169,7 +174,7 @@ app_vendor_cmd (void) break; case VRQ_FPGA_SET_RESET: - //fpga_set_reset (wValueL); + fpga_reset(wValueL); break; case VRQ_I2C_WRITE: |