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| author | Marcus Müller <marcus.mueller@ettus.com> | 2017-01-16 15:54:57 +0100 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2017-06-29 15:53:15 -0700 |
| commit | d9bcf00f69313b6dd42346d6af340a1a9874ba9f (patch) | |
| tree | 62185d7ea2c20952d60cf8f6a558866ecf1d54bf /firmware/fx2/usrp1/usrp_regs.h | |
| parent | c77bd0c46a598d5e69b179d76a3df6091e982129 (diff) | |
| download | uhd-d9bcf00f69313b6dd42346d6af340a1a9874ba9f.tar.gz uhd-d9bcf00f69313b6dd42346d6af340a1a9874ba9f.tar.bz2 uhd-d9bcf00f69313b6dd42346d6af340a1a9874ba9f.zip | |
made FX2 EEPROMS and firmware build with modern SDCC 3.6
Diffstat (limited to 'firmware/fx2/usrp1/usrp_regs.h')
| -rw-r--r-- | firmware/fx2/usrp1/usrp_regs.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/firmware/fx2/usrp1/usrp_regs.h b/firmware/fx2/usrp1/usrp_regs.h index a4f1d9896..8e5ade295 100644 --- a/firmware/fx2/usrp1/usrp_regs.h +++ b/firmware/fx2/usrp1/usrp_regs.h @@ -47,9 +47,9 @@ #define bmPA_TX_UNDERRUN bmBIT7 // misc pin to FPGA (underflow) -sbit at 0x80+0 bitS_CLK; // 0x80 is the bit address of PORT A -sbit at 0x80+1 bitS_OUT; // out from FX2 point of view -sbit at 0x80+2 bitS_IN; // in from FX2 point of view +__sbit __at (0x80+0) bitS_CLK; // 0x80 is the bit address of PORT A +__sbit __at (0x80+1) bitS_OUT; // out from FX2 point of view +__sbit __at (0x80+2) bitS_IN; // in from FX2 point of view /* all outputs except S_DATA_FROM_PERIPH, FX2_2, FX2_3 */ @@ -85,8 +85,8 @@ sbit at 0x80+2 bitS_IN; // in from FX2 point of view #define bmPC_LED0 bmBIT6 // active low #define bmPC_LED1 bmBIT7 // active low -sbit at 0xA0+1 bitALTERA_DATA0; // 0xA0 is the bit address of PORT C -sbit at 0xA0+3 bitALTERA_DCLK; +__sbit __at (0xA0+1) bitALTERA_DATA0; // 0xA0 is the bit address of PORT C +__sbit __at (0xA0+3) bitALTERA_DCLK; #define bmALTERA_BITS (bmALTERA_DATA0 \ |