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| author | Josh Blum <josh@joshknows.com> | 2010-11-05 13:53:39 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-11-05 13:53:39 -0700 |
| commit | 3ac3457184bc3b251ce7398eee56c931983abe65 (patch) | |
| tree | 7cfa1ba616788ad083236272a323c3a6e2964da3 /firmware/fx2/include | |
| parent | 144ebf29327981db8422049b451852744619678d (diff) | |
| parent | c473cc56fafcb47d6ba1f16e8c9fb89ff6c57bca (diff) | |
| download | uhd-3ac3457184bc3b251ce7398eee56c931983abe65.tar.gz uhd-3ac3457184bc3b251ce7398eee56c931983abe65.tar.bz2 uhd-3ac3457184bc3b251ce7398eee56c931983abe65.zip | |
Merge branch 'good_stuff' into mb_eeprom
Conflicts:
firmware/fx2/include
Diffstat (limited to 'firmware/fx2/include')
24 files changed, 0 insertions, 2691 deletions
diff --git a/firmware/fx2/include/.gitignore b/firmware/fx2/include/.gitignore deleted file mode 100644 index 75bb241c8..000000000 --- a/firmware/fx2/include/.gitignore +++ /dev/null @@ -1,25 +0,0 @@ -/Makefile -/Makefile.in -/aclocal.m4 -/configure -/config.h.in -/stamp-h.in -/libtool -/config.log -/config.h -/config.cache -/config.status -/missing -/stamp-h -/stamp-h1 -/.la -/.lo -/.deps -/.libs -/*.la -/*.lo -/autom4te.cache -/*.cache -/missing -/make.log -/usrp.pc diff --git a/firmware/fx2/include/Makefile.am b/firmware/fx2/include/Makefile.am deleted file mode 100644 index e17726c07..000000000 --- a/firmware/fx2/include/Makefile.am +++ /dev/null @@ -1,61 +0,0 @@ -# -# Copyright 2003 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -usrpincludedir = $(includedir)/usrp - -usrpinclude_HEADERS = \ - usrp_i2c_addr.h \ - usrp_spi_defs.h \ - fpga_regs_common.h \ - fpga_regs_standard.h - - -noinst_HEADERS = \ - delay.h \ - fpga_regs_common.v \ - fpga_regs_standard.v \ - fpga_regs0.h \ - fx2regs.h \ - fx2utils.h \ - i2c.h \ - isr.h \ - syncdelay.h \ - timer.h \ - usb_common.h \ - usb_descriptors.h \ - usb_requests.h \ - usrp_commands.h \ - usrp_config.h \ - usrp_ids.h \ - usrp_interfaces.h - - -CODE_GENERATOR = \ - generate_regs.py - -EXTRA_DIST = \ - $(CODE_GENERATOR) - -fpga_regs_common.v: fpga_regs_common.h generate_regs.py - PYTHONPATH=$(top_srcdir)/usrp/firmware/include $(PYTHON) $(srcdir)/generate_regs.py $(srcdir)/fpga_regs_common.h $@ - -fpga_regs_standard.v: fpga_regs_standard.h generate_regs.py - PYTHONPATH=$(top_srcdir)/usrp/firmware/include $(PYTHON) $(srcdir)/generate_regs.py $(srcdir)/fpga_regs_standard.h $@ diff --git a/firmware/fx2/include/delay.h b/firmware/fx2/include/delay.h deleted file mode 100644 index f5df779e1..000000000 --- a/firmware/fx2/include/delay.h +++ /dev/null @@ -1,38 +0,0 @@ -/* -*- c++ -*- */ -/* - * Copyright 2003 Free Software Foundation, Inc. - * - * This file is part of GNU Radio - * - * GNU Radio is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3, or (at your option) - * any later version. - * - * GNU Radio is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with GNU Radio; see the file COPYING. If not, write to - * the Free Software Foundation, Inc., 51 Franklin Street, - * Boston, MA 02110-1301, USA. - */ - -#ifndef _DELAY_H_ -#define _DELAY_H_ - -/* - * delay for approximately usecs microseconds - * Note limit of 255 usecs. - */ -void udelay (unsigned char usecs); - -/* - * delay for approximately msecs milliseconds - */ -void mdelay (unsigned short msecs); - - -#endif /* _DELAY_H_ */ diff --git a/firmware/fx2/include/fpga_regs0.h b/firmware/fx2/include/fpga_regs0.h deleted file mode 100644 index 883798301..000000000 --- a/firmware/fx2/include/fpga_regs0.h +++ /dev/null @@ -1,42 +0,0 @@ -/* -*- c++ -*- */ -/* - * Copyright 2003 Free Software Foundation, Inc. - * - * This file is part of GNU Radio - * - * GNU Radio is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3, or (at your option) - * any later version. - * - * GNU Radio is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with GNU Radio; see the file COPYING. If not, write to - * the Free Software Foundation, Inc., 51 Franklin Street, - * Boston, MA 02110-1301, USA. - */ - -#ifndef _FPGA_REGS0_H_ -#define _FPGA_REGS0_H_ - -#define FR_RX_FREQ_0 0 -#define FR_RX_FREQ_1 1 -#define FR_RX_FREQ_2 2 -#define FR_RX_FREQ_3 3 -#define FR_TX_FREQ_0 4 -#define FR_TX_FREQ_1 5 -#define FR_TX_FREQ_2 6 -#define FR_TX_FREQ_3 7 -#define FR_COMBO 8 - - -#define FR_ADC_CLK_DIV 128 // pseudo regs mapped to FR_COMBO by f/w -#define FR_EXT_CLK_DIV 129 -#define FR_INTERP 130 -#define FR_DECIM 131 - -#endif diff --git a/firmware/fx2/include/fpga_regs_common.h b/firmware/fx2/include/fpga_regs_common.h deleted file mode 100644 index b4a496af7..000000000 --- a/firmware/fx2/include/fpga_regs_common.h +++ /dev/null @@ -1,150 +0,0 @@ -/* -*- c++ -*- */ -/* - * Copyright 2003,2004 Free Software Foundation, Inc. - * - * This file is part of GNU Radio - * - * GNU Radio is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3, or (at your option) - * any later version. - * - * GNU Radio is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with GNU Radio; see the file COPYING. If not, write to - * the Free Software Foundation, Inc., 51 Franklin Street, - * Boston, MA 02110-1301, USA. - */ -#ifndef INCLUDED_FPGA_REGS_COMMON_H -#define INCLUDED_FPGA_REGS_COMMON_H - -// This file defines registers common to all FPGA configurations. -// Registers 0 to 31 are reserved for use in this file. - - -// The FPGA needs to know the rate that samples are coming from and -// going to the A/D's and D/A's. div = 128e6 / sample_rate - -#define FR_TX_SAMPLE_RATE_DIV 0 -#define FR_RX_SAMPLE_RATE_DIV 1 - -// 2 and 3 are defined in the ATR section - -#define FR_MASTER_CTRL 4 // master enable and reset controls -# define bmFR_MC_ENABLE_TX (1 << 0) -# define bmFR_MC_ENABLE_RX (1 << 1) -# define bmFR_MC_RESET_TX (1 << 2) -# define bmFR_MC_RESET_RX (1 << 3) - -// i/o direction registers for pins that go to daughterboards. -// Setting the bit makes it an output from the FPGA to the d'board. -// top 16 is mask, low 16 is value - -#define FR_OE_0 5 // slot 0 -#define FR_OE_1 6 -#define FR_OE_2 7 -#define FR_OE_3 8 - -// i/o registers for pins that go to daughterboards. -// top 16 is a mask, low 16 is value - -#define FR_IO_0 9 // slot 0 -#define FR_IO_1 10 -#define FR_IO_2 11 -#define FR_IO_3 12 - -#define FR_MODE 13 -# define bmFR_MODE_NORMAL 0 -# define bmFR_MODE_LOOPBACK (1 << 0) // enable digital loopback -# define bmFR_MODE_RX_COUNTING (1 << 1) // Rx is counting -# define bmFR_MODE_RX_COUNTING_32BIT (1 << 2) // Rx is counting with a 32 bit counter - // low and high 16 bits are multiplexed across channel I and Q - - -// If the corresponding bit is set, internal FPGA debug circuitry -// controls the i/o pins for the associated bank of daughterboard -// i/o pins. Typically used for debugging FPGA designs. - -#define FR_DEBUG_EN 14 -# define bmFR_DEBUG_EN_TX_A (1 << 0) // debug controls TX_A i/o -# define bmFR_DEBUG_EN_RX_A (1 << 1) // debug controls RX_A i/o -# define bmFR_DEBUG_EN_TX_B (1 << 2) // debug controls TX_B i/o -# define bmFR_DEBUG_EN_RX_B (1 << 3) // debug controls RX_B i/o - - -// If the corresponding bit is set, enable the automatic DC -// offset correction control loop. -// -// The 4 low bits are significant: -// -// ADC0 = (1 << 0) -// ADC1 = (1 << 1) -// ADC2 = (1 << 2) -// ADC3 = (1 << 3) -// -// This control loop works if the attached daugherboard blocks DC. -// Currently all daughterboards do block DC. This includes: -// basic rx, dbs_rx, tv_rx, flex_xxx_rx. - -#define FR_DC_OFFSET_CL_EN 15 // DC Offset Control Loop Enable - - -// offset corrections for ADC's and DAC's (2's complement) - -#define FR_ADC_OFFSET_0 16 -#define FR_ADC_OFFSET_1 17 -#define FR_ADC_OFFSET_2 18 -#define FR_ADC_OFFSET_3 19 - - -// ------------------------------------------------------------------------ -// Automatic Transmit/Receive switching -// -// If automatic transmit/receive (ATR) switching is enabled in the -// FR_ATR_CTL register, the presence or absence of data in the FPGA -// transmit fifo selects between two sets of values for each of the 4 -// banks of daughterboard i/o pins. -// -// Each daughterboard slot has 3 16-bit registers associated with it: -// FR_ATR_MASK_*, FR_ATR_TXVAL_* and FR_ATR_RXVAL_* -// -// FR_ATR_MASK_{0,1,2,3}: -// -// These registers determine which of the daugherboard i/o pins are -// affected by ATR switching. If a bit in the mask is set, the -// corresponding i/o bit is controlled by ATR, else it's output -// value comes from the normal i/o pin output register: -// FR_IO_{0,1,2,3}. -// -// FR_ATR_TXVAL_{0,1,2,3}: -// FR_ATR_RXVAL_{0,1,2,3}: -// -// If the Tx fifo contains data, then the bits from TXVAL that are -// selected by MASK are output. Otherwise, the bits from RXVAL that -// are selected by MASK are output. - -#define FR_ATR_MASK_0 20 // slot 0 -#define FR_ATR_TXVAL_0 21 -#define FR_ATR_RXVAL_0 22 - -#define FR_ATR_MASK_1 23 // slot 1 -#define FR_ATR_TXVAL_1 24 -#define FR_ATR_RXVAL_1 25 - -#define FR_ATR_MASK_2 26 // slot 2 -#define FR_ATR_TXVAL_2 27 -#define FR_ATR_RXVAL_2 28 - -#define FR_ATR_MASK_3 29 // slot 3 -#define FR_ATR_TXVAL_3 30 -#define FR_ATR_RXVAL_3 31 - -// Clock ticks to delay rising and falling edge of T/R signal -#define FR_ATR_TX_DELAY 2 -#define FR_ATR_RX_DELAY 3 - -#endif /* INCLUDED_FPGA_REGS_COMMON_H */ diff --git a/firmware/fx2/include/fpga_regs_common.v b/firmware/fx2/include/fpga_regs_common.v deleted file mode 100644 index 8035d8565..000000000 --- a/firmware/fx2/include/fpga_regs_common.v +++ /dev/null @@ -1,117 +0,0 @@ -// -// This file is machine generated from ./fpga_regs_common.h -// Do not edit by hand; your edits will be overwritten. -// - -// This file defines registers common to all FPGA configurations. -// Registers 0 to 31 are reserved for use in this file. - - -// The FPGA needs to know the rate that samples are coming from and -// going to the A/D's and D/A's. div = 128e6 / sample_rate - -`define FR_TX_SAMPLE_RATE_DIV 7'd0 -`define FR_RX_SAMPLE_RATE_DIV 7'd1 - -// 2 and 3 are defined in the ATR section - -`define FR_MASTER_CTRL 7'd4 // master enable and reset controls - -// i/o direction registers for pins that go to daughterboards. -// Setting the bit makes it an output from the FPGA to the d'board. -// top 16 is mask, low 16 is value - -`define FR_OE_0 7'd5 // slot 0 -`define FR_OE_1 7'd6 -`define FR_OE_2 7'd7 -`define FR_OE_3 7'd8 - -// i/o registers for pins that go to daughterboards. -// top 16 is a mask, low 16 is value - -`define FR_IO_0 7'd9 // slot 0 -`define FR_IO_1 7'd10 -`define FR_IO_2 7'd11 -`define FR_IO_3 7'd12 - -`define FR_MODE 7'd13 - - -// If the corresponding bit is set, internal FPGA debug circuitry -// controls the i/o pins for the associated bank of daughterboard -// i/o pins. Typically used for debugging FPGA designs. - -`define FR_DEBUG_EN 7'd14 - - -// If the corresponding bit is set, enable the automatic DC -// offset correction control loop. -// -// The 4 low bits are significant: -// -// ADC0 = (1 << 0) -// ADC1 = (1 << 1) -// ADC2 = (1 << 2) -// ADC3 = (1 << 3) -// -// This control loop works if the attached daugherboard blocks DC. -// Currently all daughterboards do block DC. This includes: -// basic rx, dbs_rx, tv_rx, flex_xxx_rx. - -`define FR_DC_OFFSET_CL_EN 7'd15 // DC Offset Control Loop Enable - - -// offset corrections for ADC's and DAC's (2's complement) - -`define FR_ADC_OFFSET_0 7'd16 -`define FR_ADC_OFFSET_1 7'd17 -`define FR_ADC_OFFSET_2 7'd18 -`define FR_ADC_OFFSET_3 7'd19 - - -// ------------------------------------------------------------------------ -// Automatic Transmit/Receive switching -// -// If automatic transmit/receive (ATR) switching is enabled in the -// FR_ATR_CTL register, the presence or absence of data in the FPGA -// transmit fifo selects between two sets of values for each of the 4 -// banks of daughterboard i/o pins. -// -// Each daughterboard slot has 3 16-bit registers associated with it: -// FR_ATR_MASK_*, FR_ATR_TXVAL_* and FR_ATR_RXVAL_* -// -// FR_ATR_MASK_{0,1,2,3}: -// -// These registers determine which of the daugherboard i/o pins are -// affected by ATR switching. If a bit in the mask is set, the -// corresponding i/o bit is controlled by ATR, else it's output -// value comes from the normal i/o pin output register: -// FR_IO_{0,1,2,3}. -// -// FR_ATR_TXVAL_{0,1,2,3}: -// FR_ATR_RXVAL_{0,1,2,3}: -// -// If the Tx fifo contains data, then the bits from TXVAL that are -// selected by MASK are output. Otherwise, the bits from RXVAL that -// are selected by MASK are output. - -`define FR_ATR_MASK_0 7'd20 // slot 0 -`define FR_ATR_TXVAL_0 7'd21 -`define FR_ATR_RXVAL_0 7'd22 - -`define FR_ATR_MASK_1 7'd23 // slot 1 -`define FR_ATR_TXVAL_1 7'd24 -`define FR_ATR_RXVAL_1 7'd25 - -`define FR_ATR_MASK_2 7'd26 // slot 2 -`define FR_ATR_TXVAL_2 7'd27 -`define FR_ATR_RXVAL_2 7'd28 - -`define FR_ATR_MASK_3 7'd29 // slot 3 -`define FR_ATR_TXVAL_3 7'd30 -`define FR_ATR_RXVAL_3 7'd31 - -// Clock ticks to delay rising and falling edge of T/R signal -`define FR_ATR_TX_DELAY 7'd2 -`define FR_ATR_RX_DELAY 7'd3 - diff --git a/firmware/fx2/include/fpga_regs_standard.h b/firmware/fx2/include/fpga_regs_standard.h deleted file mode 100644 index 7485e2bab..000000000 --- a/firmware/fx2/include/fpga_regs_standard.h +++ /dev/null @@ -1,300 +0,0 @@ -/* -*- c++ -*- */ -/* - * Copyright 2003,2004,2006 Free Software Foundation, Inc. - * - * This file is part of GNU Radio - * - * GNU Radio is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3, or (at your option) - * any later version. - * - * GNU Radio is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with GNU Radio; see the file COPYING. If not, write to - * the Free Software Foundation, Inc., 51 Franklin Street, - * Boston, MA 02110-1301, USA. - */ -#ifndef INCLUDED_FPGA_REGS_STANDARD_H -#define INCLUDED_FPGA_REGS_STANDARD_H - -// Register numbers 0 to 31 are reserved for use in fpga_regs_common.h. -// Registers 64 to 79 are available for custom FPGA builds. - - -// DDC / DUC - -#define FR_INTERP_RATE 32 // [1,1024] -#define FR_DECIM_RATE 33 // [1,256] - -// DDC center freq - -#define FR_RX_FREQ_0 34 -#define FR_RX_FREQ_1 35 -#define FR_RX_FREQ_2 36 -#define FR_RX_FREQ_3 37 - -// See below for DDC Starting Phase - -// ------------------------------------------------------------------------ -// configure FPGA Rx mux -// -// 3 2 1 -// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 -// +-----------------------+-------+-------+-------+-------+-+-----+ -// | must be zero | Q3| I3| Q2| I2| Q1| I1| Q0| I0|Z| NCH | -// +-----------------------+-------+-------+-------+-------+-+-----+ -// -// There are a maximum of 4 digital downconverters in the the FPGA. -// Each DDC has two 16-bit inputs, I and Q, and two 16-bit outputs, I & Q. -// -// DDC I inputs are specified by the two bit fields I3, I2, I1 & I0 -// -// 0 = DDC input is from ADC 0 -// 1 = DDC input is from ADC 1 -// 2 = DDC input is from ADC 2 -// 3 = DDC input is from ADC 3 -// -// If Z == 1, all DDC Q inputs are set to zero -// If Z == 0, DDC Q inputs are specified by the two bit fields Q3, Q2, Q1 & Q0 -// -// NCH specifies the number of complex channels that are sent across -// the USB. The legal values are 1, 2 or 4, corresponding to 2, 4 or -// 8 16-bit values. - -#define FR_RX_MUX 38 - -// ------------------------------------------------------------------------ -// configure FPGA Tx Mux. -// -// 3 2 1 -// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 -// +-----------------------+-------+-------+-------+-------+-+-----+ -// | | DAC3 | DAC2 | DAC1 | DAC0 |0| NCH | -// +-----------------------------------------------+-------+-+-----+ -// -// NCH specifies the number of complex channels that are sent across -// the USB. The legal values are 1 or 2, corresponding to 2 or 4 -// 16-bit values. -// -// There are two interpolators with complex inputs and outputs. -// There are four DACs. (We use the DUC in each AD9862.) -// -// Each 4-bit DACx field specifies the source for the DAC and -// whether or not that DAC is enabled. Each subfield is coded -// like this: -// -// 3 2 1 0 -// +-+-----+ -// |E| N | -// +-+-----+ -// -// Where E is set if the DAC is enabled, and N specifies which -// interpolator output is connected to this DAC. -// -// N which interp output -// --- ------------------- -// 0 chan 0 I -// 1 chan 0 Q -// 2 chan 1 I -// 3 chan 1 Q - -#define FR_TX_MUX 39 - -// ------------------------------------------------------------------------ -// REFCLK control -// -// Control whether a reference clock is sent to the daughterboards, -// and what frequency. The refclk is sent on d'board i/o pin 0. -// -// 3 2 1 -// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 -// +-----------------------------------------------+-+------------+ -// | Reserved (Must be zero) |E| DIVISOR | -// +-----------------------------------------------+-+------------+ - -// -// Bit 7 -- 1 turns on refclk, 0 allows IO use -// Bits 6:0 Divider value - -#define FR_TX_A_REFCLK 40 -#define FR_RX_A_REFCLK 41 -#define FR_TX_B_REFCLK 42 -#define FR_RX_B_REFCLK 43 - -# define bmFR_REFCLK_EN 0x80 -# define bmFR_REFCLK_DIVISOR_MASK 0x7f - -// ------------------------------------------------------------------------ -// DDC Starting Phase - -#define FR_RX_PHASE_0 44 -#define FR_RX_PHASE_1 45 -#define FR_RX_PHASE_2 46 -#define FR_RX_PHASE_3 47 - -// ------------------------------------------------------------------------ -// Tx data format control register -// -// 3 2 1 -// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 -// +-------------------------------------------------------+-------+ -// | Reserved (Must be zero) | FMT | -// +-------------------------------------------------------+-------+ -// -// FMT values: - -#define FR_TX_FORMAT 48 -# define bmFR_TX_FORMAT_16_IQ 0 // 16-bit I, 16-bit Q - -// ------------------------------------------------------------------------ -// Rx data format control register -// -// 3 2 1 -// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 -// +-----------------------------------------+-+-+---------+-------+ -// | Reserved (Must be zero) |B|Q| WIDTH | SHIFT | -// +-----------------------------------------+-+-+---------+-------+ -// -// FMT values: - -#define FR_RX_FORMAT 49 - -# define bmFR_RX_FORMAT_SHIFT_MASK (0x0f << 0) // arithmetic right shift [0, 15] -# define bmFR_RX_FORMAT_SHIFT_SHIFT 0 -# define bmFR_RX_FORMAT_WIDTH_MASK (0x1f << 4) // data width in bits [1, 16] (not all valid) -# define bmFR_RX_FORMAT_WIDTH_SHIFT 4 -# define bmFR_RX_FORMAT_WANT_Q (0x1 << 9) // deliver both I & Q, else just I -# define bmFR_RX_FORMAT_BYPASS_HB (0x1 << 10) // bypass half-band filter - -// The valid combinations currently are: -// -// B Q WIDTH SHIFT -// 0 1 16 0 -// 0 1 8 8 - - -// Possible future values of WIDTH = {4, 2, 1} -// 12 takes a bit more work, since we need to know packet alignment. - -// ------------------------------------------------------------------------ -// FIXME register numbers 50 to 63 are available - -// ------------------------------------------------------------------------ -// Registers 64 to 95 are reserved for user custom FPGA builds. -// The standard USRP software will not touch these. - -#define FR_USER_0 64 -#define FR_USER_1 65 -#define FR_USER_2 66 -#define FR_USER_3 67 -#define FR_USER_4 68 -#define FR_USER_5 69 -#define FR_USER_6 70 -#define FR_USER_7 71 -#define FR_USER_8 72 -#define FR_USER_9 73 -#define FR_USER_10 74 -#define FR_USER_11 75 -#define FR_USER_12 76 -#define FR_USER_13 77 -#define FR_USER_14 78 -#define FR_USER_15 79 -#define FR_USER_16 80 -#define FR_USER_17 81 -#define FR_USER_18 82 -#define FR_USER_19 83 -#define FR_USER_20 84 -#define FR_USER_21 85 -#define FR_USER_22 86 -#define FR_USER_23 87 -#define FR_USER_24 88 -#define FR_USER_25 89 -#define FR_USER_26 90 -#define FR_USER_27 91 -#define FR_USER_28 92 -#define FR_USER_29 93 -#define FR_USER_30 94 -#define FR_USER_31 95 - -//Registers needed for multi usrp master/slave configuration -// -//Rx Master/slave control register (FR_RX_MASTER_SLAVE = FR_USER_0) -// -#define FR_RX_MASTER_SLAVE 64 -#define bitnoFR_RX_SYNC 0 -#define bitnoFR_RX_SYNC_MASTER 1 -#define bitnoFR_RX_SYNC_SLAVE 2 -# define bmFR_RX_SYNC (1 <<bitnoFR_RX_SYNC) //1 If this is a master "sync now" and send sync to slave. - // If this is a slave "sync now" (testing purpose only) - // Sync is allmost the same as reset (clear all counters and buffers) - // except that the io outputs and settings don't get reset (otherwise it couldn't send the sync to the slave) - //0 Normal operation - -# define bmFR_RX_SYNC_MASTER (1 <<bitnoFR_RX_SYNC_MASTER) //1 This is a rx sync master, output sync_rx on rx_a_io[15] - //0 This is not a rx sync master -# define bmFR_RX_SYNC_SLAVE (1 <<bitnoFR_RX_SYNC_SLAVE) //1 This is a rx sync slave, follow sync_rx on rx_a_io[bitnoFR_RX_SYNC_INPUT_IOPIN] - //0 This is not an rx sync slave. - -//Caution The master settings will output values on the io lines. -//They inheritely enable these lines as output. If you have a daughtercard which uses these lines also as output then you will burn your usrp and daughtercard. -//If you set the slave bits then your usrp won't do anything if you don't connect a master. -// Rx Master/slave control register -// -// The way this is supposed to be used is connecting a (short) 16pin flatcable from an rx daughterboard in RXA master io_rx[8..15] to slave io_rx[8..15] on RXA of slave usrp -// This can be done with basic_rx boards or dbsrx boards -//dbsrx: connect master-J25 to slave-J25 -//basic rx: connect J25 to slave-J25 -//CAUTION: pay attention to the lineup of your connector. -//The red line (pin1) should be at the same side of the daughterboards on master and slave. -//If you turnaround the cable on one end you will burn your usrp. - -//You cannot use a 16pin flatcable if you are using FLEX400 or FLEX2400 daughterboards, since these use a lot of the io pins. -//You can still link them but you must use only a 2pin or 1pin cable -//You can also use a 2-wire link. put a 2pin header on io[15],gnd of the master RXA daughterboard and connect it to io15,gnd of the slave RXA db. -//You can use a cable like the ones found with the leds on the mainbord of a PC. -//Make sure you don't twist the cable, otherwise you connect the sync output to ground. -//To be save you could also just use a single wire from master io[15] to slave io[15], but this is not optimal for signal integrity. - - -// Since rx_io[0] can normally be used as a refclk and is not exported on all daughterboards this line -// still has the refclk function if you use the master/slave setup (it is not touched by the master/slave settings). -// The master/slave circuitry will only use io pin 15 and does not touch any of the other io pins. -#define bitnoFR_RX_SYNC_INPUT_IOPIN 15 -#define bmFR_RX_SYNC_INPUT_IOPIN (1<<bitnoFR_RX_SYNC_INPUT_IOPIN) -//TODO the output pin is still hardcoded in the verilog code, make it listen to the following define -#define bitnoFR_RX_SYNC_OUTPUT_IOPIN 15 -#define bmFR_RX_SYNC_OUTPUT_IOPIN (1<<bitnoFR_RX_SYNC_OUTPUT_IOPIN) -// ======================================================================= -// READBACK Registers -// ======================================================================= - -#define FR_RB_IO_RX_A_IO_TX_A 1 // read back a-side i/o pins -#define FR_RB_IO_RX_B_IO_TX_B 2 // read back b-side i/o pins - -// ------------------------------------------------------------------------ -// FPGA Capability register -// -// 3 2 1 -// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 -// +-----------------------------------------------+-+-----+-+-----+ -// | Reserved (Must be zero) |T|NDUC |R|NDDC | -// +-----------------------------------------------+-+-----+-+-----+ -// -// Bottom 4-bits are Rx capabilities -// Next 4-bits are Tx capabilities - -#define FR_RB_CAPS 3 -# define bmFR_RB_CAPS_NDDC_MASK (0x7 << 0) // # of digital down converters 0,1,2,4 -# define bmFR_RB_CAPS_NDDC_SHIFT 0 -# define bmFR_RB_CAPS_RX_HAS_HALFBAND (0x1 << 3) -# define bmFR_RB_CAPS_NDUC_MASK (0x7 << 4) // # of digital up converters 0,1,2 -# define bmFR_RB_CAPS_NDUC_SHIFT 4 -# define bmFR_RB_CAPS_TX_HAS_HALFBAND (0x1 << 7) - - -#endif /* INCLUDED_FPGA_REGS_STANDARD_H */ diff --git a/firmware/fx2/include/fpga_regs_standard.v b/firmware/fx2/include/fpga_regs_standard.v deleted file mode 100644 index d09aa6116..000000000 --- a/firmware/fx2/include/fpga_regs_standard.v +++ /dev/null @@ -1,256 +0,0 @@ -// -// This file is machine generated from ./fpga_regs_standard.h -// Do not edit by hand; your edits will be overwritten. -// - -// Register numbers 0 to 31 are reserved for use in fpga_regs_common.h. -// Registers 64 to 79 are available for custom FPGA builds. - - -// DDC / DUC - -`define FR_INTERP_RATE 7'd32 // [1,1024] -`define FR_DECIM_RATE 7'd33 // [1,256] - -// DDC center freq - -`define FR_RX_FREQ_0 7'd34 -`define FR_RX_FREQ_1 7'd35 -`define FR_RX_FREQ_2 7'd36 -`define FR_RX_FREQ_3 7'd37 - -// See below for DDC Starting Phase - -// ------------------------------------------------------------------------ -// configure FPGA Rx mux -// -// 3 2 1 -// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 -// +-----------------------+-------+-------+-------+-------+-+-----+ -// | must be zero | Q3| I3| Q2| I2| Q1| I1| Q0| I0|Z| NCH | -// +-----------------------+-------+-------+-------+-------+-+-----+ -// -// There are a maximum of 4 digital downconverters in the the FPGA. -// Each DDC has two 16-bit inputs, I and Q, and two 16-bit outputs, I & Q. -// -// DDC I inputs are specified by the two bit fields I3, I2, I1 & I0 -// -// 0 = DDC input is from ADC 0 -// 1 = DDC input is from ADC 1 -// 2 = DDC input is from ADC 2 -// 3 = DDC input is from ADC 3 -// -// If Z == 1, all DDC Q inputs are set to zero -// If Z == 0, DDC Q inputs are specified by the two bit fields Q3, Q2, Q1 & Q0 -// -// NCH specifies the number of complex channels that are sent across -// the USB. The legal values are 1, 2 or 4, corresponding to 2, 4 or -// 8 16-bit values. - -`define FR_RX_MUX 7'd38 - -// ------------------------------------------------------------------------ -// configure FPGA Tx Mux. -// -// 3 2 1 -// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 -// +-----------------------+-------+-------+-------+-------+-+-----+ -// | | DAC3 | DAC2 | DAC1 | DAC0 |0| NCH | -// +-----------------------------------------------+-------+-+-----+ -// -// NCH specifies the number of complex channels that are sent across -// the USB. The legal values are 1 or 2, corresponding to 2 or 4 -// 16-bit values. -// -// There are two interpolators with complex inputs and outputs. -// There are four DACs. (We use the DUC in each AD9862.) -// -// Each 4-bit DACx field specifies the source for the DAC and -// whether or not that DAC is enabled. Each subfield is coded -// like this: -// -// 3 2 1 0 -// +-+-----+ -// |E| N | -// +-+-----+ -// -// Where E is set if the DAC is enabled, and N specifies which -// interpolator output is connected to this DAC. -// -// N which interp output -// --- ------------------- -// 0 chan 0 I -// 1 chan 0 Q -// 2 chan 1 I -// 3 chan 1 Q - -`define FR_TX_MUX 7'd39 - -// ------------------------------------------------------------------------ -// REFCLK control -// -// Control whether a reference clock is sent to the daughterboards, -// and what frequency. The refclk is sent on d'board i/o pin 0. -// -// 3 2 1 -// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 -// +-----------------------------------------------+-+------------+ -// | Reserved (Must be zero) |E| DIVISOR | -// +-----------------------------------------------+-+------------+ - -// -// Bit 7 -- 1 turns on refclk, 0 allows IO use -// Bits 6:0 Divider value - -`define FR_TX_A_REFCLK 7'd40 -`define FR_RX_A_REFCLK 7'd41 -`define FR_TX_B_REFCLK 7'd42 -`define FR_RX_B_REFCLK 7'd43 - - -// ------------------------------------------------------------------------ -// DDC Starting Phase - -`define FR_RX_PHASE_0 7'd44 -`define FR_RX_PHASE_1 7'd45 -`define FR_RX_PHASE_2 7'd46 -`define FR_RX_PHASE_3 7'd47 - -// ------------------------------------------------------------------------ -// Tx data format control register -// -// 3 2 1 -// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 -// +-------------------------------------------------------+-------+ -// | Reserved (Must be zero) | FMT | -// +-------------------------------------------------------+-------+ -// -// FMT values: - -`define FR_TX_FORMAT 7'd48 - -// ------------------------------------------------------------------------ -// Rx data format control register -// -// 3 2 1 -// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 -// +-----------------------------------------+-+-+---------+-------+ -// | Reserved (Must be zero) |B|Q| WIDTH | SHIFT | -// +-----------------------------------------+-+-+---------+-------+ -// -// FMT values: - -`define FR_RX_FORMAT 7'd49 - - -// The valid combinations currently are: -// -// B Q WIDTH SHIFT -// 0 1 16 0 -// 0 1 8 8 - - -// Possible future values of WIDTH = {4, 2, 1} -// 12 takes a bit more work, since we need to know packet alignment. - -// ------------------------------------------------------------------------ -// FIXME register numbers 50 to 63 are available - -// ------------------------------------------------------------------------ -// Registers 64 to 95 are reserved for user custom FPGA builds. -// The standard USRP software will not touch these. - -`define FR_USER_0 7'd64 -`define FR_USER_1 7'd65 -`define FR_USER_2 7'd66 -`define FR_USER_3 7'd67 -`define FR_USER_4 7'd68 -`define FR_USER_5 7'd69 -`define FR_USER_6 7'd70 -`define FR_USER_7 7'd71 -`define FR_USER_8 7'd72 -`define FR_USER_9 7'd73 -`define FR_USER_10 7'd74 -`define FR_USER_11 7'd75 -`define FR_USER_12 7'd76 -`define FR_USER_13 7'd77 -`define FR_USER_14 7'd78 -`define FR_USER_15 7'd79 -`define FR_USER_16 7'd80 -`define FR_USER_17 7'd81 -`define FR_USER_18 7'd82 -`define FR_USER_19 7'd83 -`define FR_USER_20 7'd84 -`define FR_USER_21 7'd85 -`define FR_USER_22 7'd86 -`define FR_USER_23 7'd87 -`define FR_USER_24 7'd88 -`define FR_USER_25 7'd89 -`define FR_USER_26 7'd90 -`define FR_USER_27 7'd91 -`define FR_USER_28 7'd92 -`define FR_USER_29 7'd93 -`define FR_USER_30 7'd94 -`define FR_USER_31 7'd95 - -//Registers needed for multi usrp master/slave configuration -// -//Rx Master/slave control register (FR_RX_MASTER_SLAVE = FR_USER_0) -// -`define FR_RX_MASTER_SLAVE 7'd64 -`define bitnoFR_RX_SYNC 0 -`define bitnoFR_RX_SYNC_MASTER 1 -`define bitnoFR_RX_SYNC_SLAVE 2 - - -//Caution The master settings will output values on the io lines. -//They inheritely enable these lines as output. If you have a daughtercard which uses these lines also as output then you will burn your usrp and daughtercard. -//If you set the slave bits then your usrp won't do anything if you don't connect a master. -// Rx Master/slave control register -// -// The way this is supposed to be used is connecting a (short) 16pin flatcable from an rx daughterboard in RXA master io_rx[8..15] to slave io_rx[8..15] on RXA of slave usrp -// This can be done with basic_rx boards or dbsrx boards -//dbsrx: connect master-J25 to slave-J25 -//basic rx: connect J25 to slave-J25 -//CAUTION: pay attention to the lineup of your connector. -//The red line (pin1) should be at the same side of the daughterboards on master and slave. -//If you turnaround the cable on one end you will burn your usrp. - -//You cannot use a 16pin flatcable if you are using FLEX400 or FLEX2400 daughterboards, since these use a lot of the io pins. -//You can still link them but you must use only a 2pin or 1pin cable -//You can also use a 2-wire link. put a 2pin header on io[15],gnd of the master RXA daughterboard and connect it to io15,gnd of the slave RXA db. -//You can use a cable like the ones found with the leds on the mainbord of a PC. -//Make sure you don't twist the cable, otherwise you connect the sync output to ground. -//To be save you could also just use a single wire from master io[15] to slave io[15], but this is not optimal for signal integrity. - - -// Since rx_io[0] can normally be used as a refclk and is not exported on all daughterboards this line -// still has the refclk function if you use the master/slave setup (it is not touched by the master/slave settings). -// The master/slave circuitry will only use io pin 15 and does not touch any of the other io pins. -`define bitnoFR_RX_SYNC_INPUT_IOPIN 15 -`define bmFR_RX_SYNC_INPUT_IOPIN (1<<bitnoFR_RX_SYNC_INPUT_IOPIN) -//TODO the output pin is still hardcoded in the verilog code, make it listen to the following define -`define bitnoFR_RX_SYNC_OUTPUT_IOPIN 15 -`define bmFR_RX_SYNC_OUTPUT_IOPIN (1<<bitnoFR_RX_SYNC_OUTPUT_IOPIN) -// ======================================================================= -// READBACK Registers -// ======================================================================= - -`define FR_RB_IO_RX_A_IO_TX_A 7'd1 // read back a-side i/o pins -`define FR_RB_IO_RX_B_IO_TX_B 7'd2 // read back b-side i/o pins - -// ------------------------------------------------------------------------ -// FPGA Capability register -// -// 3 2 1 -// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 -// +-----------------------------------------------+-+-----+-+-----+ -// | Reserved (Must be zero) |T|NDUC |R|NDDC | -// +-----------------------------------------------+-+-----+-+-----+ -// -// Bottom 4-bits are Rx capabilities -// Next 4-bits are Tx capabilities - -`define FR_RB_CAPS 7'd3 - - diff --git a/firmware/fx2/include/fx2regs.h b/firmware/fx2/include/fx2regs.h deleted file mode 100644 index 2f210f567..000000000 --- a/firmware/fx2/include/fx2regs.h +++ /dev/null @@ -1,716 +0,0 @@ -/* -*- c++ -*- */ -/* - * Copyright 2003 Free Software Foundation, Inc. - * - * This file is part of GNU Radio - * - * GNU Radio is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3, or (at your option) - * any later version. - * - * GNU Radio is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with GNU Radio; see the file COPYING. If not, write to - * the Free Software Foundation, Inc., 51 Franklin Street, - * Boston, MA 02110-1301, USA. - */ - -/* -//----------------------------------------------------------------------------- -// File: FX2regs.h -// Contents: EZ-USB FX2 register declarations and bit mask definitions. -// -// $Archive: /USB/Target/Inc/fx2regs.h $ -// $Date$ -// $Revision$ -// -// -// Copyright (c) 2000 Cypress Semiconductor, All rights reserved -//----------------------------------------------------------------------------- -*/ - - -#ifndef FX2REGS_H /* Header Sentry */ -#define FX2REGS_H - -#define ALLOCATE_EXTERN // required for "right thing to happen" with fx2regs.h - -/* -//----------------------------------------------------------------------------- -// FX2 Related Register Assignments -//----------------------------------------------------------------------------- - -// The Ez-USB FX2 registers are defined here. We use FX2regs.h for register -// address allocation by using "#define ALLOCATE_EXTERN". -// When using "#define ALLOCATE_EXTERN", you get (for instance): -// xdata volatile BYTE OUT7BUF[64] _at_ 0x7B40; -// Such lines are created from FX2.h by using the preprocessor. -// Incidently, these lines will not generate any space in the resulting hex -// file; they just bind the symbols to the addresses for compilation. -// You just need to put "#define ALLOCATE_EXTERN" in your main program file; -// i.e. fw.c or a stand-alone C source file. -// Without "#define ALLOCATE_EXTERN", you just get the external reference: -// extern xdata volatile BYTE OUT7BUF[64] ;// 0x7B40; -// This uses the concatenation operator "##" to insert a comment "//" -// to cut off the end of the line, "_at_ 0x7B40;", which is not wanted. -*/ - - -#ifdef ALLOCATE_EXTERN -#define EXTERN -#define _AT_(a) at a -#else -#define EXTERN extern -#define _AT_ ;/ ## / -#endif - -typedef unsigned char BYTE; -typedef unsigned short WORD; - -EXTERN xdata _AT_(0xE400) volatile BYTE GPIF_WAVE_DATA[128]; -EXTERN xdata _AT_(0xE480) volatile BYTE RES_WAVEDATA_END ; - -// General Configuration - -EXTERN xdata _AT_(0xE600) volatile BYTE CPUCS ; // Control & Status -EXTERN xdata _AT_(0xE601) volatile BYTE IFCONFIG ; // Interface Configuration -EXTERN xdata _AT_(0xE602) volatile BYTE PINFLAGSAB ; // FIFO FLAGA and FLAGB Assignments -EXTERN xdata _AT_(0xE603) volatile BYTE PINFLAGSCD ; // FIFO FLAGC and FLAGD Assignments -EXTERN xdata _AT_(0xE604) volatile BYTE FIFORESET ; // Restore FIFOS to default state -EXTERN xdata _AT_(0xE605) volatile BYTE BREAKPT ; // Breakpoint -EXTERN xdata _AT_(0xE606) volatile BYTE BPADDRH ; // Breakpoint Address H -EXTERN xdata _AT_(0xE607) volatile BYTE BPADDRL ; // Breakpoint Address L -EXTERN xdata _AT_(0xE608) volatile BYTE UART230 ; // 230 Kbaud clock for T0,T1,T2 -EXTERN xdata _AT_(0xE609) volatile BYTE FIFOPINPOLAR ; // FIFO polarities -EXTERN xdata _AT_(0xE60A) volatile BYTE REVID ; // Chip Revision -EXTERN xdata _AT_(0xE60B) volatile BYTE REVCTL ; // Chip Revision Control - -// Endpoint Configuration - -EXTERN xdata _AT_(0xE610) volatile BYTE EP1OUTCFG ; // Endpoint 1-OUT Configuration -EXTERN xdata _AT_(0xE611) volatile BYTE EP1INCFG ; // Endpoint 1-IN Configuration -EXTERN xdata _AT_(0xE612) volatile BYTE EP2CFG ; // Endpoint 2 Configuration -EXTERN xdata _AT_(0xE613) volatile BYTE EP4CFG ; // Endpoint 4 Configuration -EXTERN xdata _AT_(0xE614) volatile BYTE EP6CFG ; // Endpoint 6 Configuration -EXTERN xdata _AT_(0xE615) volatile BYTE EP8CFG ; // Endpoint 8 Configuration -EXTERN xdata _AT_(0xE618) volatile BYTE EP2FIFOCFG ; // Endpoint 2 FIFO configuration -EXTERN xdata _AT_(0xE619) volatile BYTE EP4FIFOCFG ; // Endpoint 4 FIFO configuration -EXTERN xdata _AT_(0xE61A) volatile BYTE EP6FIFOCFG ; // Endpoint 6 FIFO configuration -EXTERN xdata _AT_(0xE61B) volatile BYTE EP8FIFOCFG ; // Endpoint 8 FIFO configuration -EXTERN xdata _AT_(0xE620) volatile BYTE EP2AUTOINLENH ; // Endpoint 2 Packet Length H (IN only) -EXTERN xdata _AT_(0xE621) volatile BYTE EP2AUTOINLENL ; // Endpoint 2 Packet Length L (IN only) -EXTERN xdata _AT_(0xE622) volatile BYTE EP4AUTOINLENH ; // Endpoint 4 Packet Length H (IN only) -EXTERN xdata _AT_(0xE623) volatile BYTE EP4AUTOINLENL ; // Endpoint 4 Packet Length L (IN only) -EXTERN xdata _AT_(0xE624) volatile BYTE EP6AUTOINLENH ; // Endpoint 6 Packet Length H (IN only) -EXTERN xdata _AT_(0xE625) volatile BYTE EP6AUTOINLENL ; // Endpoint 6 Packet Length L (IN only) -EXTERN xdata _AT_(0xE626) volatile BYTE EP8AUTOINLENH ; // Endpoint 8 Packet Length H (IN only) -EXTERN xdata _AT_(0xE627) volatile BYTE EP8AUTOINLENL ; // Endpoint 8 Packet Length L (IN only) -EXTERN xdata _AT_(0xE630) volatile BYTE EP2FIFOPFH ; // EP2 Programmable Flag trigger H -EXTERN xdata _AT_(0xE631) volatile BYTE EP2FIFOPFL ; // EP2 Programmable Flag trigger L -EXTERN xdata _AT_(0xE632) volatile BYTE EP4FIFOPFH ; // EP4 Programmable Flag trigger H -EXTERN xdata _AT_(0xE633) volatile BYTE EP4FIFOPFL ; // EP4 Programmable Flag trigger L -EXTERN xdata _AT_(0xE634) volatile BYTE EP6FIFOPFH ; // EP6 Programmable Flag trigger H -EXTERN xdata _AT_(0xE635) volatile BYTE EP6FIFOPFL ; // EP6 Programmable Flag trigger L -EXTERN xdata _AT_(0xE636) volatile BYTE EP8FIFOPFH ; // EP8 Programmable Flag trigger H -EXTERN xdata _AT_(0xE637) volatile BYTE EP8FIFOPFL ; // EP8 Programmable Flag trigger L -EXTERN xdata _AT_(0xE640) volatile BYTE EP2ISOINPKTS ; // EP2 (if ISO) IN Packets per frame (1-3) -EXTERN xdata _AT_(0xE641) volatile BYTE EP4ISOINPKTS ; // EP4 (if ISO) IN Packets per frame (1-3) -EXTERN xdata _AT_(0xE642) volatile BYTE EP6ISOINPKTS ; // EP6 (if ISO) IN Packets per frame (1-3) -EXTERN xdata _AT_(0xE643) volatile BYTE EP8ISOINPKTS ; // EP8 (if ISO) IN Packets per frame (1-3) -EXTERN xdata _AT_(0xE648) volatile BYTE INPKTEND ; // Force IN Packet End -EXTERN xdata _AT_(0xE649) volatile BYTE OUTPKTEND ; // Force OUT Packet End - -// Interrupts - -EXTERN xdata _AT_(0xE650) volatile BYTE EP2FIFOIE ; // Endpoint 2 Flag Interrupt Enable -EXTERN xdata _AT_(0xE651) volatile BYTE EP2FIFOIRQ ; // Endpoint 2 Flag Interrupt Request -EXTERN xdata _AT_(0xE652) volatile BYTE EP4FIFOIE ; // Endpoint 4 Flag Interrupt Enable -EXTERN xdata _AT_(0xE653) volatile BYTE EP4FIFOIRQ ; // Endpoint 4 Flag Interrupt Request -EXTERN xdata _AT_(0xE654) volatile BYTE EP6FIFOIE ; // Endpoint 6 Flag Interrupt Enable -EXTERN xdata _AT_(0xE655) volatile BYTE EP6FIFOIRQ ; // Endpoint 6 Flag Interrupt Request -EXTERN xdata _AT_(0xE656) volatile BYTE EP8FIFOIE ; // Endpoint 8 Flag Interrupt Enable -EXTERN xdata _AT_(0xE657) volatile BYTE EP8FIFOIRQ ; // Endpoint 8 Flag Interrupt Request -EXTERN xdata _AT_(0xE658) volatile BYTE IBNIE ; // IN-BULK-NAK Interrupt Enable -EXTERN xdata _AT_(0xE659) volatile BYTE IBNIRQ ; // IN-BULK-NAK interrupt Request -EXTERN xdata _AT_(0xE65A) volatile BYTE NAKIE ; // Endpoint Ping NAK interrupt Enable -EXTERN xdata _AT_(0xE65B) volatile BYTE NAKIRQ ; // Endpoint Ping NAK interrupt Request -EXTERN xdata _AT_(0xE65C) volatile BYTE USBIE ; // USB Int Enables -EXTERN xdata _AT_(0xE65D) volatile BYTE USBIRQ ; // USB Interrupt Requests -EXTERN xdata _AT_(0xE65E) volatile BYTE EPIE ; // Endpoint Interrupt Enables -EXTERN xdata _AT_(0xE65F) volatile BYTE EPIRQ ; // Endpoint Interrupt Requests -EXTERN xdata _AT_(0xE660) volatile BYTE GPIFIE ; // GPIF Interrupt Enable -EXTERN xdata _AT_(0xE661) volatile BYTE GPIFIRQ ; // GPIF Interrupt Request -EXTERN xdata _AT_(0xE662) volatile BYTE USBERRIE ; // USB Error Interrupt Enables -EXTERN xdata _AT_(0xE663) volatile BYTE USBERRIRQ ; // USB Error Interrupt Requests -EXTERN xdata _AT_(0xE664) volatile BYTE ERRCNTLIM ; // USB Error counter and limit -EXTERN xdata _AT_(0xE665) volatile BYTE CLRERRCNT ; // Clear Error Counter EC[3..0] -EXTERN xdata _AT_(0xE666) volatile BYTE INT2IVEC ; // Interupt 2 (USB) Autovector -EXTERN xdata _AT_(0xE667) volatile BYTE INT4IVEC ; // Interupt 4 (FIFOS & GPIF) Autovector -EXTERN xdata _AT_(0xE668) volatile BYTE INTSETUP ; // Interrupt 2&4 Setup - -// Input/Output - -EXTERN xdata _AT_(0xE670) volatile BYTE PORTACFG ; // I/O PORTA Alternate Configuration -EXTERN xdata _AT_(0xE671) volatile BYTE PORTCCFG ; // I/O PORTC Alternate Configuration -EXTERN xdata _AT_(0xE672) volatile BYTE PORTECFG ; // I/O PORTE Alternate Configuration -EXTERN xdata _AT_(0xE678) volatile BYTE I2CS ; // Control & Status -EXTERN xdata _AT_(0xE679) volatile BYTE I2DAT ; // Data -EXTERN xdata _AT_(0xE67A) volatile BYTE I2CTL ; // I2C Control -EXTERN xdata _AT_(0xE67B) volatile BYTE XAUTODAT1 ; // Autoptr1 MOVX access -EXTERN xdata _AT_(0xE67C) volatile BYTE XAUTODAT2 ; // Autoptr2 MOVX access - -#define EXTAUTODAT1 XAUTODAT1 -#define EXTAUTODAT2 XAUTODAT2 - -// USB Control - -EXTERN xdata _AT_(0xE680) volatile BYTE USBCS ; // USB Control & Status -EXTERN xdata _AT_(0xE681) volatile BYTE SUSPEND ; // Put chip into suspend -EXTERN xdata _AT_(0xE682) volatile BYTE WAKEUPCS ; // Wakeup source and polarity -EXTERN xdata _AT_(0xE683) volatile BYTE TOGCTL ; // Toggle Control -EXTERN xdata _AT_(0xE684) volatile BYTE USBFRAMEH ; // USB Frame count H -EXTERN xdata _AT_(0xE685) volatile BYTE USBFRAMEL ; // USB Frame count L -EXTERN xdata _AT_(0xE686) volatile BYTE MICROFRAME ; // Microframe count, 0-7 -EXTERN xdata _AT_(0xE687) volatile BYTE FNADDR ; // USB Function address - -// Endpoints - -EXTERN xdata _AT_(0xE68A) volatile BYTE EP0BCH ; // Endpoint 0 Byte Count H -EXTERN xdata _AT_(0xE68B) volatile BYTE EP0BCL ; // Endpoint 0 Byte Count L -EXTERN xdata _AT_(0xE68D) volatile BYTE EP1OUTBC ; // Endpoint 1 OUT Byte Count -EXTERN xdata _AT_(0xE68F) volatile BYTE EP1INBC ; // Endpoint 1 IN Byte Count -EXTERN xdata _AT_(0xE690) volatile BYTE EP2BCH ; // Endpoint 2 Byte Count H -EXTERN xdata _AT_(0xE691) volatile BYTE EP2BCL ; // Endpoint 2 Byte Count L -EXTERN xdata _AT_(0xE694) volatile BYTE EP4BCH ; // Endpoint 4 Byte Count H -EXTERN xdata _AT_(0xE695) volatile BYTE EP4BCL ; // Endpoint 4 Byte Count L -EXTERN xdata _AT_(0xE698) volatile BYTE EP6BCH ; // Endpoint 6 Byte Count H -EXTERN xdata _AT_(0xE699) volatile BYTE EP6BCL ; // Endpoint 6 Byte Count L -EXTERN xdata _AT_(0xE69C) volatile BYTE EP8BCH ; // Endpoint 8 Byte Count H -EXTERN xdata _AT_(0xE69D) volatile BYTE EP8BCL ; // Endpoint 8 Byte Count L -EXTERN xdata _AT_(0xE6A0) volatile BYTE EP0CS ; // Endpoint Control and Status -EXTERN xdata _AT_(0xE6A1) volatile BYTE EP1OUTCS ; // Endpoint 1 OUT Control and Status -EXTERN xdata _AT_(0xE6A2) volatile BYTE EP1INCS ; // Endpoint 1 IN Control and Status -EXTERN xdata _AT_(0xE6A3) volatile BYTE EP2CS ; // Endpoint 2 Control and Status -EXTERN xdata _AT_(0xE6A4) volatile BYTE EP4CS ; // Endpoint 4 Control and Status -EXTERN xdata _AT_(0xE6A5) volatile BYTE EP6CS ; // Endpoint 6 Control and Status -EXTERN xdata _AT_(0xE6A6) volatile BYTE EP8CS ; // Endpoint 8 Control and Status -EXTERN xdata _AT_(0xE6A7) volatile BYTE EP2FIFOFLGS ; // Endpoint 2 Flags -EXTERN xdata _AT_(0xE6A8) volatile BYTE EP4FIFOFLGS ; // Endpoint 4 Flags -EXTERN xdata _AT_(0xE6A9) volatile BYTE EP6FIFOFLGS ; // Endpoint 6 Flags -EXTERN xdata _AT_(0xE6AA) volatile BYTE EP8FIFOFLGS ; // Endpoint 8 Flags -EXTERN xdata _AT_(0xE6AB) volatile BYTE EP2FIFOBCH ; // EP2 FIFO total byte count H -EXTERN xdata _AT_(0xE6AC) volatile BYTE EP2FIFOBCL ; // EP2 FIFO total byte count L -EXTERN xdata _AT_(0xE6AD) volatile BYTE EP4FIFOBCH ; // EP4 FIFO total byte count H -EXTERN xdata _AT_(0xE6AE) volatile BYTE EP4FIFOBCL ; // EP4 FIFO total byte count L -EXTERN xdata _AT_(0xE6AF) volatile BYTE EP6FIFOBCH ; // EP6 FIFO total byte count H -EXTERN xdata _AT_(0xE6B0) volatile BYTE EP6FIFOBCL ; // EP6 FIFO total byte count L -EXTERN xdata _AT_(0xE6B1) volatile BYTE EP8FIFOBCH ; // EP8 FIFO total byte count H -EXTERN xdata _AT_(0xE6B2) volatile BYTE EP8FIFOBCL ; // EP8 FIFO total byte count L -EXTERN xdata _AT_(0xE6B3) volatile BYTE SUDPTRH ; // Setup Data Pointer high address byte -EXTERN xdata _AT_(0xE6B4) volatile BYTE SUDPTRL ; // Setup Data Pointer low address byte -EXTERN xdata _AT_(0xE6B5) volatile BYTE SUDPTRCTL ; // Setup Data Pointer Auto Mode -EXTERN xdata _AT_(0xE6B8) volatile BYTE SETUPDAT[8] ; // 8 bytes of SETUP data - -// GPIF - -EXTERN xdata _AT_(0xE6C0) volatile BYTE GPIFWFSELECT ; // Waveform Selector -EXTERN xdata _AT_(0xE6C1) volatile BYTE GPIFIDLECS ; // GPIF Done, GPIF IDLE drive mode -EXTERN xdata _AT_(0xE6C2) volatile BYTE GPIFIDLECTL ; // Inactive Bus, CTL states -EXTERN xdata _AT_(0xE6C3) volatile BYTE GPIFCTLCFG ; // CTL OUT pin drive -EXTERN xdata _AT_(0xE6C4) volatile BYTE GPIFADRH ; // GPIF Address H -EXTERN xdata _AT_(0xE6C5) volatile BYTE GPIFADRL ; // GPIF Address L - -EXTERN xdata _AT_(0xE6CE) volatile BYTE GPIFTCB3 ; // GPIF Transaction Count Byte 3 -EXTERN xdata _AT_(0xE6CF) volatile BYTE GPIFTCB2 ; // GPIF Transaction Count Byte 2 -EXTERN xdata _AT_(0xE6D0) volatile BYTE GPIFTCB1 ; // GPIF Transaction Count Byte 1 -EXTERN xdata _AT_(0xE6D1) volatile BYTE GPIFTCB0 ; // GPIF Transaction Count Byte 0 - -#define EP2GPIFTCH GPIFTCB1 // these are here for backwards compatibility -#define EP2GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD) -#define EP4GPIFTCH GPIFTCB1 // these are here for backwards compatibility -#define EP4GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD) -#define EP6GPIFTCH GPIFTCB1 // these are here for backwards compatibility -#define EP6GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD) -#define EP8GPIFTCH GPIFTCB1 // these are here for backwards compatibility -#define EP8GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD) - -// EXTERN xdata volatile BYTE EP2GPIFTCH _AT_ 0xE6D0; // EP2 GPIF Transaction Count High -// EXTERN xdata volatile BYTE EP2GPIFTCL _AT_ 0xE6D1; // EP2 GPIF Transaction Count Low -EXTERN xdata _AT_(0xE6D2) volatile BYTE EP2GPIFFLGSEL ; // EP2 GPIF Flag select -EXTERN xdata _AT_(0xE6D3) volatile BYTE EP2GPIFPFSTOP ; // Stop GPIF EP2 transaction on prog. flag -EXTERN xdata _AT_(0xE6D4) volatile BYTE EP2GPIFTRIG ; // EP2 FIFO Trigger -// EXTERN xdata volatile BYTE EP4GPIFTCH _AT_ 0xE6D8; // EP4 GPIF Transaction Count High -// EXTERN xdata volatile BYTE EP4GPIFTCL _AT_ 0xE6D9; // EP4 GPIF Transactionr Count Low -EXTERN xdata _AT_(0xE6DA) volatile BYTE EP4GPIFFLGSEL ; // EP4 GPIF Flag select -EXTERN xdata _AT_(0xE6DB) volatile BYTE EP4GPIFPFSTOP ; // Stop GPIF EP4 transaction on prog. flag -EXTERN xdata _AT_(0xE6DC) volatile BYTE EP4GPIFTRIG ; // EP4 FIFO Trigger -// EXTERN xdata volatile BYTE EP6GPIFTCH _AT_ 0xE6E0; // EP6 GPIF Transaction Count High -// EXTERN xdata volatile BYTE EP6GPIFTCL _AT_ 0xE6E1; // EP6 GPIF Transaction Count Low -EXTERN xdata _AT_(0xE6E2) volatile BYTE EP6GPIFFLGSEL ; // EP6 GPIF Flag select -EXTERN xdata _AT_(0xE6E3) volatile BYTE EP6GPIFPFSTOP ; // Stop GPIF EP6 transaction on prog. flag -EXTERN xdata _AT_(0xE6E4) volatile BYTE EP6GPIFTRIG ; // EP6 FIFO Trigger -// EXTERN xdata volatile BYTE EP8GPIFTCH _AT_ 0xE6E8; // EP8 GPIF Transaction Count High -// EXTERN xdata volatile BYTE EP8GPIFTCL _AT_ 0xE6E9; // EP8GPIF Transaction Count Low -EXTERN xdata _AT_(0xE6EA) volatile BYTE EP8GPIFFLGSEL ; // EP8 GPIF Flag select -EXTERN xdata _AT_(0xE6EB) volatile BYTE EP8GPIFPFSTOP ; // Stop GPIF EP8 transaction on prog. flag -EXTERN xdata _AT_(0xE6EC) volatile BYTE EP8GPIFTRIG ; // EP8 FIFO Trigger -EXTERN xdata _AT_(0xE6F0) volatile BYTE XGPIFSGLDATH ; // GPIF Data H (16-bit mode only) -EXTERN xdata _AT_(0xE6F1) volatile BYTE XGPIFSGLDATLX ; // Read/Write GPIF Data L & trigger transac -EXTERN xdata _AT_(0xE6F2) volatile BYTE XGPIFSGLDATLNOX ; // Read GPIF Data L, no transac trigger -EXTERN xdata _AT_(0xE6F3) volatile BYTE GPIFREADYCFG ; // Internal RDY,Sync/Async, RDY5CFG -EXTERN xdata _AT_(0xE6F4) volatile BYTE GPIFREADYSTAT ; // RDY pin states -EXTERN xdata _AT_(0xE6F5) volatile BYTE GPIFABORT ; // Abort GPIF cycles - -// UDMA - -EXTERN xdata _AT_(0xE6C6) volatile BYTE FLOWSTATE ; //Defines GPIF flow state -EXTERN xdata _AT_(0xE6C7) volatile BYTE FLOWLOGIC ; //Defines flow/hold decision criteria -EXTERN xdata _AT_(0xE6C8) volatile BYTE FLOWEQ0CTL ; //CTL states during active flow state -EXTERN xdata _AT_(0xE6C9) volatile BYTE FLOWEQ1CTL ; //CTL states during hold flow state -EXTERN xdata _AT_(0xE6CA) volatile BYTE FLOWHOLDOFF ; -EXTERN xdata _AT_(0xE6CB) volatile BYTE FLOWSTB ; //CTL/RDY Signal to use as master data strobe -EXTERN xdata _AT_(0xE6CC) volatile BYTE FLOWSTBEDGE ; //Defines active master strobe edge -EXTERN xdata _AT_(0xE6CD) volatile BYTE FLOWSTBHPERIOD ; //Half Period of output master strobe -EXTERN xdata _AT_(0xE60C) volatile BYTE GPIFHOLDAMOUNT ; //Data delay shift -EXTERN xdata _AT_(0xE67D) volatile BYTE UDMACRCH ; //CRC Upper byte -EXTERN xdata _AT_(0xE67E) volatile BYTE UDMACRCL ; //CRC Lower byte -EXTERN xdata _AT_(0xE67F) volatile BYTE UDMACRCQUAL ; //UDMA In only, host terminated use only - - -// Debug/Test - -EXTERN xdata _AT_(0xE6F8) volatile BYTE DBUG ; // Debug -EXTERN xdata _AT_(0xE6F9) volatile BYTE TESTCFG ; // Test configuration -EXTERN xdata _AT_(0xE6FA) volatile BYTE USBTEST ; // USB Test Modes -EXTERN xdata _AT_(0xE6FB) volatile BYTE CT1 ; // Chirp Test--Override -EXTERN xdata _AT_(0xE6FC) volatile BYTE CT2 ; // Chirp Test--FSM -EXTERN xdata _AT_(0xE6FD) volatile BYTE CT3 ; // Chirp Test--Control Signals -EXTERN xdata _AT_(0xE6FE) volatile BYTE CT4 ; // Chirp Test--Inputs - -// Endpoint Buffers - -EXTERN xdata _AT_(0xE740) volatile BYTE EP0BUF[64] ; // EP0 IN-OUT buffer -EXTERN xdata _AT_(0xE780) volatile BYTE EP1OUTBUF[64] ; // EP1-OUT buffer -EXTERN xdata _AT_(0xE7C0) volatile BYTE EP1INBUF[64] ; // EP1-IN buffer -EXTERN xdata _AT_(0xF000) volatile BYTE EP2FIFOBUF[1024] ; // 512/1024-byte EP2 buffer (IN or OUT) -EXTERN xdata _AT_(0xF400) volatile BYTE EP4FIFOBUF[1024] ; // 512 byte EP4 buffer (IN or OUT) -EXTERN xdata _AT_(0xF800) volatile BYTE EP6FIFOBUF[1024] ; // 512/1024-byte EP6 buffer (IN or OUT) -EXTERN xdata _AT_(0xFC00) volatile BYTE EP8FIFOBUF[1024] ; // 512 byte EP8 buffer (IN or OUT) - -#undef EXTERN -#undef _AT_ - -/*----------------------------------------------------------------------------- - Special Function Registers (SFRs) - The byte registers and bits defined in the following list are based - on the Synopsis definition of the 8051 Special Function Registers for EZ-USB. - If you modify the register definitions below, please regenerate the file - "ezregs.inc" which includes the same basic information for assembly inclusion. ------------------------------------------------------------------------------*/ - -sfr at 0x80 IOA; -sfr at 0x81 SP; -sfr at 0x82 DPL; -sfr at 0x83 DPH; -sfr at 0x84 DPL1; -sfr at 0x85 DPH1; -sfr at 0x86 DPS; - /* DPS */ - sbit at 0x86+0 SEL; -sfr at 0x87 PCON; /* PCON */ - //sbit IDLE = 0x87+0; - //sbit STOP = 0x87+1; - //sbit GF0 = 0x87+2; - //sbit GF1 = 0x87+3; - //sbit SMOD0 = 0x87+7; -sfr at 0x88 TCON; - /* TCON */ - sbit at 0x88+0 IT0; - sbit at 0x88+1 IE0; - sbit at 0x88+2 IT1; - sbit at 0x88+3 IE1; - sbit at 0x88+4 TR0; - sbit at 0x88+5 TF0; - sbit at 0x88+6 TR1; - sbit at 0x88+7 TF1; -sfr at 0x89 TMOD; - /* TMOD */ - //sbit M00 = 0x89+0; - //sbit M10 = 0x89+1; - //sbit CT0 = 0x89+2; - //sbit GATE0 = 0x89+3; - //sbit M01 = 0x89+4; - //sbit M11 = 0x89+5; - //sbit CT1 = 0x89+6; - //sbit GATE1 = 0x89+7; -sfr at 0x8A TL0; -sfr at 0x8B TL1; -sfr at 0x8C TH0; -sfr at 0x8D TH1; -sfr at 0x8E CKCON; - /* CKCON */ - //sbit MD0 = 0x89+0; - //sbit MD1 = 0x89+1; - //sbit MD2 = 0x89+2; - //sbit T0M = 0x89+3; - //sbit T1M = 0x89+4; - //sbit T2M = 0x89+5; -// sfr at 0x8F SPC_FNC; // Was WRS in Reg320 - /* CKCON */ - //sbit WRS = 0x8F+0; -sfr at 0x90 IOB; -sfr at 0x91 EXIF; // EXIF Bit Values differ from Reg320 - /* EXIF */ - //sbit USBINT = 0x91+4; - //sbit I2CINT = 0x91+5; - //sbit IE4 = 0x91+6; - //sbit IE5 = 0x91+7; -sfr at 0x92 MPAGE; -sfr at 0x98 SCON0; - /* SCON0 */ - sbit at 0x98+0 RI; - sbit at 0x98+1 TI; - sbit at 0x98+2 RB8; - sbit at 0x98+3 TB8; - sbit at 0x98+4 REN; - sbit at 0x98+5 SM2; - sbit at 0x98+6 SM1; - sbit at 0x98+7 SM0; -sfr at 0x99 SBUF0; - -sfr at 0x9A APTR1H; -sfr at 0x9B APTR1L; -sfr at 0x9C AUTODAT1; -sfr at 0x9D AUTOPTRH2; -sfr at 0x9E AUTOPTRL2; -sfr at 0x9F AUTODAT2; -sfr at 0xA0 IOC; -sfr at 0xA1 INT2CLR; -sfr at 0xA2 INT4CLR; - -#define AUTOPTRH1 APTR1H -#define AUTOPTRL1 APTR1L - -sfr at 0xA8 IE; - /* IE */ - sbit at 0xA8+0 EX0; - sbit at 0xA8+1 ET0; - sbit at 0xA8+2 EX1; - sbit at 0xA8+3 ET1; - sbit at 0xA8+4 ES0; - sbit at 0xA8+5 ET2; - sbit at 0xA8+6 ES1; - sbit at 0xA8+7 EA; - -sfr at 0xAA EP2468STAT; - /* EP2468STAT */ - //sbit EP2E = 0xAA+0; - //sbit EP2F = 0xAA+1; - //sbit EP4E = 0xAA+2; - //sbit EP4F = 0xAA+3; - //sbit EP6E = 0xAA+4; - //sbit EP6F = 0xAA+5; - //sbit EP8E = 0xAA+6; - //sbit EP8F = 0xAA+7; - -sfr at 0xAB EP24FIFOFLGS; -sfr at 0xAC EP68FIFOFLGS; -sfr at 0xAF AUTOPTRSETUP; - /* AUTOPTRSETUP */ - // sbit EXTACC = 0xAF+0; - // sbit APTR1FZ = 0xAF+1; - // sbit APTR2FZ = 0xAF+2; - -sfr at 0xB0 IOD; -sfr at 0xB1 IOE; -sfr at 0xB2 OEA; -sfr at 0xB3 OEB; -sfr at 0xB4 OEC; -sfr at 0xB5 OED; -sfr at 0xB6 OEE; - -sfr at 0xB8 IP; - /* IP */ - sbit at 0xB8+0 PX0; - sbit at 0xB8+1 PT0; - sbit at 0xB8+2 PX1; - sbit at 0xB8+3 PT1; - sbit at 0xB8+4 PS0; - sbit at 0xB8+5 PT2; - sbit at 0xB8+6 PS1; - -sfr at 0xBA EP01STAT; -sfr at 0xBB GPIFTRIG; - -sfr at 0xBD GPIFSGLDATH; -sfr at 0xBE GPIFSGLDATLX; -sfr at 0xBF GPIFSGLDATLNOX; - -sfr at 0xC0 SCON1; - /* SCON1 */ - sbit at 0xC0+0 RI1; - sbit at 0xC0+1 TI1; - sbit at 0xC0+2 RB81; - sbit at 0xC0+3 TB81; - sbit at 0xC0+4 REN1; - sbit at 0xC0+5 SM21; - sbit at 0xC0+6 SM11; - sbit at 0xC0+7 SM01; -sfr at 0xC1 SBUF1; -sfr at 0xC8 T2CON; - /* T2CON */ - sbit at 0xC8+0 CP_RL2; - sbit at 0xC8+1 C_T2; - sbit at 0xC8+2 TR2; - sbit at 0xC8+3 EXEN2; - sbit at 0xC8+4 TCLK; - sbit at 0xC8+5 RCLK; - sbit at 0xC8+6 EXF2; - sbit at 0xC8+7 TF2; -sfr at 0xCA RCAP2L; -sfr at 0xCB RCAP2H; -sfr at 0xCC TL2; -sfr at 0xCD TH2; -sfr at 0xD0 PSW; - /* PSW */ - sbit at 0xD0+0 P; - sbit at 0xD0+1 FL; - sbit at 0xD0+2 OV; - sbit at 0xD0+3 RS0; - sbit at 0xD0+4 RS1; - sbit at 0xD0+5 F0; - sbit at 0xD0+6 AC; - sbit at 0xD0+7 CY; -sfr at 0xD8 EICON; // Was WDCON in DS80C320 EICON; Bit Values differ from Reg320 - /* EICON */ - sbit at 0xD8+3 INT6; - sbit at 0xD8+4 RESI; - sbit at 0xD8+5 ERESI; - sbit at 0xD8+7 SMOD1; -sfr at 0xE0 ACC; -sfr at 0xE8 EIE; // EIE Bit Values differ from Reg320 - /* EIE */ - sbit at 0xE8+0 EIUSB; - sbit at 0xE8+1 EI2C; - sbit at 0xE8+2 EIEX4; - sbit at 0xE8+3 EIEX5; - sbit at 0xE8+4 EIEX6; -sfr at 0xF0 B; -sfr at 0xF8 EIP; // EIP Bit Values differ from Reg320 - /* EIP */ - sbit at 0xF8+0 PUSB; - sbit at 0xF8+1 PI2C; - sbit at 0xF8+2 EIPX4; - sbit at 0xF8+3 EIPX5; - sbit at 0xF8+4 EIPX6; - -/*----------------------------------------------------------------------------- - Bit Masks ------------------------------------------------------------------------------*/ - -#define bmBIT0 1 -#define bmBIT1 2 -#define bmBIT2 4 -#define bmBIT3 8 -#define bmBIT4 16 -#define bmBIT5 32 -#define bmBIT6 64 -#define bmBIT7 128 - -/* CPU Control & Status Register (CPUCS) */ -#define bmPRTCSTB bmBIT5 -#define bmCLKSPD (bmBIT4 | bmBIT3) -#define bmCLKSPD1 bmBIT4 -#define bmCLKSPD0 bmBIT3 -#define bmCLKINV bmBIT2 -#define bmCLKOE bmBIT1 -#define bm8051RES bmBIT0 -/* Port Alternate Configuration Registers */ -/* Port A (PORTACFG) */ -#define bmFLAGD bmBIT7 -#define bmINT1 bmBIT1 -#define bmINT0 bmBIT0 -/* Port C (PORTCCFG) */ -#define bmGPIFA7 bmBIT7 -#define bmGPIFA6 bmBIT6 -#define bmGPIFA5 bmBIT5 -#define bmGPIFA4 bmBIT4 -#define bmGPIFA3 bmBIT3 -#define bmGPIFA2 bmBIT2 -#define bmGPIFA1 bmBIT1 -#define bmGPIFA0 bmBIT0 -/* Port E (PORTECFG) */ -#define bmGPIFA8 bmBIT7 -#define bmT2EX bmBIT6 -#define bmINT6 bmBIT5 -#define bmRXD1OUT bmBIT4 -#define bmRXD0OUT bmBIT3 -#define bmT2OUT bmBIT2 -#define bmT1OUT bmBIT1 -#define bmT0OUT bmBIT0 - -/* I2C Control & Status Register (I2CS) */ -#define bmSTART bmBIT7 -#define bmSTOP bmBIT6 -#define bmLASTRD bmBIT5 -#define bmID (bmBIT4 | bmBIT3) -#define bmBERR bmBIT2 -#define bmACK bmBIT1 -#define bmDONE bmBIT0 -/* I2C Control Register (I2CTL) */ -#define bmSTOPIE bmBIT1 -#define bm400KHZ bmBIT0 -/* Interrupt 2 (USB) Autovector Register (INT2IVEC) */ -#define bmIV4 bmBIT6 -#define bmIV3 bmBIT5 -#define bmIV2 bmBIT4 -#define bmIV1 bmBIT3 -#define bmIV0 bmBIT2 -/* USB Interrupt Request & Enable Registers (USBIE/USBIRQ) */ -#define bmEP0ACK bmBIT6 -#define bmHSGRANT bmBIT5 -#define bmURES bmBIT4 -#define bmSUSP bmBIT3 -#define bmSUTOK bmBIT2 -#define bmSOF bmBIT1 -#define bmSUDAV bmBIT0 -/* Breakpoint register (BREAKPT) */ -#define bmBREAK bmBIT3 -#define bmBPPULSE bmBIT2 -#define bmBPEN bmBIT1 -/* Interrupt 2 & 4 Setup (INTSETUP) */ -#define bmAV2EN bmBIT3 -#define bmINT4IN bmBIT1 -#define bmAV4EN bmBIT0 -/* USB Control & Status Register (USBCS) */ -#define bmHSM bmBIT7 -#define bmDISCON bmBIT3 -#define bmNOSYNSOF bmBIT2 -#define bmRENUM bmBIT1 -#define bmSIGRESUME bmBIT0 -/* Wakeup Control and Status Register (WAKEUPCS) */ -#define bmWU2 bmBIT7 -#define bmWU bmBIT6 -#define bmWU2POL bmBIT5 -#define bmWUPOL bmBIT4 -#define bmDPEN bmBIT2 -#define bmWU2EN bmBIT1 -#define bmWUEN bmBIT0 -/* End Point 0 Control & Status Register (EP0CS) */ -#define bmHSNAK bmBIT7 -/* End Point 0-1 Control & Status Registers (EP0CS/EP1OUTCS/EP1INCS) */ -#define bmEPBUSY bmBIT1 -#define bmEPSTALL bmBIT0 -/* End Point 2-8 Control & Status Registers (EP2CS/EP4CS/EP6CS/EP8CS) */ -#define bmNPAK (bmBIT6 | bmBIT5 | bmBIT4) -#define bmEPFULL bmBIT3 -#define bmEPEMPTY bmBIT2 -/* Endpoint Status (EP2468STAT) SFR bits */ -#define bmEP8FULL bmBIT7 -#define bmEP8EMPTY bmBIT6 -#define bmEP6FULL bmBIT5 -#define bmEP6EMPTY bmBIT4 -#define bmEP4FULL bmBIT3 -#define bmEP4EMPTY bmBIT2 -#define bmEP2FULL bmBIT1 -#define bmEP2EMPTY bmBIT0 -/* SETUP Data Pointer Auto Mode (SUDPTRCTL) */ -#define bmSDPAUTO bmBIT0 -/* Endpoint Data Toggle Control (TOGCTL) */ -#define bmQUERYTOGGLE bmBIT7 -#define bmSETTOGGLE bmBIT6 -#define bmRESETTOGGLE bmBIT5 -#define bmTOGCTLEPMASK bmBIT3 | bmBIT2 | bmBIT1 | bmBIT0 -/* IBN (In Bulk Nak) enable and request bits (IBNIE/IBNIRQ) */ -#define bmEP8IBN bmBIT5 -#define bmEP6IBN bmBIT4 -#define bmEP4IBN bmBIT3 -#define bmEP2IBN bmBIT2 -#define bmEP1IBN bmBIT1 -#define bmEP0IBN bmBIT0 - -/* PING-NAK enable and request bits (NAKIE/NAKIRQ) */ -#define bmEP8PING bmBIT7 -#define bmEP6PING bmBIT6 -#define bmEP4PING bmBIT5 -#define bmEP2PING bmBIT4 -#define bmEP1PING bmBIT3 -#define bmEP0PING bmBIT2 -#define bmIBN bmBIT0 - -/* Interface Configuration bits (IFCONFIG) */ -#define bmIFCLKSRC bmBIT7 // set == INTERNAL -#define bm3048MHZ bmBIT6 // set == 48 MHz -#define bmIFCLKOE bmBIT5 -#define bmIFCLKPOL bmBIT4 -#define bmASYNC bmBIT3 -#define bmGSTATE bmBIT2 -#define bmIFCFG1 bmBIT1 -#define bmIFCFG0 bmBIT0 -#define bmIFCFGMASK (bmIFCFG0 | bmIFCFG1) -#define bmIFGPIF bmIFCFG1 - -/* EP 2468 FIFO Configuration bits (EP2FIFOCFG,EP4FIFOCFG,EP6FIFOCFG,EP8FIFOCFG) */ -#define bmINFM bmBIT6 -#define bmOEP bmBIT5 -#define bmAUTOOUT bmBIT4 -#define bmAUTOIN bmBIT3 -#define bmZEROLENIN bmBIT2 -// must be zero bmBIT1 -#define bmWORDWIDE bmBIT0 - -/* - * Chip Revision Control Bits (REVCTL) - used to ebable/disable revision specific features - */ -#define bmNOAUTOARM bmBIT1 // these don't match the docs -#define bmSKIPCOMMIT bmBIT0 // these don't match the docs - -#define bmDYN_OUT bmBIT1 // these do... -#define bmENH_PKT bmBIT0 - - -/* Fifo Reset bits (FIFORESET) */ -#define bmNAKALL bmBIT7 - -/* Endpoint Configuration (EPxCFG) */ -#define bmVALID bmBIT7 -#define bmIN bmBIT6 -#define bmTYPE1 bmBIT5 -#define bmTYPE0 bmBIT4 -#define bmISOCHRONOUS bmTYPE0 -#define bmBULK bmTYPE1 -#define bmINTERRUPT (bmTYPE1 | bmTYPE0) -#define bm1KBUF bmBIT3 -#define bmBUF1 bmBIT1 -#define bmBUF0 bmBIT0 -#define bmQUADBUF 0 -#define bmINVALIDBUF bmBUF0 -#define bmDOUBLEBUF bmBUF1 -#define bmTRIPLEBUF (bmBUF1 | bmBUF0) - -/* OUTPKTEND */ -#define bmSKIP bmBIT7 // low 4 bits specify which end point - -/* GPIFTRIG defs */ -#define bmGPIF_IDLE bmBIT7 // status bit - -#define bmGPIF_EP2_START 0 -#define bmGPIF_EP4_START 1 -#define bmGPIF_EP6_START 2 -#define bmGPIF_EP8_START 3 -#define bmGPIF_READ bmBIT2 -#define bmGPIF_WRITE 0 - -/* EXIF bits */ -#define bmEXIF_USBINT bmBIT4 -#define bmEXIF_I2CINT bmBIT5 -#define bmEXIF_IE4 bmBIT6 -#define bmEXIF_IE5 bmBIT7 - - -#endif /* FX2REGS_H */ diff --git a/firmware/fx2/include/fx2utils.h b/firmware/fx2/include/fx2utils.h deleted file mode 100644 index b184dec27..000000000 --- a/firmware/fx2/include/fx2utils.h +++ /dev/null @@ -1,31 +0,0 @@ -/* -*- c -*- */ -/* - * Copyright 2003 Free Software Foundation, Inc. - * - * This file is part of GNU Radio - * - * GNU Radio is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3, or (at your option) - * any later version. - * - * GNU Radio is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with GNU Radio; see the file COPYING. If not, write to - * the Free Software Foundation, Inc., 51 Franklin Street, - * Boston, MA 02110-1301, USA. - */ -#ifndef _FX2UTILS_H_ -#define _FX2UTILS_H_ - -void fx2_stall_ep0 (void); -void fx2_reset_data_toggle (unsigned char ep); -void fx2_renumerate (void); - - - -#endif /* _FX2UTILS_H_ */ diff --git a/firmware/fx2/include/generate_regs.py b/firmware/fx2/include/generate_regs.py deleted file mode 100755 index 656cd5e81..000000000 --- a/firmware/fx2/include/generate_regs.py +++ /dev/null @@ -1,57 +0,0 @@ -#!/usr/bin/env python - -import os, os.path -import re -import sys - - -# set srcdir to the directory that contains Makefile.am -try: - srcdir = os.environ['srcdir'] -except KeyError, e: - srcdir = "." -srcdir = srcdir + '/' - -def open_src (name, mode): - global srcdir - return open (os.path.join (srcdir, name), mode) - - -def generate_fpga_regs (h_filename, v_filename): - const_width = 7 # bit width of constants - - h_file = open_src (h_filename, 'r') - v_file = open (v_filename, 'w') - v_file.write ( - '''// -// This file is machine generated from %s -// Do not edit by hand; your edits will be overwritten. -// -''' % (h_filename,)) - - pat = re.compile (r'^#define\s*(FR_\w*)\s*(\w*)(.*)$') - pat_bitno = re.compile (r'^#define\s*(bitno\w*)\s*(\w*)(.*)$') - pat_bm = re.compile (r'^#define\s*(bm\w*)\s*(\w*)(.*)$') - for line in h_file: - if re.match ('//|\s*$', line): # comment or blank line - v_file.write (line) - mo = pat.search (line) - mo_bitno =pat_bitno.search (line) - mo_bm =pat_bm.search (line) - if mo: - v_file.write ('`define %-25s %d\'d%s%s\n' % ( - mo.group (1), const_width, mo.group (2), mo.group (3))) - elif mo_bitno: - v_file.write ('`define %-25s %s%s\n' % ( - mo_bitno.group (1), mo_bitno.group (2), mo_bitno.group (3))) - elif mo_bm: - v_file.write ('`define %-25s %s%s\n' % ( - mo_bm.group (1), mo_bm.group (2), mo_bm.group (3))) - - -if __name__ == '__main__': - if len (sys.argv) != 3: - sys.stderr.write ('usage: %s file.h file.v\n' % (sys.argv[0])) - sys.exit (1) - generate_fpga_regs (sys.argv[1], sys.argv[2]) - diff --git a/firmware/fx2/include/i2c.h b/firmware/fx2/include/i2c.h deleted file mode 100644 index 273526dad..000000000 --- a/firmware/fx2/include/i2c.h +++ /dev/null @@ -1,32 +0,0 @@ -/* -*- c++ -*- */ -/* - * Copyright 2003 Free Software Foundation, Inc. - * - * This file is part of GNU Radio - * - * GNU Radio is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3, or (at your option) - * any later version. - * - * GNU Radio is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with GNU Radio; see the file COPYING. If not, write to - * the Free Software Foundation, Inc., 51 Franklin Street, - * Boston, MA 02110-1301, USA. - */ - -#ifndef _I2C_H_ -#define _I2C_H_ - -// returns non-zero if successful, else 0 -unsigned char i2c_read (unsigned char addr, xdata unsigned char *buf, unsigned char len); - -// returns non-zero if successful, else 0 -unsigned char i2c_write (unsigned char addr, xdata const unsigned char *buf, unsigned char len); - -#endif /* _I2C_H_ */ diff --git a/firmware/fx2/include/isr.h b/firmware/fx2/include/isr.h deleted file mode 100644 index 856532890..000000000 --- a/firmware/fx2/include/isr.h +++ /dev/null @@ -1,172 +0,0 @@ -/* -*- c++ -*- */ -/* - * Copyright 2003 Free Software Foundation, Inc. - * - * This file is part of GNU Radio - * - * GNU Radio is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3, or (at your option) - * any later version. - * - * GNU Radio is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with GNU Radio; see the file COPYING. If not, write to - * the Free Software Foundation, Inc., 51 Franklin Street, - * Boston, MA 02110-1301, USA. - */ - -#ifndef _ISR_H_ -#define _ISR_H_ - -/* - * ---------------------------------------------------------------- - * routines for managing interrupt services routines - * ---------------------------------------------------------------- - */ - -/* - * The FX2 has three discrete sets of interrupt vectors. - * The first set is the standard 8051 vector (13 8-byte entries). - * The second set is USB interrupt autovector (32 4-byte entries). - * The third set is the FIFO/GPIF autovector (14 4-byte entries). - * - * Since all the code we're running in the FX2 is ram based, we - * forego the typical "initialize the interrupt vectors at link time" - * strategy, in favor of calls at run time that install the correct - * pointers to functions. - */ - -/* - * Standard Vector numbers - */ - -#define SV_INT_0 0x03 -#define SV_TIMER_0 0x0b -#define SV_INT_1 0x13 -#define SV_TIMER_1 0x1b -#define SV_SERIAL_0 0x23 -#define SV_TIMER_2 0x2b -#define SV_RESUME 0x33 -#define SV_SERIAL_1 0x3b -#define SV_INT_2 0x43 // (INT_2) points at USB autovector -#define SV_I2C 0x4b -#define SV_INT_4 0x53 // (INT_4) points at FIFO/GPIF autovector -#define SV_INT_5 0x5b -#define SV_INT_6 0x63 - -#define SV_MIN SV_INT_0 -#define SV_MAX SV_INT_6 - -/* - * USB Auto Vector numbers - */ - -#define UV_SUDAV 0x00 -#define UV_SOF 0x04 -#define UV_SUTOK 0x08 -#define UV_SUSPEND 0x0c -#define UV_USBRESET 0x10 -#define UV_HIGHSPEED 0x14 -#define UV_EP0ACK 0x18 -#define UV_SPARE_1C 0x1c -#define UV_EP0IN 0x20 -#define UV_EP0OUT 0x24 -#define UV_EP1IN 0x28 -#define UV_EP1OUT 0x2c -#define UV_EP2 0x30 -#define UV_EP4 0x34 -#define UV_EP6 0x38 -#define UV_EP8 0x3c -#define UV_IBN 0x40 -#define UV_SPARE_44 0x44 -#define UV_EP0PINGNAK 0x48 -#define UV_EP1PINGNAK 0x4c -#define UV_EP2PINGNAK 0x50 -#define UV_EP4PINGNAK 0x54 -#define UV_EP6PINGNAK 0x58 -#define UV_EP8PINGNAK 0x5c -#define UV_ERRLIMIT 0x60 -#define UV_SPARE_64 0x64 -#define UV_SPARE_68 0x68 -#define UV_SPARE_6C 0x6c -#define UV_EP2ISOERR 0x70 -#define UV_EP4ISOERR 0x74 -#define UV_EP6ISOERR 0x78 -#define UV_EP8ISOERR 0x7c - -#define UV_MIN UV_SUDAV -#define UV_MAX UV_EP8ISOERR - -/* - * FIFO/GPIF Auto Vector numbers - */ - -#define FGV_EP2PF 0x00 -#define FGV_EP4PF 0x04 -#define FGV_EP6PF 0x08 -#define FGV_EP8PF 0x0c -#define FGV_EP2EF 0x10 -#define FGV_EP4EF 0x14 -#define FGV_EP6EF 0x18 -#define FGV_EP8EF 0x1c -#define FGV_EP2FF 0x20 -#define FGV_EP4FF 0x24 -#define FGV_EP6FF 0x28 -#define FGV_EP8FF 0x2c -#define FGV_GPIFDONE 0x30 -#define FGV_GPIFWF 0x34 - -#define FGV_MIN FGV_EP2PF -#define FGV_MAX FGV_GPIFWF - - -/* - * Hook standard interrupt vector. - * - * vector_number is from the SV_<foo> list above. - * addr is the address of the interrupt service routine. - */ -void hook_sv (unsigned char vector_number, unsigned short addr); - -/* - * Hook usb interrupt vector. - * - * vector_number is from the UV_<foo> list above. - * addr is the address of the interrupt service routine. - */ -void hook_uv (unsigned char vector_number, unsigned short addr); - -/* - * Hook fifo/gpif interrupt vector. - * - * vector_number is from the FGV_<foo> list above. - * addr is the address of the interrupt service routine. - */ -void hook_fgv (unsigned char vector_number, unsigned short addr); - -/* - * One time call to enable autovectoring for both USB and FIFO/GPIF - */ -void setup_autovectors (void); - - -/* - * Must be called in each usb interrupt handler - */ -#define clear_usb_irq() \ - EXIF &= ~bmEXIF_USBINT; \ - INT2CLR = 0 - -/* - * Must be calledin each fifo/gpif interrupt handler - */ -#define clear_fifo_gpif_irq() \ - EXIF &= ~bmEXIF_IE4; \ - INT4CLR = 0 - -#endif /* _ISR_H_ */ diff --git a/firmware/fx2/include/syncdelay.h b/firmware/fx2/include/syncdelay.h deleted file mode 100644 index 0af7d099f..000000000 --- a/firmware/fx2/include/syncdelay.h +++ /dev/null @@ -1,65 +0,0 @@ -/* -*- c++ -*- */ -/* - * Copyright 2003 Free Software Foundation, Inc. - * - * This file is part of GNU Radio - * - * GNU Radio is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3, or (at your option) - * any later version. - * - * GNU Radio is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with GNU Radio; see the file COPYING. If not, write to - * the Free Software Foundation, Inc., 51 Franklin Street, - * Boston, MA 02110-1301, USA. - */ -#ifndef _SYNCDELAY_H_ -#define _SYNCDELAY_H_ - -/* - * Magic delay required between access to certain xdata registers (TRM page 15-106). - * For our configuration, 48 MHz FX2 / 48 MHz IFCLK, we need three cycles. Each - * NOP is a single cycle.... - * - * From TRM page 15-105: - * - * Under certain conditions, some read and write access to the FX2 registers must - * be separated by a "synchronization delay". The delay is necessary only under the - * following conditions: - * - * - between a write to any register in the 0xE600 - 0xE6FF range and a write to one - * of the registers listed below. - * - * - between a write to one of the registers listed below and a read from any register - * in the 0xE600 - 0xE6FF range. - * - * Registers which require a synchronization delay: - * - * FIFORESET FIFOPINPOLAR - * INPKTEND EPxBCH:L - * EPxFIFOPFH:L EPxAUTOINLENH:L - * EPxFIFOCFG EPxGPIFFLGSEL - * PINFLAGSAB PINFLAGSCD - * EPxFIFOIE EPxFIFOIRQ - * GPIFIE GPIFIRQ - * UDMACRCH:L GPIFADRH:L - * GPIFTRIG EPxGPIFTRIG - * OUTPKTEND REVCTL - * GPIFTCB3 GPIFTCB2 - * GPIFTCB1 GPIFTCB0 - */ - -/* - * FIXME ensure that the peep hole optimizer isn't screwing us - */ -#define SYNCDELAY _asm nop; nop; nop; _endasm -#define NOP _asm nop; _endasm - - -#endif /* _SYNCDELAY_H_ */ diff --git a/firmware/fx2/include/timer.h b/firmware/fx2/include/timer.h deleted file mode 100644 index 3181874d5..000000000 --- a/firmware/fx2/include/timer.h +++ /dev/null @@ -1,35 +0,0 @@ -/* -*- c++ -*- */ -/* - * Copyright 2003 Free Software Foundation, Inc. - * - * This file is part of GNU Radio - * - * GNU Radio is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3, or (at your option) - * any later version. - * - * GNU Radio is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with GNU Radio; see the file COPYING. If not, write to - * the Free Software Foundation, Inc., 51 Franklin Street, - * Boston, MA 02110-1301, USA. - */ - -#ifndef _TIMER_H_ -#define _TIMER_H_ - -/* - * Arrange to have isr_tick_handler called at 100 Hz - */ -void hook_timer_tick (unsigned short isr_tick_handler); - -#define clear_timer_irq() \ - TF2 = 0 /* clear overflow flag */ - - -#endif /* _TIMER_H_ */ diff --git a/firmware/fx2/include/usb_common.h b/firmware/fx2/include/usb_common.h deleted file mode 100644 index ae07b236c..000000000 --- a/firmware/fx2/include/usb_common.h +++ /dev/null @@ -1,37 +0,0 @@ -/* -*- c -*- */ -/* - * Copyright 2003 Free Software Foundation, Inc. - * - * This file is part of GNU Radio - * - * GNU Radio is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3, or (at your option) - * any later version. - * - * GNU Radio is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with GNU Radio; see the file COPYING. If not, write to - * the Free Software Foundation, Inc., 51 Franklin Street, - * Boston, MA 02110-1301, USA. - */ - -#ifndef _USB_COMMON_H_ -#define _USB_COMMON_H_ - -extern volatile bit _usb_got_SUDAV; - -// Provided by user application to handle VENDOR commands. -// returns non-zero if it handled the command. -unsigned char app_vendor_cmd (void); - -void usb_install_handlers (void); -void usb_handle_setup_packet (void); - -#define usb_setup_packet_avail() _usb_got_SUDAV - -#endif /* _USB_COMMON_H_ */ diff --git a/firmware/fx2/include/usb_descriptors.h b/firmware/fx2/include/usb_descriptors.h deleted file mode 100644 index 0b8c6212f..000000000 --- a/firmware/fx2/include/usb_descriptors.h +++ /dev/null @@ -1,40 +0,0 @@ -/* -*- c++ -*- */ -/* - * Copyright 2003 Free Software Foundation, Inc. - * - * This file is part of GNU Radio - * - * GNU Radio is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3, or (at your option) - * any later version. - * - * GNU Radio is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with GNU Radio; see the file COPYING. If not, write to - * the Free Software Foundation, Inc., 51 Franklin Street, - * Boston, MA 02110-1301, USA. - */ - -extern xdata const char high_speed_device_descr[]; -extern xdata const char high_speed_devqual_descr[]; -extern xdata const char high_speed_config_descr[]; - -extern xdata const char full_speed_device_descr[]; -extern xdata const char full_speed_devqual_descr[]; -extern xdata const char full_speed_config_descr[]; - -extern xdata unsigned char nstring_descriptors; -extern xdata char * xdata string_descriptors[]; - -/* - * We patch these locations with info read from the usrp config eeprom - */ -extern xdata char usb_desc_hw_rev_binary_patch_location_0[]; -extern xdata char usb_desc_hw_rev_binary_patch_location_1[]; -extern xdata char usb_desc_hw_rev_ascii_patch_location_0[]; -extern xdata char usb_desc_serial_number_ascii[]; diff --git a/firmware/fx2/include/usb_requests.h b/firmware/fx2/include/usb_requests.h deleted file mode 100644 index 7a543abb0..000000000 --- a/firmware/fx2/include/usb_requests.h +++ /dev/null @@ -1,88 +0,0 @@ -/* -*- c++ -*- */ -/* - * Copyright 2003 Free Software Foundation, Inc. - * - * This file is part of GNU Radio - * - * GNU Radio is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3, or (at your option) - * any later version. - * - * GNU Radio is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with GNU Radio; see the file COPYING. If not, write to - * the Free Software Foundation, Inc., 51 Franklin Street, - * Boston, MA 02110-1301, USA. - */ - -// Standard USB requests. -// These are contained in end point 0 setup packets - - -#ifndef _USB_REQUESTS_H_ -#define _USB_REQUESTS_H_ - -// format of bmRequestType byte - -#define bmRT_DIR_MASK (0x1 << 7) -#define bmRT_DIR_IN (1 << 7) -#define bmRT_DIR_OUT (0 << 7) - -#define bmRT_TYPE_MASK (0x3 << 5) -#define bmRT_TYPE_STD (0 << 5) -#define bmRT_TYPE_CLASS (1 << 5) -#define bmRT_TYPE_VENDOR (2 << 5) -#define bmRT_TYPE_RESERVED (3 << 5) - -#define bmRT_RECIP_MASK (0x1f << 0) -#define bmRT_RECIP_DEVICE (0 << 0) -#define bmRT_RECIP_INTERFACE (1 << 0) -#define bmRT_RECIP_ENDPOINT (2 << 0) -#define bmRT_RECIP_OTHER (3 << 0) - - -// standard request codes (bRequest) - -#define RQ_GET_STATUS 0 -#define RQ_CLEAR_FEATURE 1 -#define RQ_RESERVED_2 2 -#define RQ_SET_FEATURE 3 -#define RQ_RESERVED_4 4 -#define RQ_SET_ADDRESS 5 -#define RQ_GET_DESCR 6 -#define RQ_SET_DESCR 7 -#define RQ_GET_CONFIG 8 -#define RQ_SET_CONFIG 9 -#define RQ_GET_INTERFACE 10 -#define RQ_SET_INTERFACE 11 -#define RQ_SYNCH_FRAME 12 - -// standard descriptor types - -#define DT_DEVICE 1 -#define DT_CONFIG 2 -#define DT_STRING 3 -#define DT_INTERFACE 4 -#define DT_ENDPOINT 5 -#define DT_DEVQUAL 6 -#define DT_OTHER_SPEED 7 -#define DT_INTERFACE_POWER 8 - -// standard feature selectors - -#define FS_ENDPOINT_HALT 0 // recip: endpoint -#define FS_DEV_REMOTE_WAKEUP 1 // recip: device -#define FS_TEST_MODE 2 // recip: device - -// Get Status device attributes - -#define bmGSDA_SELF_POWERED 0x01 -#define bmGSDA_REM_WAKEUP 0x02 - - -#endif /* _USB_REQUESTS_H_ */ diff --git a/firmware/fx2/include/usrp_commands.h b/firmware/fx2/include/usrp_commands.h deleted file mode 100644 index 02778c7e3..000000000 --- a/firmware/fx2/include/usrp_commands.h +++ /dev/null @@ -1,106 +0,0 @@ -/* - * USRP - Universal Software Radio Peripheral - * - * Copyright (C) 2003,2004 Free Software Foundation, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA - */ - -#ifndef _USRP_COMMANDS_H_ -#define _USRP_COMMANDS_H_ - -#include <usrp_interfaces.h> -#include <usrp_spi_defs.h> - -#define MAX_EP0_PKTSIZE 64 // max size of EP0 packet on FX2 - -// ---------------------------------------------------------------- -// Vendor bmRequestType's -// ---------------------------------------------------------------- - -#define VRT_VENDOR_IN 0xC0 -#define VRT_VENDOR_OUT 0x40 - -// ---------------------------------------------------------------- -// USRP Vendor Requests -// -// Note that Cypress reserves [0xA0,0xAF]. -// 0xA0 is the firmware load function. -// ---------------------------------------------------------------- - - -// IN commands - -#define VRQ_GET_STATUS 0x80 -#define GS_TX_UNDERRUN 0 // wIndexL // returns 1 byte -#define GS_RX_OVERRUN 1 // wIndexL // returns 1 byte - -#define VRQ_I2C_READ 0x81 // wValueL: i2c address; length: how much to read - -#define VRQ_SPI_READ 0x82 // wValue: optional header bytes - // wIndexH: enables - // wIndexL: format - // len: how much to read - -#define VRQ_SPI_TRANSACT 0x83 // wValueH: OUT byte 0 - // wValueL: OUT byte 1 - // wIndexH: OUT byte 2 - // wIndexL: OUT byte 3 - // wLengthH: enables - // wLengthL: transaction length - -// OUT commands - -#define VRQ_SET_LED 0x01 // wValueL off/on {0,1}; wIndexL: which {0,1} - -#define VRQ_FPGA_LOAD 0x02 -# define FL_BEGIN 0 // wIndexL: begin fpga programming cycle. stalls if trouble. -# define FL_XFER 1 // wIndexL: xfer up to 64 bytes of data -# define FL_END 2 // wIndexL: end programming cycle, check for success. - // stalls endpoint if trouble. - -#define VRQ_FPGA_WRITE_REG 0x03 // wIndexL: regno; data: 32-bit regval MSB first -#define VRQ_FPGA_SET_RESET 0x04 // wValueL: {0,1} -#define VRQ_FPGA_SET_TX_ENABLE 0x05 // wValueL: {0,1} -#define VRQ_FPGA_SET_RX_ENABLE 0x06 // wValueL: {0,1} -// see below VRQ_FPGA_SET_{TX,RX}_RESET - -#define VRQ_SET_SLEEP_BITS 0x07 // wValueH: mask; wValueL: bits. set bits given by mask to bits - -# define SLEEP_ADC0 0x01 -# define SLEEP_ADC1 0x02 -# define SLEEP_DAC0 0x04 -# define SLEEP_DAC1 0x08 - -#define VRQ_I2C_WRITE 0x08 // wValueL: i2c address; data: data - -#define VRQ_SPI_WRITE 0x09 // wValue: optional header bytes - // wIndexH: enables - // wIndexL: format - // len: how much to write - -#define VRQ_FPGA_SET_TX_RESET 0x0a // wValueL: {0, 1} -#define VRQ_FPGA_SET_RX_RESET 0x0b // wValueL: {0, 1} - - -// ------------------------------------------------------------------- -// we store the hashes at fixed addresses in the FX2 internal memory - -#define USRP_HASH_SLOT_0_ADDR 0xe1e0 -#define USRP_HASH_SLOT_1_ADDR 0xe1f0 - - - -#endif /* _USRP_COMMANDS_H_ */ diff --git a/firmware/fx2/include/usrp_config.h b/firmware/fx2/include/usrp_config.h deleted file mode 100644 index e77f8e4c5..000000000 --- a/firmware/fx2/include/usrp_config.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * USRP - Universal Software Radio Peripheral - * - * Copyright (C) 2003 Free Software Foundation, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA - */ - -/* - * configuration stuff for debugging - */ - -/* - * Define to 0 for normal use of port A, i.e., FPGA control bus. - * Define to 1 to write trace to port A for scoping with logic analyzer. - */ -#define UC_TRACE_USING_PORT_A 0 - - -/* - * Define to 0 for normal use of low 3 bits of port E, i.e., A/D, D/A SLEEP bits. - * Define to 1 to enable by default driving the GPIF state to the - * low three bits of port E. - */ -#define UC_START_WITH_GSTATE_OUTPUT_ENABLED 0 - - -/* - * Define to 1 for normal use (the board really has an FPGA on it). - * Define to 0 for debug use on board without FPGA. - */ -#define UC_BOARD_HAS_FPGA 1 diff --git a/firmware/fx2/include/usrp_i2c_addr.h b/firmware/fx2/include/usrp_i2c_addr.h deleted file mode 100644 index 0a4f3ea59..000000000 --- a/firmware/fx2/include/usrp_i2c_addr.h +++ /dev/null @@ -1,78 +0,0 @@ -/* -*- c++ -*- */ -/* - * Copyright 2004 Free Software Foundation, Inc. - * - * This file is part of GNU Radio - * - * GNU Radio is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3, or (at your option) - * any later version. - * - * GNU Radio is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with GNU Radio; see the file COPYING. If not, write to - * the Free Software Foundation, Inc., 51 Franklin Street, - * Boston, MA 02110-1301, USA. - */ -#ifndef INCLUDED_USRP_I2C_ADDR_H -#define INCLUDED_USRP_I2C_ADDR_H - -// I2C addresses - -#define I2C_DEV_EEPROM 0x50 // 24LC02[45]: 7-bits 1010xxx - -#define I2C_ADDR_BOOT (I2C_DEV_EEPROM | 0x0) -#define I2C_ADDR_TX_A (I2C_DEV_EEPROM | 0x4) -#define I2C_ADDR_RX_A (I2C_DEV_EEPROM | 0x5) -#define I2C_ADDR_TX_B (I2C_DEV_EEPROM | 0x6) -#define I2C_ADDR_RX_B (I2C_DEV_EEPROM | 0x7) - - -// format of FX2 BOOT EEPROM -// 00: 0xC0 code for ``Read IDs from EEPROM'' -// 01: 0xFE USB Vendor ID (LSB) -// 02: 0xFF USB Vendor ID (MSB) -// 03: 0x02 USB Product ID (LSB) -// 04: 0x00 USB Product ID (MSB) -// 05: 0x01 USB Device ID (LSB) // rev1 -// 06: 0x00 USB Device ID (MSB) // 0 = unconfig'd (no firmware) -// 07: 0x00 option byte - - -// format of daughterboard EEPROM -// 00: 0xDB code for ``I'm a daughterboard'' -// 01: .. Daughterboard ID (LSB) -// 02: .. Daughterboard ID (MSB) -// 03: .. io bits 7-0 direction (bit set if it's an output from m'board) -// 04: .. io bits 15-8 direction (bit set if it's an output from m'board) -// 05: .. ADC0 DC offset correction (LSB) -// 06: .. ADC0 DC offset correction (MSB) -// 07: .. ADC1 DC offset correction (LSB) -// 08: .. ADC1 DC offset correction (MSB) -// ... -// 1f: .. negative of the sum of bytes [0x00, 0x1e] - -#define DB_EEPROM_MAGIC 0x00 -#define DB_EEPROM_MAGIC_VALUE 0xDB -#define DB_EEPROM_ID_LSB 0x01 -#define DB_EEPROM_ID_MSB 0x02 -#define DB_EEPROM_OE_LSB 0x03 -#define DB_EEPROM_OE_MSB 0x04 -#define DB_EEPROM_OFFSET_0_LSB 0x05 // offset correction for ADC or DAC 0 -#define DB_EEPROM_OFFSET_0_MSB 0x06 -#define DB_EEPROM_OFFSET_1_LSB 0x07 // offset correction for ADC or DAC 1 -#define DB_EEPROM_OFFSET_1_MSB 0x08 -#define DB_EEPROM_CHKSUM 0x1f - -#define DB_EEPROM_CLEN 0x20 // length of common portion of eeprom - -#define DB_EEPROM_CUSTOM_BASE DB_EEPROM_CLEN // first avail offset for - // daughterboard specific use - -#endif /* INCLUDED_USRP_I2C_ADDR_H */ - diff --git a/firmware/fx2/include/usrp_ids.h b/firmware/fx2/include/usrp_ids.h deleted file mode 100644 index 46a069434..000000000 --- a/firmware/fx2/include/usrp_ids.h +++ /dev/null @@ -1,68 +0,0 @@ -/* -*- c++ -*- */ -/* - * Copyright 2003,2006,2007 Free Software Foundation, Inc. - * - * This file is part of GNU Radio - * - * GNU Radio is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3, or (at your option) - * any later version. - * - * GNU Radio is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with GNU Radio; see the file COPYING. If not, write to - * the Free Software Foundation, Inc., 51 Franklin Street, - * Boston, MA 02110-1301, USA. - */ - -/* - * USB Vendor and Product IDs that we use - * - * (keep in sync with usb_descriptors.a51) - */ - -#ifndef _USRP_IDS_H_ -#define _USRP_IDS_H_ - -#define USB_VID_CYPRESS 0x04b4 -#define USB_PID_CYPRESS_FX2 0x8613 - - -#define USB_VID_FSF 0xfffe // Free Software Folks -#define USB_PID_FSF_EXP_0 0x0000 // Experimental 0 -#define USB_PID_FSF_EXP_1 0x0001 // Experimental 1 -#define USB_PID_FSF_USRP 0x0002 // Universal Software Radio Peripheral -#define USB_PID_FSF_USRP_reserved 0x0003 // Universal Software Radio Peripheral -#define USB_PID_FSF_SSRP 0x0004 // Simple Software Radio Peripheral -#define USB_PID_FSF_SSRP_reserved 0x0005 // Simple Software Radio Peripheral -#define USB_PID_FSF_HPSDR 0x0006 // High Performance Software Defined Radio (Internal Boot) -#define USB_PID_FSF_HPSDR_HA 0x0007 // High Performance Software Defined Radio (Host Assisted Boot) -#define USB_PID_FSF_QS1R 0x0008 // QS1R HF receiver -#define USB_PID_FSF_EZDOP 0x0009 // ezdop <jcorgan@aeinet.com> -#define USB_PID_FSF_BDALE_0 0x000a // Bdale Garbee <bdale@gag.com> -#define USB_PID_FSF_BDALE_1 0x000b // Bdale Garbee <bdale@gag.com> -#define USB_PID_FSF_BDALE_2 0x000c // Bdale Garbee <bdale@gag.com> -#define USB_PID_FSF_BDALE_3 0x000d // Bdale Garbee <bdale@gag.com> -#define USB_PID_FSF_BDALE_4 0x000e // Bdale Garbee <bdale@gag.com> -#define USB_PID_FSF_BDALE_5 0x000f // Bdale Garbee <bdale@gag.com> -#define USB_PID_FSF_BDALE_6 0x0010 // Bdale Garbee <bdale@gag.com> -#define USB_PID_FSF_BDALE_7 0x0011 // Bdale Garbee <bdale@gag.com> -#define USB_PID_FSF_BDALE_8 0x0012 // Bdale Garbee <bdale@gag.com> -#define USB_PID_FSF_BDALE_9 0x0013 // Bdale Garbee <bdale@gag.com> -#define USB_PID_FSF_HPSDR_HERMES 0x0014 // HPSDR Hermes -#define USB_PID_FSF_THINKRF 0x0015 // Catalin Patulea <catalin.patulea@thinkrf.com> -#define USB_PID_FSF_MSA 0x0016 // Hans de Bok <hdbok@dionaea.demon.nl> Scotty's Modular Spectrum Analyzer - -#define USB_PID_FSF_LBNL_UXO 0x0018 // http://recycle.lbl.gov/~ldoolitt/uxo/ - - -#define USB_DID_USRP_0 0x0000 // unconfigured rev 0 USRP -#define USB_DID_USRP_1 0x0001 // unconfigured rev 1 USRP -#define USB_DID_USRP_2 0x0002 // unconfigured rev 2 USRP - -#endif /* _USRP_IDS_H_ */ diff --git a/firmware/fx2/include/usrp_interfaces.h b/firmware/fx2/include/usrp_interfaces.h deleted file mode 100644 index 8666e0490..000000000 --- a/firmware/fx2/include/usrp_interfaces.h +++ /dev/null @@ -1,47 +0,0 @@ -/* -*- c++ -*- */ -/* - * Copyright 2003 Free Software Foundation, Inc. - * - * This file is part of GNU Radio - * - * GNU Radio is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3, or (at your option) - * any later version. - * - * GNU Radio is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with GNU Radio; see the file COPYING. If not, write to - * the Free Software Foundation, Inc., 51 Franklin Street, - * Boston, MA 02110-1301, USA. - */ - -#ifndef _USRP_INTERFACES_H_ -#define _USRP_INTERFACES_H_ - -/* - * We've now split the USRP into 3 separate interfaces. - * - * Interface 0 contains only ep0 and is used for command and status. - * Interface 1 is the Tx path and it uses ep2 OUT BULK. - * Interface 2 is the Rx path and it uses ep6 IN BULK. - */ - -#define USRP_CMD_INTERFACE 0 -#define USRP_CMD_ALTINTERFACE 0 -#define USRP_CMD_ENDPOINT 0 - -#define USRP_TX_INTERFACE 1 -#define USRP_TX_ALTINTERFACE 0 -#define USRP_TX_ENDPOINT 2 // streaming data from host to FPGA - -#define USRP_RX_INTERFACE 2 -#define USRP_RX_ALTINTERFACE 0 -#define USRP_RX_ENDPOINT 6 // streaming data from FPGA to host - - -#endif /* _USRP_INTERFACES_H_ */ diff --git a/firmware/fx2/include/usrp_spi_defs.h b/firmware/fx2/include/usrp_spi_defs.h deleted file mode 100644 index 963463ef2..000000000 --- a/firmware/fx2/include/usrp_spi_defs.h +++ /dev/null @@ -1,86 +0,0 @@ -/* -*- c++ -*- */ -/* - * Copyright 2004 Free Software Foundation, Inc. - * - * This file is part of GNU Radio - * - * GNU Radio is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3, or (at your option) - * any later version. - * - * GNU Radio is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with GNU Radio; see the file COPYING. If not, write to - * the Free Software Foundation, Inc., 51 Franklin Street, - * Boston, MA 02110-1301, USA. - */ - -#ifndef INCLUDED_USRP_SPI_DEFS_H -#define INCLUDED_USRP_SPI_DEFS_H - -/* - * defines for the VRQ_SPI_READ and VRQ_SPI_WRITE commands - * - * SPI == "Serial Port Interface". SPI is a 3 wire bus plus a - * separate enable for each peripheral. The common lines are SCLK, - * SDI and SDO. The FX2 always drives SCLK and SDI, the clock and - * data lines from the FX2 to the peripheral. When enabled, a - * peripheral may drive SDO, the data line from the peripheral to the - * FX2. - * - * The SPI_READ and SPI_WRITE commands are formatted identically. - * Each specifies which peripherals to enable, whether the bits should - * be transmistted Most Significant Bit first or Least Significant Bit - * first, the number of bytes in the optional header, and the number - * of bytes to read or write in the body. - * - * The body is limited to 64 bytes. The optional header may contain - * 0, 1 or 2 bytes. For an SPI_WRITE, the header bytes are - * transmitted to the peripheral followed by the the body bytes. For - * an SPI_READ, the header bytes are transmitted to the peripheral, - * then len bytes are read back from the peripheral. - */ - -/* - * SPI_FMT_* goes in wIndexL - */ -#define SPI_FMT_xSB_MASK (1 << 7) -# define SPI_FMT_LSB (1 << 7) // least signficant bit first -# define SPI_FMT_MSB (0 << 7) // most significant bit first -#define SPI_FMT_HDR_MASK (3 << 5) -# define SPI_FMT_HDR_0 (0 << 5) // 0 header bytes -# define SPI_FMT_HDR_1 (1 << 5) // 1 header byte -# define SPI_FMT_HDR_2 (2 << 5) // 2 header bytes - -/* - * SPI_ENABLE_* goes in wIndexH - * - * For the software interface, the enables are active high. - * For reads, it's an error to have more than one enable set. - * - * [FWIW, the hardware implements them as active low. Don't change the - * definitions of these. They are related to usrp_rev1_regs.h] - */ -#define SPI_ENABLE_FPGA 0x01 // select FPGA -#define SPI_ENABLE_CODEC_A 0x02 // select AD9862 A -#define SPI_ENABLE_CODEC_B 0x04 // select AD9862 B -#define SPI_ENABLE_reserved 0x08 -#define SPI_ENABLE_TX_A 0x10 // select d'board TX A -#define SPI_ENABLE_RX_A 0x20 // select d'board RX A -#define SPI_ENABLE_TX_B 0x40 // select d'board TX B -#define SPI_ENABLE_RX_B 0x80 // select d'board RX B - -/* - * If there's one header byte, it goes in wValueL. - * - * If there are two header bytes, they go in wValueH | wValueL. - * The transmit order of the bytes (and bits within them) is - * determined by SPI_FMT_*SB - */ - -#endif /* INCLUDED_USRP_SPI_DEFS_H */ |