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authorJosh Blum <josh@joshknows.com>2011-06-14 17:15:38 -0700
committerJosh Blum <josh@joshknows.com>2011-06-14 17:56:54 -0700
commitdeae10bc1c85726ed7c206abca37a869c6f77cea (patch)
tree1bd8f8dc2734af460d8434e508d33ecdb9cf5fe7 /firmware/fx2/common
parent2d8d1a4d1ad15482e25f52e1fa3ad8ae94490a8e (diff)
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b100: added b100 firmware (squashed)
Diffstat (limited to 'firmware/fx2/common')
-rw-r--r--firmware/fx2/common/fx2regs.h4
-rw-r--r--firmware/fx2/common/usrp_commands.h6
2 files changed, 10 insertions, 0 deletions
diff --git a/firmware/fx2/common/fx2regs.h b/firmware/fx2/common/fx2regs.h
index 2f210f567..aa44791d0 100644
--- a/firmware/fx2/common/fx2regs.h
+++ b/firmware/fx2/common/fx2regs.h
@@ -664,6 +664,10 @@ sfr at 0xF8 EIP; // EIP Bit Values differ from Reg320
// must be zero bmBIT1
#define bmWORDWIDE bmBIT0
+/* EP 24 FIFO Flag bits (EP24FIFOFLGS) */
+#define EP2FIFOEMPTY bmBIT1
+#define EP4FIFOEMPTY bmBIT5
+
/*
* Chip Revision Control Bits (REVCTL) - used to ebable/disable revision specific features
*/
diff --git a/firmware/fx2/common/usrp_commands.h b/firmware/fx2/common/usrp_commands.h
index 20c28e264..2466729b2 100644
--- a/firmware/fx2/common/usrp_commands.h
+++ b/firmware/fx2/common/usrp_commands.h
@@ -54,6 +54,8 @@
// wIndexL: format
// len: how much to read
+#define VRQ_FW_COMPAT 0x83 //low 16 bits
+
// OUT commands
#define VRQ_SET_LED 0x01 // wValueL off/on {0,1}; wIndexL: which {0,1}
@@ -87,6 +89,10 @@
#define VRQ_FPGA_SET_TX_RESET 0x0a // wValueL: {0, 1}
#define VRQ_FPGA_SET_RX_RESET 0x0b // wValueL: {0, 1}
+#define VRQ_RESET_GPIF 0x0c
+#define VRQ_ENABLE_GPIF 0x0d
+#define VRQ_CLEAR_FPGA_FIFO 0x0e
+
// -------------------------------------------------------------------
// we store the hashes at fixed addresses in the FX2 internal memory