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authorJosh Blum <josh@joshknows.com>2010-11-05 12:32:09 -0700
committerJosh Blum <josh@joshknows.com>2010-11-05 12:32:09 -0700
commitc473cc56fafcb47d6ba1f16e8c9fb89ff6c57bca (patch)
tree4760fc8fd3f409831dda97b81b65b379abfd61fc /firmware/fx2/common/usrp_config.h
parent7a7e704fa3d79036da1f33013e761eb747b725f0 (diff)
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usrp1: pulled in cmake build system for usrp1 firmware
Diffstat (limited to 'firmware/fx2/common/usrp_config.h')
-rw-r--r--firmware/fx2/common/usrp_config.h44
1 files changed, 44 insertions, 0 deletions
diff --git a/firmware/fx2/common/usrp_config.h b/firmware/fx2/common/usrp_config.h
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+/*
+ * USRP - Universal Software Radio Peripheral
+ *
+ * Copyright (C) 2003 Free Software Foundation, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * configuration stuff for debugging
+ */
+
+/*
+ * Define to 0 for normal use of port A, i.e., FPGA control bus.
+ * Define to 1 to write trace to port A for scoping with logic analyzer.
+ */
+#define UC_TRACE_USING_PORT_A 0
+
+
+/*
+ * Define to 0 for normal use of low 3 bits of port E, i.e., A/D, D/A SLEEP bits.
+ * Define to 1 to enable by default driving the GPIF state to the
+ * low three bits of port E.
+ */
+#define UC_START_WITH_GSTATE_OUTPUT_ENABLED 0
+
+
+/*
+ * Define to 1 for normal use (the board really has an FPGA on it).
+ * Define to 0 for debug use on board without FPGA.
+ */
+#define UC_BOARD_HAS_FPGA 1